References

For reasons of consistency in this domain, the references have been organized by chapter.

Preface

  1. Darche, P. (2000). Architecture des ordinateurs – Représentation des nombres et codes – Cours avec exercices corrigés. Éditions Gaëtan Morin.
  2. Darche, P. (2002). Architecture des ordinateurs – Fonctions booléennes, logiques combinatoire et séquentielle – Cours avec exercices et exemples en VHDL. Éditions Vuibert.
  3. Darche, P. (2003). Architecture des ordinateurs – Interfaces et périphériques – Cours avec exercices corrigés. Éditions Vuibert.
  4. Darche, P. (2004). Architecture des ordinateurs – Logique booléenne: implémentations et technologies. Éditions Vuibert.
  5. Darche, P. (2012). Mémoires à semi-conducteurs: principe de fonctionnement et organisation interne des mémoires vives – Volume 1. Éditions Vuibert. One of four books selected for the AFISI (Association Française d’Ingénierie des Systèmes d’Information) prize for the best computing book 2012.

Part 1 (Chapters 1 and 2)

  1. Agrawal, V.D., Kime, C.R., and Saluja, K.K. (1993a). A tutorial on built-in self-test. Part 1: Principles. IEEE Design & Test of Computers, 10(1), 73–82.
  2. Agrawal, V.D., Kime, C.R., and Saluja, K.K. (1993b). A tutorial on built-in self-test. Part 2: Applications. IEEE Design & Test of Computers, 10(2), 69–77.
  3. Albrecht, A.J. (1979). Measuring application development productivity. Joint SHARE, GUIDE, and IBM Application Development Symposium, 83–92, October 14–17, Monterey, California, USA.
  4. Anderson, A., Cruess, M., and Wiencek, E. (1989). The binary compatibility standard. Thirty-fourth IEEE Computer Society International Conference: Intellectual Leverage (COMPCON Spring 89), 32–37, February 27, 1989–March 3, 1989.
  5. Backus, J.W., Bauer, F.L., Green, J., Katz, C., McCarthy, J., Perlis, A.J., Rutishauser, H., Samelson, K., Vauquois, B., Wegstein, J.H., van Wijngaarden, A., and Woodger, M. (1960). Report on the algorithmic language ALGOL 60. Communications of the ACM (CACM), 3(5), 299–314.
  6. Backus, J.W., Bauer, F.L., Green, J., Katz, C., McCarthy, J., Naur, P., Perlis, A.J., Rutishauser, H., Samelson, K., Vauquois, B., Wegstein, J.H., van Wijngaarden, A., and Woodger, M. (1963). Revised report on the algorithmic language Algol 60. In Communications of the ACM (CACM), Naur, P. (ed.). 6(1), 1–17.
  7. Bell, J.R. (1973). Threaded code. Communications of the ACM (CACM), 16(6), 370–372.
  8. Carson, J.H. (eds) (1979). Tutorial: Design of microprocessor systems. Tutorial Week 79, Institute of Electrical and Electronics Engineering (IEEE), December 10–14, San Diego, California, USA.
  9. Chen, H.-M., Kao, C.-F., and Huang, I.-J. (2002). Analysis of hardware and software approaches to embedded in-circuit emulation of microprocessors. Seventh Asia-Pacific Computer Systems Architecture Conference (ACSAC’2002), Melbourne, Australia. In Conferences in Research and Practice in Information Technology, 6 (CRPIT’02), Lai, F. and Morris, J. (eds), 127–133. Australian Computer Science Communications, 24(3).
  10. Cohen, D. (1981). On holy wars and a plea for peace. IEEE Computer, 14(10), 48–54. Original: Internet Engineering Note (IEN) 137. USC/ISI (University of Southern California /Information Sciences Institute). April 1, 1980.
  11. Crookes, D. (1983). Teaching assembly-language programming: A high-level approach. Software & Microsystems, 2(2), 40–43.
  12. Darche, P. (2000). Architecture des ordinateurs – Représentation des nombres et codes – Cours avec exercices corrigés. Éditions Gaëtan Morin.
  13. Darche, P. (2002). Architecture des ordinateurs – Fonctions booléennes, logiques combinatoire et séquentielle – Cours avec exercices et exemples en VHDL. Éditions Vuibert.
  14. Darche, P. (2003). Architecture des ordinateurs – Interfaces et périphériques – Cours avec exercices corrigés. Éditions Vuibert.
  15. Darche, P. (2004). Architecture des ordinateurs – Logique booléenne: implémentations et technologies. Éditions Vuibert.
  16. Darche, P. (2012). Mémoires à semi-conducteurs: principe de fonctionnement et organisation interne des mémoires vives – Volume 1. Éditions Vuibert. One of four books selected for the AFISI (Association Française d’Ingénierie des Systèmes d’Information) prize for best computing book 2012.
  17. DaSilva, F., Zorian, Y., Whetsel, L., Arabi, K., and Kapur, R. (2003). Overview of the IEEE P1500 Standard. 2003 International Test Conference (ITC 2003), 938–997. Paper 38.1. 30 September–2 October, Charlotte, North Carolina, USA.
  18. Doyle, J. (1985). C – An alternative to assembly programming. Microprocessors and Microsystems, 9(3), 124–132.
  19. Ferguson, D.E. (1966). Evolution of the meta-assembly program. Communications of the ACM (CACM), 9(3), 190–196.
  20. Helwig, F. (ed.) (1957). Coding for the MIT-IBM 704 Computer. Prepared at the MIT Computation Center by D. Arden, J. McCarthy, S. Best, A. Siegel, F. Corbato, F. Verzuh, F. Helwig, M. Watkins, and M. Weinstein. Massachusetts Institute of Technology, The Technology Press.
  21. Huang, I.-J. and Kao, C.-F. (2000). Exploration of multiple ICEs for embedded microprocessor cores in an SoC chip. Second IEEE Asia Pacific Conference on ASICs (AP-ASIC 2000), 311–314.
  22. Hughes, T.P. and Sawin III, D.H. (1978). Breakpoint design for debugging microprocessor software. Computer Design, 17(11), 99–107. Also in Carson 1979, p. 186–194.
  23. Hyde, R. (2010). The Art of Assembly Language, 2nd edition. No Starch Press.
  24. IEEE (1985). IEEE Standard for Microprocessor Assembly Language. IEEE Std 694-1985. The Institute of Electrical and Electronics Engineers (IEEE), New York, USA.
  25. IEEE (2000). IEEE Standard VHDL Language Reference Manual. IEEE Std 1076-2000. The Institute of Electrical and Electronics Engineers (IEEE), New York, USA.
  26. IEEE (2003). IEEE Standard for In-system Configuration of Programmable Devices. IEEE Std 1532-2002. Revision of IEEE Std 1532™-2001 (Revision of IEEE Std 1532-2000). The Institute of Electrical and Electronics Engineers (IEEE), New York, USA.
  27. IEEE (2005). 1500™ – IEEE Standard Testability Method for Embedded Core-based Integrated Circuits. IEEE Standard 1500™-2005. The Institute of Electrical and Electronics Engineers (IEEE), New York, USA. Approved June 30, 2005.
  28. IEEE (2013). Standard for Test Access Port and Boundary-Scan Architecture. IEEE Std 1149.1 – 2013 (Revision of IEEE Std 1149.1-2001). The Institute of Electrical and Electronics Engineers (IEEE), New York, USA. Approved February 6, 2013.
  29. IEEE/IEC (2007). IEC 62528 Ed. 1 / IEEE 1500™ Standard Testability Method for Embedded Core-based Integrated Circuits.
  30. IEEE-ISTO (1999). The Nexus 5001 Forum™ Standard for a Global Embedded Processor Debug Interface. IEEE-ISTO Std 5001™-1999.
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  32. Jones, C. (1986). Programming Productivity: Steps Toward a Science. McGraw-Hill, New York, USA.
  33. Jones, C. (1998). Sizing up software. Scientific American, 279(6), 107–109.
  34. Kao, C.-F., Huang, I.-J., and Chen, H.-M. (2008). Hardware–software approaches to in-circuit emulation for embedded processors. IEEE Design & Test of Computers, 25(5), 462–477.
  35. Kernighan, B.W. (1983). A programming language called C. IEEE Potentials, 2(4), 26–30.
  36. Kline, B., Maerz, M., and Rosenfeld, P. (1976). The in-circuit approach to the development of microcomputer-based products. Proceedings of the IEEE, 64(6), 937–942. Also in Carson 1979, p. 104–109.
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  38. Krummel, L. and Schultz, G. (1977). Advances in microcomputer development systems. IEEE Computer, 10(2), 13–19. Republished in Carson 1979, p. 87–93.
  39. Maunder, C.M. and Tulloss, R.E. (1990). The Test Access Port and Boundary-scan Architecture. IEEE Computer Society Press Tutorial. IEEE Computer Society Press.
  40. McEwan, R. (2002). MPC8xx Using BDM and JTAG. Application Note. AN2387/D. Rev. 0. Motorola Inc., November.
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  43. Navabi, Z. (2010). Digital System Test and Testable Design: Using HDL Models and Architectures. Springer-Verlag Inc., New York, USA.
  44. Nicoud, J.-D. (1976). A common assembly language. Second Euromicro Conference, 213–220.
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  46. Novell (1995b). System V Interface Definition, Volume 2, 4th edition. Novell, Inc.
  47. Novell (1995c). System V Interface Definition, Volume 3, 4th edition. Novell, Inc.
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  50. SCO (1996a). System V Application Binary Interface, 4th edition. The Santa Cruz Operation, Inc., California, USA.
  51. SCO (1996b). System V Application Binary Interface. Intel386 Architecture Processor Supplement, 4th edition. The Santa Cruz Operation, Inc., California, USA.
  52. SCO (1997). System V Application Binary Interface, 1st edition. The Santa Cruz Operation, Inc., California, USA.
  53. Smith, J.E. and Nair, R. (2005). Virtual Machines. Versatile Platforms for Systems and Processes. Morgan Kaufmann Publishers, Elsevier Inc.
  54. Stiefel, M.L. (1979). Microcomputer development systems. Product Profile. Mini-Micro Systems, 12(9), 74. Republished in Carson 1979, p. 78–86.
  55. Stollon, N. (2011). On-Chip Instrumentation – Design and Debug for Systems on Chip. Springer Science+Business Media, LLC.
  56. Streib, J.T. (2011). Guide to Assembly Language: A Concise Introduction. Springer-Verlag London Ltd.
  57. Vermeulen, B., Stollon, N., Kühnis, R., Swoboda, G., and Rearick, J. (2008). Overview of debug standardization activities. IEEE Design & Test of Computers, 25(3), 258–267.
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  60. Wegner, P. (1976). Programming languages – The first 25 years. IEEE Transactions on Computers, C-25(12), 1207–1225.
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  63. Wilkes, M.V. and Renwick, W. (1950). The EDSAC (Electronic Delay Storage Automatic Calculator). Mathematical Tables and other Aids to Computation (Mathematics of Computation), IV(30), 61–65.
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Part 2 (Chapter 3)

  1. Ajanovic, J. and Harriman, D.J. (2000). Method and apparatus for an improved interface between computer components. American patent n° 6145039. Intel Corporation. Filing date: November 3, 1998.
  2. Bradley, D. (2011). A personal history of the IBM PC. IEEE Computer, 44(8), 19–25.
  3. Bride, E. (2011). The IBM personal computer: A software-driven market. IEEE Computer, 44(8), 34–39.
  4. Ciarcia, S. (1987a). Part 1: AT basics. Build the circuit cellar AT computer. Ciarcia’s circuit cellar. Byte, 12(10), 115–120.
  5. Ciarcia, S. (1987b). Part 2: Schematic. Build the circuit cellar AT computer. Ciarcia’s circuit cellar. Byte, 12(11), 135–143.
  6. Croucher, P. (2004). The BIOS Companion. Electrocution Technical Publishers.
  7. Dice, P. (2018). Quick Boot: A Guide for Embedded Firmware Developers, 2nd edition. De|G Press.
  8. Gayler, W. (1983). The Apple II® Circuit Description. Howard W. Sams & Co., Inc.
  9. Goth, G. (2011). IBM PC retrospective: There was enough right to make it work. IEEE Computer, 44(8), 26–33, August.
  10. Gwennap, L. (1993). Intel provides PCI chip set for Pentium. New PCI-to-EISA Bridge also works with 486 chip set. Microprocessor Report (MPR), 7(4).
  11. Holden, B., Trodden, J., and Anderson, D. (2008). HyperTransport 3.1 Interconnect Technology. MindShare, Inc. MindShare Press.
  12. IBM (1981). Technical Reference. Personal Computer Hardware Reference Library, 1st edition. International Business Machines Corporation.
  13. IBM (1983). Technical Reference. Personal Computer XT Hardware Reference Library, 1st edition (Revised May 1983). International Business Machines Corporation.
  14. IBM (1984a). Technical Reference. Personal Computer Hardware Reference Library, revised edition. International Business Machines Corporation.
  15. IBM (1984b). Technical Reference. Personal Computer Hardware Reference Library, reference 1502494, 1st edition. International Business Machines Corporation.
  16. IBM (1986). Technical Reference. Personal Computer Hardware Reference Library, reference 6183355, 1st edition. International Business Machines Corporation.
  17. IEEE (1994a). IEEE Std 1275.1-1994. IEEE Standard for Boot (Initialization Configuration) Firmware: Instruction Set Architecture (ISA) Supplement for IEEE 1754. IEEE.
  18. IEEE (1994b). IEEE Std 1275.2-1994. IEEE Standard for Boot (Initialization Configuration) Firmware: Bus Supplement for IEEE 1496 (SBus). IEEE.
  19. IEEE (1994c). IEEE Std 1275-1994. IEEE Standard for Boot (Initialization Configuration) Firmware: Core Requirements and Practices. IEEE.
  20. IEEE (1995). IEEE Std 1275.4-1995 (Supplement to IEEE Std 1275-1994). IEEE Standard for Boot (Initialization Configuration) Firmware: IEEE Standard for Boot (Initialization Configuration) Firmware: Bus Supplement for IEEE 896 (Futurebus+®). Approved September 21.
  21. Intel (1993). 82420/82430 PCIset. ISA and EISA Bridges. Databook. Intel Corporation.
  22. Intel (1996). Intel 450KX/GX PCIset. Databook. Intel Corporation.
  23. Intel (2002). Extensible Firmware Interface Specification. Version 1.10. Intel.
  24. Noll, M.J. (1998). System for a Primary BIOS ROM Recovery in a Dual BIOS ROM Computer System. American patent n° 5793943. Application number: 08/688056. Filing date: July 29, 1996.
  25. Opler, A. (1967). Fourth-generation software, the realigment. Datamation, 13(1), 22–24.
  26. PCI-SIG (1998). PCI Local Bus Specification, Revision 2.2. PCI-SIG (Special Interest Group).
  27. Singh, G. (2011). The IBM PC: The silicon story. IEEE Computer, 44(8), 40–45.
  28. Slater, M. (1992). Intel unveils first PCI chip set. Three-chip set supports high-end 486 ISA systems. Microprocessor Report (MPR), 6(1).
  29. Trodden, J. and Anderson, D. (2003). HyperTransport™ System Architecture. MindShare, Inc., Addison-Wesley Developers Press.
  30. UEFI (2017). Unified Extensible Firmware Interface Specification, Version 2.7. Unified EFI Forum, Inc.
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