23

Intel 8259A— Programmable Interrupt Controller

Need for an interrupt controller

Overview of the working of 8259

Pins of 8259

Registers used in 8259

Interrupt request register

Interrupt mask register

In-service register

Slave register

Programming the 8259 with no slaves

Initialization command word 2 (ICW2)

Initialization command word 1 (ICW1)

Initialization command word 3 (ICW3)

Initialization command word 4 (ICW4)

Operation command word 1 (OCW1)

Operation command word 2 (OCW2)

Operation command word 3 (OCW3)

Programming the 8259 with slaves

Initialization command word 3 (ICW3)

Initialization command word 4 (ICW4)

Use of 8259 in an 8086-based system

Architecture of 8259

Questions

In this chapter we deal with the above mentioned topics of programmable interrupt controller 8259A. For simplicity, the 8259A is denoted as 8259 throughout this chapter.

23.1 NEED FOR AN INTERRUPT CONTROLLER

In an 8085 microprocessor, there are five interrupt input pins. They are TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. If there are a maximum of five I/O devices that desireto perform interrupt driven data transfer, they can be connected to the five interrupt input pins. Now consider the case where there are more than five I/O devices that would like to perform interrupt drivendata transfer. In such a case, on some interrupt pins more than one I/O device will have to interrupt. In fact, most microprocessors provide very few interrupt input pins. For example, Zilog Z-80, Motorola 6800, Intel 8086 have only two interrupt input pins. Thus an interruptpin may be required to receive interrupt requests from several devices. Figure 23.1 shows a case where three I/O devices interrupt the 8085 using the RST 6.5 interrupt input.

Fig. 23.1 Three devices interrupting 8085 using RST6.5 pin

In Fig. 23.1, the inputs to the OR gate are from Port B of 8255 PPI chips. Port B in these 8255 chips are assumed to be configured for mode 1 operation. The 8085 is interrupted when any one or more of the three inputs to the OR gate is active. It then branchesto the interrupt service subroutine (ISS)at 6.5×8 = 5 = 52 = 0034H. Thus the branch to ISS at 0034H takes place immaterial of the source of the interrupt. In reality, the processor is required to branch to different subroutines based on the source of the interrupt. Thusin the ISS for RST 6.5 the processor has to identify from among the I/O ports connected to the RST 6.5 pin the I/O port that needs service. This process of identifying the port that needs service is called ‘polling’. The subroutine that starts at 0034H is now called the interrupt level subroutine (ILS) for RST 6.5 instead of ISS for RST 6.5. Once the port that needs service is identified in the ILS, the processor performs a branch to the appropriate ISS.

The identification of the port that needs service is quite simple. The status information about Port B is obtained by reading Port C. If the LS bit of Port C is 1, it means that Port B interrupt request is active. The format of the ILS is shown as follows.

PUSH PSW
      PUSH B
      PUSH D
      PUSH H      ; Save registers

      IN PORT_C1
      RRC
      JC DEV_1    ; If LS bit of Port C in 8255-1 is 1, go to DEV_1

      IN PORT_C2
      RRC

JC DEV_2    ; If LS bit of Port C in 8255-2 is 1, go to DEV_2
      IN PORT_C3
      RRC
      JC DEV_3    ; If LS bit of Port C in 8255-3 is 1, go to DEV_3
      JMP EXIT

DEV_1:CALL ISS_1   ; Branch to ISS_1
      JMP EXIT

DEV_2:CALL ISS_2   ; Branch to ISS_2
      JMP EXIT

DEV_3:CALL ISS_3   ; Branch to ISS_3

EXIT: POP H
      POP D
      POP B
      POP PSW      ; Restore registers

      EI
      RET          ; Return to interrupted program

ISS_1:-
      -
      -
      -
      RET

ISS_2:-
      -
      -
      -
      RET

ISS_3:-
      -
      -
      -
      RET

The disadvantages of the polling method are as follows.

1. The polling process as shown in the ILS earlier takes quite a lotof time. This results in slow interrupt response.
2. If all the three inputs of the OR gate are active in Fig. 23.1, then in the ILS shown, device_1 is serviced first as device_1 is polled first. Thus the priority for the various devices connected on a single interrupt input pin is decided by the order in which they are polled. Similarly, if only device_3 is in need of service, the ILS first of all checks device_1 and device_2, finds that they are not in need of service, and only then it checks device_3 and starts servicing it. The priority thus gets fixed and cannot be altered.

The above mentioned disadvantages are eliminated if a programmable interrupt controller (PIC) is used in the microcomputer system. The 8259 chip is such a PIC in the Intel family.

23.2 OVERVIEW OF THE WORKING OF 8259

The 8259 accepts interrupt requests from as many as eight interrupting devices on IR₀ to IR₇ pins. Then it identifies the highest priority interrupt request from among those inputs that are active. It is possible to configure the 8259 for ‘fixed priority’ mode of operation. In such a case, IR₀ has the highest and IR₇ has the lowest priority. If IR₂, IR₄, and IR₆ inputs are active, then IR₂ is the highest priority interrupt request among the active requests. The details about the interrupt requests that are active are stored in the interrupt request register (IRR).

It is possible to mask the interrupt requests by loading the interrupt mask register (IMR). If IR₂ and IR₃ interrupt requests are masked, then IR₄ is the highest priority interrupt request among the active requests that are not masked. It is possible that the processor is already servicing IR₅interrupt request. Information about the interrupt requests that are presently being serviced will be kept in in-service register (ISR).

There is a priority resolver unit in the 8259. It receives inputs from IRR, IMR, and ISR and identifies the highest priority interrupt request. As the priority of IR4 is greater than IR5 that is currently being serviced, the INT (interrupt request) output is activated. At the same time, bit 4 of ISR is set to 1 by the 8259. The INT output of 8259 is connected to INTR input of 8085 as shown in Fig. 23.2. The INT output of 8259 should not be connected to anyother interrupt pin of 8085.

Thus the priority resolver decides to activateINT output only when the following conditions are satisfied.

• An IR input is activated;
• The IR input is not masked;
• The processor is presently not servicing an IR request with a higher priority.

Fig. 23.2 Interfacing of 8259 with 8085 processor

The 8085 completes the execution of the instruction during which the INTR input was activated. Then the 8085 sends out INTA* output thrice in succession assuming that the 8085 interrupt system is enabled, and higher priority interrupts of 8085 are not active. In response to the activation of INTA*, the 8259 sends to the 8085 using the D_7-0 pins a 3-byte CALL instruction. The first time the INTA* is activated, the 8259 sends code for CALL (5CDH) to the 8085 on D_7-0 pins. It is received in the IR register of 8085. The second time the INTA* is activated the 8259 sends LS byte of interrupt vector (IV) address to the 8085 on D_7-0 pins. It is received in the Z register of 8085. The third time the INTA* is activated the 8259 sends MS byte of IV address to the 8085 on D_7-0 pins. It is received in the W register of 8085. The IV address supplied by the 8259 to the 8085 depends on the IR input of 8259 that is being serviced. This results in a branch to the appropriate ISS. After finishing the ISS the control returns to the main program.

The important thing to note is that the processor is not required to identify the source of the interrupt on INTR pin. The 8259 has the mechanism to identify the source of interrupt from among IR₀ to IR₇. It sends to the 8085 the CALL instruction with appropriate ISS address accordingly. Thus the problem of polling is eliminated and so the interrupt response time is reduced. Second, the 8259 could be configured to operate in ‘rotating priority’mode. Then the disadvantage of fixed priority is also taken care of.

With a single 8259 in the system as many as eight interrupting devices can interrupt on INTR input of 8085. If there are a large number of devices that need to perform interrupt drivendata transfer, multiple 8259s could be used. The 8259 whose INT output is connected to INTR input of 8085 will be called the Master 8259. The 8259s whose INT outputs are connected to the IR inputs of the Master 8259 will be called Slave 8259s. With this scheme a total of 64 devices can interrupt on the INTR input of 8085. Such a scheme is shown in Fig. 23.3. In this figure only two Slave 8259s are used. As such, 2×8+6 = 22 devices can interrupt on the INTR input of 8085. The 8259 can be used even in Intel 8086-based system. Intel 8086 is a 16-bit processor. The working of 8259 in a 8086-based system is described at the end of the chapter.

fig. 23.3 Use of multiple 8259s

23.3 PINS OF 8259

Intel 8259 is a 28-pin programmable IC available as a DIP package. Its physical and functional pin diagrams are indicated in Figs. 23.4 and 23.5, respectively.

fig. 23.4 Pin diagram of Intel 8259

• An IR input is activated.
• The IR input is not masked.
• The processor is presently not servicing an IR request with a higher priority.

23.4 REGISTERS USED IN 8259

From the point of view of a microprocessor, the 8259 is a specialized I/O port chip. It is never used for interfacing I/O devices, but only for controlling the interrupt system in a microcomputer. The 8259 has A₀ as the only address input pin. Thus only two addresses are possible for the 8259 ports as seen from a microprocessor. The two ports can be designated as low port and high port.

The processor issues command words to these ports in order to configure the 8259 as per the need. There are several command words which are classified as initialization command words and operation command words. There are four initialization command words (ICW1, ICW2, ICW3, and ICW4)and three operation command words (OCW1, OCW2, and OCW3). The processor also reads thestatus of 8259 by reading the low port and the high port. There are several status words to be read.

The 8259 makes use of a number of 8-bit registers shown as follows for its working.

The processor writes command words, reads status words, or accesses registers using only the low port and the high port. Identification of a command word, status word, or a register is based on A₀ value, the bit values in certain bit positions, and in some cases by the context of the programming. The details about the identification of a command word, status word, or a register are provided later.

A brief description of the registers is provided as follows.

23.4.1 INTERRUPT REQUEST REGISTER

It is an 8-bit register that keeps track of active interrupt requests. Whenever an interrupt request input is activated, the corresponding bit in IRR register is set to 1. For example, if IR₄ and IR₆ inputs are activated, bits 4 and 6 of IRR are set to 1 making the contents of IRR as 01010000. The processorcan only read the contents of this register but cannot write to IRR. To read the IRR contents, the processor has to issue OCW3 command to the 8259, with the LS 3 bits of the OCW3 command as 010. This results in 8259 storing the IRR status in low port of 8259. Then the processor has to read the low port of 8259.

23.4.2 INTERRUPT MASK REGISTER

It is an 8-bit register that keeps track of the interrupt requests that are masked. If IR₄ and IR₆ requests should not cause an interrupt to the processor, it is easily achieved by making the contents of IMR as 01010000 that sets bits 4 and 6 of IMR to 1. Then even if IR₄ or IR₆ request is activated, the 8259 does not activate INT output and hence the processor will not be interrupted. The IMR is written by issuing the OCW1 command. The command uses high port of 8259. The processor can also read the contents of IMR register. To do this, the processor has to read the high port of 8259.

23.4.3 IN-SERVICE REGISTER

It is an 8-bit register that keeps track of the interrupt requests that are currently being serviced. If IR₆ request is currently being serviced, then the contents of ISR will be 01000000. If IR₃ request becomes active during the service of IR₆, the 8259 sets bit 3 of ISR to 1 and activates INT output. But bit 6 of ISR remains set at 1 as IR₆ request is not fully serviced yet. Thus the contents of ISR will be 01001000. The following assumptions must hold good for this to happen.

• 8259 is operating in fully nested mode, without rotating priority, so that IR₃ has higher priority over IR₆.
• The processor has enabled interrupts in the routine for IR₆.
• IR₃ request has not been masked.

The processor can only read the contents of the ISR register but cannot write to ISR. To read the ISR contents, the processor has to issue OCW3 command to the 8259, with the LS 3 bits of the OCW3 command as 011. This results in the 8259 storing the ISR status in low port of 8259. Then the processor has to read the low port of 8259.

23.4.4 SLAVE REGISTER

It is an 8-bit register. The processor writes to SLR but cannot read it. The content of this register has different meanings for Master 8259 and a Slave 8259. For Master 8259, it provides information about the IR inputs to which Slave 8259s are connected. If SLR of Master 8259 is loaded with the value 00001111, then it means that:

• There are Slave 8259s on IR₀, IR₁, IR₂, and IR₃.
• There are no Slave 8259s on IR₄, IR₅, IR₆, and IR₇.

For a Slave 8259, it provides information about the IR input of Master 8259 to which the Slave 8259 is connected. In this case, only the LS 3 bits of SLR are meaningful. If the SLR of a Slave 8259 is loaded with the value 00000101, then it means that the Slave 8259 is connected to IR₅ input of the Master 8259. The SLR is written by issuing the ICW3 command, which uses high port of 8259.

23.5 PROGRAMMING THE 8259 WITH NO SLAVES

In this section, it is assumed that

Before 8259 PIC could be used in a microcomputer system for interrupt control application, it has to be properly configured to meet the needs of the system. By configuring the 8259, it is provided with a variety of information like

To provide this information to the 8259, the processor has to issue the following commands.

Two initialization command words (ICW1 and ICW2) must be issued to the 8259 before it could be used, as they are compulsory. ICW3 is also compulsory provided there are Slave 8259s in the system. ICW4 is also compulsory provided the processor is 8086 or special modes of 8259 are desired. In contrast to this, operation command words are not compulsory. Hence operation command words could also be called ‘optional command words’.

The command words have to be written to the low port or the high port of 8259 depending on the command.

The 8259 port addresses depend on the chip select used in the system. For the discussion that follows, it is assumed that the port addresses of 8259 are as given in the following:

23.5.1 INITIALIZATION COMMAND WORD 2 (ICW2)

ICW1 will be explained after ICW2. The ICW2 command is written to the high port of 8259. It indicates A_15-8, which is the MS byte of IV address. The 8259 should supply this MS byteof IV address to the 8085 processor when the processor activates INTA* for the third time. If it is desired that the IV supplied by 8259 to 8085 processor is 2480H when IR₀ request is active, then the ICW2 command should indicate that 24H is the MS byte of IV address. This is achieved by executing the following instructions.

23.5.2 INITIALIZATION COMMAND WORD 1 (ICW1)

The ICW1 command is written to the low port of 8259. Several other commands are also written to the same port. If bit 4 of the low port is 1, the command in the low port is identified as ICW1.

The ICW1 command indicates the LS byte of IV address which the 8259 should supply to the 8085 processor when the processor activates INTA* for the second time. If it is desired that the IV supplied by 8259 to 8085 processor is 2480H when IR₀ request is active, then the ICW1 command should indicate that 80H is the LS byte of IV address.

The ICW1 command provides some additional information also to the 8259 detailed as follows.

The format of the ICW1 command is indicated as follows. Note that bit 4 = 1, indicating it is ICW1 command.

4/8* bit: Suppose the 8259 is configured such that the IV address is 2480H when IR0 request is activated. If IR1 request causes the activation of INT output, the 8259 automatically sends out 2484H (a distance of 4 bytes from 2480H) as the IV address when 4/8* bit = 1. For the same IR₁ request, the IV address automatically sent out by 8259 is 2488H (a distance of 8 bytes from 2480H) when 4/8* = 0. Table 23.1 indicates the IV address sent out by 8259 for different activations IR inputs when the 4/8* bit is 1.

Table 23.1 IV addresses when configured for 4-byte interval

The following points are to be noted from Table 23.1.

• Only four locations are available for writing service routine for an IR input. For example, for IR₂ request, the service routine should start at 2488H and should end by 248BH. Obviously, the amount of memory space will be inadequate. Storing a 3-byte jump instruction say ‘JMP C100H’ at 2488H could solve this problem. In such a case, the service routine for IR2 starts at C100H. If the service routine for IR₂ ends at C3FFH, then the service routine for IR₃ can be started at C400H. Storing ‘JMP C400H’ at location 248CH achieves this.
• The LS 2 bits (shown underlined) in the LS byte of address are always 00. So the 8259 will not be informed about the value of these bits explicitly.
• The value of the next 3 bits (shown in bold type) is dependent on the IR input that is active. For IR₀ it is 000, for IR₅ it is 101 etc. The 8085 processor cannot foresee which IR request will be activated. Only the 8259 should decide about the valueof these bits depending on the IR request that is active. As such, the value of these bits will not be supplied to 8259 by the 8085. Thus, out of the 16-bit IV address, the 8085 is required to supply only the MS 11 bit address. The LS 5 bits of the address will be decided by the 8259 itself. Out of the MS 11 bits of address, the MS 8 bits of address is provided by ICW2 command, as already described. The remaining 3 bits (shown in italics) that are the MS 3 bits of LS byte of address is provided by the ICW1 command. In the ICW1 format, these 3 bits of address are indicated as A₇, A₆, and A_5.

The LS 5 bits of IV address have to be 00000 for IR₀ request. Hence the only possible IV addresses for IR₀ when 24H is the MS byte of address depends on A₇, A₆, and A₅. They are as shown in Table 23.2.

Table 23.2 Possible IV addresses for IR₀

Table 23.3 indicates the IV address sent out by 8259 for different activation of IR inputs when the 4/8* bit is 0, assuming IV address for IR₀ to be 2480H.

Table 23.3 IV addresses when configured for 8-byte interval

The following points are to be noted from Table 23.3.

• Only eight locations are available for writing service routine for an IR input. For example, for IR₂ request, the service routine should start at 2490H and end by 2497H. Obviously, the amount of memory space will be inadequate. Storing a 3-byte jump instruction say ‘JMP C100H’ at 2490H could solve this problem. In such a case, the service routine for IR₂ starts at C100H. If the service routine for IR₂ ends at C3FFH, then the service routine for IR₃ can be started at C400H. Storing ‘JMP C400H’ at location 2498H achieves this.
• The LS 3 bits (shown underlined) in the LS byte of address are always 000. So the 8259 will not be informed about the value of these bits explicitly.
• The value of next 3 bits (shown in bold type) is dependent on the IR input that is active. For IR₀ it is 000, for IR₅ it is 101 etc. The 8085 processor cannot foresee which IR request will be activated. Only the 8259 should decide about the value of these bits depending on the IR request that is active. As such, the value of these bits will not be supplied to 8259 by the 8085. Thus, out of the 16-bit IV address, the 8085 is required to supply only the MS 10-bit address. The LS 6 bits of the address will be decided by the 8259 itself. Out of the MS 10 bits of address, the MS 8 bits of address is provided by ICW2 command, as already described. The remaining 2 bits (shown in italics) that are the MS 2 bits of LS byte of address is provided by the ICW1 command. In the ICW1 format, these 2 bits of address are indicated as A₇ and A₆. The bit indicated as A_5/X is used as X (don't-care) bit when 4/8* bit = 0. Generally a 0 is stored for the X bit.

The LS 6 bits of IV address have to be 000000 for IR₀ request. Hence the only possible IV addresses for IR₀ when 24H is the MS byte of address depends on A₇ and A₆. They are as shown in Table 23.4.

Table 23.4 Possible IV addresses for IR₀

Example

Assume it is required to configure the 8259 using ICW1 for the following operation.

• ICW4 is not going to be issued.
• Only one 8259 to be used in the system.
• The address interval is required to be 8 bytes.
• The IR_0-7 requests are to be edge triggered.
• The LS byte of IV address for IR₀ to be 80H.

This is achieved by executing the following instructions.

The MS 2 bits are 10 which means that A_7-6 = 10. Thus the LS byte of IV address for IR₀ will be 10 000000 5 80H as required.

23.5.3 INITIALIZATION COMMAND WORD 3 (ICW3)

ICW3 is not needed when there are no Slave 8259s in the system. As it is assumed that there are no Slave 8259s in the system, the discussion about ICW3 is deferred for the present.

23.5.4 INITIALIZATION COMMAND WORD 4 (ICW4)

The ICW4 command is written to the high port of 8259 and is needed only if any of the following conditions is satisfied.

• If the processor used in the system is 8086.
• If the 8259 has to be configured for special modes (special fully nested mode, buffered mode, automatic end of interrupt mode) immaterial of the processor used in the system.

If any of these conditions is true, the processor has to issue an ICW1 command with IC4 bit, present at the LS bit position, as 1. The LS bit of ICW1 command indicates whether ICW4 command is needed or not. ICW4 command is written to the high port. Several other commands are also written to the same port. For example ICW2, as described earlier, is written to the high port of 8259. Even ICW3 and OCW1 commands are written to the same port. The 8259 identifies the command in the high port based on the ICW1 command issued to the low port of 8259 earlier.

The first time the high port is written, the command is always interpreted as ICW2. The second time the high port is written, the command is interpreted as ICW3, if there are Slave 8259s in the system. If there are no Slave 8259s, it will be interpreted as ICW4, if ICW4 is needed as indicated in bit 0 of ICW1 command. If ICW4 is also not needed, it will be interpreted as OCW1. The third time the high port is written, the command is interpreted as ICW4 if ICW4 is needed, else it is interpreted as OCW1. If the high port is written for the fourth time and onwards, the command is interpreted as OCW1. Thus if it is needed to load the high port of 8259 with ICW2 command again, it is necessary to load the low port of 8259 with ICW1 command first.

Assuming that the processor writes to the high port of 8259 five times, the interpretation of the contents of the high port will be as indicated in Table 23.5.

Table 23.5 Interpretation of the contents of high Port

The format of the ICW4 command is indicated as follows. Note that only 5 bits are used in this command. The MS 3 bits are always 000.

AEOI bit: If the processor is servicing IR₄, then bit 4 of ISR is set to 1 by the 8259. This bit has to be reset to 0 sometime later. Otherwise, IR₄ input cannot interrupt the processor anymore. The highest priority ISR bit that is set can be reset to 0 by the following two methods.

• By issuing an EOI command before returning from service routine.
• Automatically following the last INTA* pulse.

If the AEOI bit is 1, the 8259 is configured for AEOI mode, else it is configured for EOI mode.

The SFNM, BUF, M/S* bits of ICW4 command will be described when ‘programming the 8259 when there are slaves’ topic is discussed.

23.5.5 OPERATION COMMAND WORD 1 (OCW1)

The OCW1 command is written to the high port of 8259. It indicates the IR inputs that must be masked. Basically, when the high port of 8259 is loaded with OCW1 command, the content of the high port is internally moved to the IMR. The format of the OCW1 command is indicated as follows.

Similar is the meaning for the other bits in the command.

Assume IR₄ and IR₆ requests should not cause an interrupt to the processor. This is easily achieved by issuing OCW1 command with 01010000 as the data, which in turn is achieved by executing the following instructions.

MVI A, 50H

OUT 51H

23.5.6 OPERATION COMMAND WORD 2 (OCW2)

The OCW2 command is written to the low port of 8259. The ICW1 and OCW3 commands are also written to the same port. If bit 4 and bit 3 of the low port are 00, the command in the low port is identified as OCW2, which is used for issuing the following types of commands to the 8259.

The format of the OCW2 command is indicated as follows. Note that bit 4 = 0 and bit 3 = 0, indicating that it is an OCW2 command.

The R, SL, and EOI bits of OCW2 command identify the configuration of 8259.

When R = 1, SL = 1, and EOI = 0 in the OCW2 command, it means that specific rotation has to be performed in AEOI command. It simply rotates the priorities.

It may be noted that when R = 0, SL = 1, and EOI = 0 in the OCW2 command, it means that—no rotation, AEOI, but specified level to be used. It is indeed a ‘no operation’ command that is never used.

Need for rotation of priorities: In some applications it is possible that all the devices that interrupt on IR0₇ have equal priority. However, after initialization of 8259, IR₀ will have the highest and IR₇ the lowest priority unless rotating priority is forced on 8259. This will result in a poor response to low-priority interrupt requests. For example, IR₇ request may never be serviced, if other higher priority requests keep occurring. This problem is solved using rotating priority. There are two types of rotation of priorities. They are:

Non-specific rotation: In this mode, the priorities will be rotated such that the highest priority ISR bit that is presently in the set state will get the lowest priority. If bit 4 of ISR is the highest-priority ISR bit that is in the set state, then the priorities would be rotated so that IR4 will have the lowest priority and IR₅ the highest as indicated in the following.

The EOI command is always combined with non-specific rotation command. Hence in this example, bit 4 of ISR is reset to 0. Non-specific rotation with EOI is used, when fully nested structure is preserved.

Specific rotation: In this mode, the priorities will be rotated such that the specified level will get the lowest priority. If level 4 were specified using specific rotation, then the priorities would be rotated so that IR₄ will have the lowest priority and IR₅ the highest priority as indicated in the following.

The EOI command is generally combined with specific rotation. If EOI command is combined with specific rotation in the above example shown, bit 4 of ISR will be reset to 0. Specific rotation without EOI command is not commonly used. Such a command disturbs thefully nested structure. ‘Specific EOI command’ will have to be executed to reset the appropriate ISR bit in case ‘specific rotation without EOI command’ is used earlier. An example illustrates this situation.

Consider the following situation. Presently IR0 has the highest and IR₇ has the lowest priority. IR₄input is activated and has not been masked. The processor is busy servicing IR₆ request. Then bit 4 of ISR will be set to 1. However, bit 6 of ISR remains set at 1, as IR₆ request has not been fully serviced. The processor now branches to the IR₄ service routine. Assume that the following instructions are executed within the IR₄ service routine.

After the execution of the instructions shown, bit 4 and bit 6 of ISR remain set, as EOI bit is 0. However priorities would be rotated so that IR₄ will have the lowest priority and IR₅ the highest priority indicated as follows.

If non-specific EOI command is issued just before the end of the service routine for IR₄, the 8259 resets the highest priority ISR bit that is in the set state. In this case, it resets bit 6 of ISR and not bit 4 of ISR. The rotation of priorities without EOI command has disturbed the fully nested structure. It is necessary in such a case to issue a specific EOI command that resets bit 4 of the ISR.

Some examples for OCW2 commands are provided in the following. It is assumed that the low port address is 50H.

Example 1: The OCW2 needed to issue a non-specific EOI command to the 8259 is:

Example 2: The OCW2 needed to issue a specific EOI command to the 8259 that resets bit 5 of ISR is:

Example 3: The OCW2 needed to issue a rotate with non-specific EOI command to the 8259 is:

Example 4: The OCW2 needed to issue a rotate with specific EOI command to the 8259 that resets bit-5 of ISR is:

Example 5: If 8259 is already configured for AEOI mode using ICW4 command, then the OCW2 needed to issue a rotate in AEOI command to the 8259 is:

Example 6: If 8259 is already configured for AEOI mode using ICW4 command and the 8259 is already configured for rotate in AEOI mode using OCW2 command, as in the previous example, then the new OCW2 needed to issue a ‘stop rotate in automatic EOI command’ to the 8259 is:

23.5.7 OPERATION COMMAND WORD 3 (OCW3)

The OCW3 command is written to the low port of 8259. The ICW1 and OCW2 commands are also written to the same port. If bit 4 and bit 3 of the low port are 01, the command in the low port is identified as OCW3. The OCW3 command is used for issuing the following types of commands to the 8259.

The format of the OCW3 command is indicated as follows. Note that bit 4 = 0 and bit 3 = 1, indicating it is OCW3 command. The MS bit in this command is a don't-care bit.

Polled mode: When the P bit is set to 1, the 8259 works in polled mode. If P= 0, polling mode is not used. When working in polled mode, the INT output will never be activated by the 8259. As such, the INT output of 8259 need not be connected to the INTR input of 8085. In this mode, the processor has to identify the IR input that needs service using software. The processor first of all issues an OCW3 command and configures the 8259 for polled mode. Then the 8259 automatically freezes the contents of ISR based on IR inputs at that moment, till the low port of 8259 is read. Thus even if the IR inputs were to change after poll command is issued, the ISR contents do not change. The processor then reads the low port that provides information about the highest priority-level requesting service. The information is provided in the following format.

Where W_2-0 indicates the highest priority-level requesting service and I indicates whether the corresponding IRinput is still active.

The following instructions are to be executed by the 8259 to find out about the IR input that needs service in polling mode.

The polled mode can be used to expand the number of priority levels indefinitely, unlike the limitation of 64 levels in non-polled mode using one Master and eight Slave 8259s. Figure 23.6 shows three 8259s connected in cascade. The INT output of 8259-2 is connected to IR₄ input of 8259-1 and that of 8259-3 is connected to IR6 input of 8259-2.

Assume only IR0 input of 8259-3 is active. All the three 8259s are configured for polled mode. The processor polls 8259-1 and comes to the conclusion that IR₄ input of 8259-1 is active. As 8259-2 is connected to IR₄ input of 8259-1, the processor polls 8259-2 and comes to the conclusion that the IR₆input of 8259-2 is active. Finally, as 8259-3 is connected to IR₆ input of 8259-2, the processor polls 8259-3 and comes to the conclusion that the IR₀ input of 8259-3 is active. Once the interrupting source is identified, the processor branches to the appropriate service routine.

Fig. 23.6 Cascade of 8259s in polled mode

Read status of IRR or ISR: Sometimes we wish to know the contents of the IRR or ISR. For this purpose, the OCW3 command has to be executed first indicating whether it is desired to read IRR or ISR. After this, the low port of 8259 has to be read to get the status of the desired register.

The IS/IR* bit is a don't-care bit when RR bit is 0.

Thus, the execution of the following instructions results in register A of 8085 getting the status information present in IRR of 8259.

In case OCW3 command is issued with P = 1 and RR = 1, reading of the low port provides polled information and not status of IRR or ISR.

Special masked mode (SMM): Sometimes it is necessary that in a service routine some of the lower priority IR inputs should be capable of interrupting the processor. Under normal conditions, assuming IR₀ is the highest priority input, if the processor is servicing say IR4 request, IR_5-7 inputs cannot activate INT output of 8259. This is true even if none of IR_5-7 is masked. This is where the SMM proves useful.

If IMR is loaded with 00010011 when the 8259 is configured for SMM in the service routine for IR₄, then it means that not only the higher priority inputs IR₂ and IR₃ but also the lower-priority inputs IR₅, IR₆, and IR₇ are capable of interrupting the IR₄ service routine. For the same value in IMR, if the command were normal mask mode, only the higher priority inputs IR₂ and IR₃ would be capable of interrupting the IR₄ service routine.

The SMM is set when ESMM = 1 and SMM = 1 in OCW3 command. It reverts to normal mask mode when ESMM = 1 and SMM = 0. ESMM stands for enable special mask mode and SMM stands for special mask mode. When ESMM = 0, the SMM bit is a don't-care bit.

23.6 PROGRAMMING THE 8259 WITH SLAVES

In this section, it is assumed that a Slave 8259 is connected to IR₄ input of Master 8259 and the processor used in the microcomputer system is 8085. This is shown in Fig. 23.7.

The port addresses of 8259 depend on the chip select circuit used. For the discussion, the port addresses are assumed as follows.

fig. 23.7 A Slave 8259 connected to IR₄ input of Master 8259

The Master 8259 and all Slave 8259s used in the system have to be individually programmed using ICWs and OCWs. The ICW1 and ICW2 have the same meaning whether it is Master 8259 or a Slave 8259. Hence discussion about ICW1 and ICW2 is not repeated.

23.6.1 INITIALIZATION COMMAND WORD 3 (ICW3)

The ICW3 command is written to the high port of 8259 and is needed only if there are Slave 8259s in the system. Bit 1 of ICW1 command indicates whether there are Slave 8259s or not. Several other commands are also written to the same port, for example, ICW2, ICW4, and OCW1. The 8259 identifies the command in the high port based on the ICW1 command issued to the low port of 8259 earlier. This topic has already been dealt with.

The ICW3 command has different interpretations for Master 8259 and a Slave 8259. Basically, when the high port of 8259 is loaded with ICW3 command, the content of the high port is internally moved to the SLR.

For Master 8259, ICW3 provides information about the IR inputs to which Slave 8259s are connected. Assume the following instructions to be executed after the ICW2 command, when there are Slave 8259s in the system.

The SLR of Master 8259 is loaded with the value 00010000. Then it means that there is a Slave 8259 on IR₄ input only of the Master 8259.

For a Slave 8259, ICW3 provides information about the IR input of Master 8259 to which the Slave 8259 is connected. In this case, only the LS 3 bits of SLR are meaningful. Assume SLR of Slave 8259 to be loaded with the value 00000100 using the following instructions.

Then it means that the Slave 8259 is connected to IR₄ input of the Master 8259.

23.6.2 INITIALIZATION COMMAND WORD 4 (ICW4)

The ICW4 was partly described earlier. It is written to the high port of 8259 and is needed only if any of the following conditions is satisfied.

• If the processor used in the system is 8086.
• If the 8259 has to be configured for special modes (special fully nested mode, buffered mode, automatic end of interrupt mode) immaterial of the processor used in the system.

If any of these conditions are true, the processor has to issue an ICW1 command with IC4 bit, present at the LS bit position, as 1. The LS bit of ICW1 command indicates whether ICW4 command is needed or not.

The format of the ICW4 command is indicated as follows. Note that only 5 bits are used in this command. The MS 3 bits are always 000.

The meaning of 86/85* and AEOI bits are already discussed.

Buffered mode of 8259: If the 8259 is used in a large system, then bus-driving buffers are needed on the data bus. This opens up the problem of enabling the buffers which is solved by configuring the 8259 for buffered mode of operation.

In non-buffered mode, SP*/EN* pin is used as the input pin SP*. This has been discussed earlier. However, in the buffered mode, SP*/EN* pin is used as the output pin EN* that enables the buffers. This output pin is activated whenever the 8259 data bus outputs are enabled. Then in the buffered mode, as SP*/EN* is used as EN* output, the identification of an 8259 as master or a slave becomes a problem. This is solved by software using BUF and M/S* bits of the ICW4 command.

The M/S* bit is a don't-care bit when BUF = 0.

Special fully nested mode: If the SFNM bit is 1, the 8259 will be configured for SFNM. This mode is meaningful only for Master 8259. To understand SFNM, it is necessary to first understand FNM.

Fully nested mode: The 8259 is configured to function in FNM if SFNM bit = 0 in the ICW4 command. If ICW4 command is not used in the configuring of 8259, the 8259 is automatically configured for FNM. In this mode IR₀ will have the highest and IR₇ will have the lowest priority to start with. This priority changes dynamically as interrupt requests arrive, if the 8259 is configured for rotating priority mode. Rotating priority is already described. If the 8259 is not configured for rotating priority, IR₀ will continuously have the highest and IR₇ the lowest priority.

The FNM of operation is normally used when there are no Slave 8259s. In FNM, IR₀ will have the highest and IR₇ the lowest priority if rotating priority is not used. Thus if IR₄ causes the activation of INT output, bit 4 of ISR will be set to 1. In such a case, IR_4-7 cannot activate INT output till bit 4 of ISR is reset to 0 using EOI command with the help of OCW2 or using AEOI command with the help of ICW4 command.

Assume a Slave 8259 is connected to IR₄ input of the Master 8259 and the IR₆ input of Slave 8259 is responsible for the activation of INT output of the Slave. This is shown in Fig. 23.8.

Fig. 23.8 Need for SFNM

As the INT output of Slave 8259 is connected to IR₄ input of Master 8259, bit 4 of ISR in the Master 8259 is set to 1. Now assume that the IR₂ input of Slave 8259 becomes active in the service routine for IR₆ of Slave 8259. As IR₂ has higher priority over IR₆ that iscurrently being serviced, the Slave 8259 again activates its INT output. But the Master 8259 does not activate its INT output because it is only the IR₄ input of Master 8259 that is active and bit 4 of ISR in the Master 8259 is not yet reset to 0. This problem is solved using the SFNM for Master 8259 and configuring Slave 8259s in FNM.

The SFNM is very similar to FNM with the following difference. Assume the processor is servicing an IR input of a Slave 8259. If a higher priority IR input of the Slave 8259 becomes active, the Master 8259 activates its INT output if the Master is configured for SFNM. This would not have happened if the master were in FNM. When the Master 8259 is configured for SFNM, the procedure to be adopted before exiting a service routine is as follows. It is explained with the situation described here as an example.

First of all, non-specific EOI command using OCW2 has to be issued to the Slave 8259. This would reset bit 2 of the ISR of Slave 8259. Then the ISR of Slave 8259 is read by issuing OCW3 command to the Slave 8259. If the contents of ISR of Slave 8259 is 00H, it means none of the IR inputs of Slave 8259 are currently being serviced. Only in such a case, non-specific EOI command using OCW2 has to be issued to the Master 8259. If the ISR contents of Slave 8259 is non zero, EOI command should not be issued to the Master 8259.

The Master 8259 is configured for SFNM if SFNM bit is set to 1 in the ICW4 command. If this bit is 0, the Master 8259 is configured for FNM only as indicated in the following.

Default settings for ICW4: If the ICW4 command is not used in the system, the 8259 will automatically be configured as if the LS 5 bits of ICW4 command were 00000. In other words when ICW4 command is not used, the 8259 is automatically configured as follows.

• The processor used in the system is assumed to be 8085/8080.
• End of interrupt command needed before the end of the service routine.
• Non-buffered mode is used.
• Fully nested mode is used.

23.7 USE OF 8259 IN AN 8086-BASED SYSTEM

When 8259 is used in an 8086-based system, the 8259 automatically changes its working to suit the requirements of 8086 processor. The 8086 processor has two interrupt pins—INT and NMI. The INT output of 8259 is always connected to the INT input of 8086. It is never connected to NMI input of 8086. When the 8086 is interrupted on INT halfway through an instruction, the 8086 completes the instruction under execution and then sends out INTA* pulse two times in succession. When INTA* is pulsed the first time, the highest priority ISR bit is set to 1 and the corresponding IRR bit is reset to 0. The 8259 does not send out any data in response to the first INTA* pulse. In response to the second INTA* pulse, the 8259 sends out an 8-bit interrupt type number. It is to be noted that the 8259 does not send out a CALL instruction to the 8086. The 8086 performs branch to appropriate service routine based on the interrupt type number received by it.

When 8259 is used in an 8086-based system, some differences exist in the interpretation of ICW1 and ICW2 command words. The other commands have the same interpretation immaterial of whether the processor is 8085 or 8086.

ICW2 is used to provide the 8086 with the interrupt type number. In this command only the MS 5 bits are meaningful. The LS 3 bits are don't cares. Normally 000 is stored in these bit positions. The 8259 appends the IR input number that is responsible for the activation of INT output to the MS 5 bits of ICW2. If ICW2command is issued with 10101 000 =A8H as the data, then it means that the interrupt type number is A8H if IR0 input is responsible for the activation of INT output of 8259. If the IR₁input is responsible for the activation of the INT output of 8259, the 8259 automatically sends out 10101 001 = A9H as the interrupt type number. Finally, if the IR₇ input is responsible for activation of INT output of 8259, the 8259 automatically sends out 10101 111 =AFH as the interrupt type number. In ICW1 command A₇, A₆, A_5/X, and 4/8* bits are don't-care bits when 8259 is used in an 8086-based system.

23.8 ARCHITECTURE OF 8259

Based on the description of the working of 8259, the simplified architecture of 8259 can be illustrated as in Fig. 23.9.

Fig. 23.9 Internal architecture of 8259

To conclude, the 8259 is a highly programmable chip that can be configured to exactly suit the requirements of interrupt control in an application.

1. Describe the need for an interrupt controller in a microcomputer system.
2. Provide a brief overview of the working of 8259 programmable interrupt controller.
3. Briefly describe the functions of the pins of 8259.
4. Describe the functions of the important registers available in 8259
5. Provide an overview of the initialization command words used when a single 8259 is used in a system.
6. Provide an overview of the operation command words of 8259.
7. Is it possible to have an IV address for IR₀ as 3456H when the 8259 is configured for 4-byte CALL interval? If the answer is no, what is the possible IV address for IR₀ that is closest to 3456H?
8. Name the command word and indicate the contents of the command word that is required to configure the 8259 for the following operations.
   1. ICW4 is going to be issued.
   2. Several 8259s are to be used in the system.
   3. The address interval is required to be 4 bytes.
   4. The IR_0-7 requests are to be level triggered.
   5. The LS byte of IV address for IR₀ to be C0H.
9. Name the command word and indicate the contents of the command words that are required to configure three 8259s such that the Slave 8259s are connected on IR₂ and IR₅ inputs of Master 8259.
10. Name the command word of 8259 that specifies the processor used in the system. What should be the contents of this command word to configure the 8259 as buffered-mode slave, in FNM, with highest priority ISR bit getting automatically reset when the second INTA* pulse is received in an 8086-based system?
11. What is the change in the interpretation of bits in ICW1 and ICW2 commands of 8259 when the processor used in the system is changed from 8085 to 8086?
12. How does the 8259 identify the command written to the high port of 8259?
13. Explain the need for SFNM. How do you configure 8259 for SFNM?
14. Explain OCW2 command with relevant examples.
15. Explain polled mode of operation in 8259.
16. Explain SMM of 8259 and its utility.
17. What is the default setting of ICW4 command?
18. Explain the architecture of 8259 with a neat diagram.