6.1.1 Production of Metallurgical Silicon

MG‐Si is produced from silicon, the most abundant element on Earth. Silicon in nature is bound with oxygen in the form of quartz (silica, SiO₂). Separation of oxygen from silicon is energy intensive, requiring the reduction of SiO₂ with carbon in a carbon arc furnace, producing CO₂. This takes place in gigantic electric arc furnaces (Figure 6.1).

Modern factories generally use between two and six of these furnaces. The electricity is fed through three carbon electrodes that are submerged in a mixture of quartz, carbon (in the form of coal, charcoal, and petroleum coke), and wood chips. The electricity then cuts a path to the furnace’s floor, which acts as a counter electrode. Since the mixture of raw materials is a poor conductor of electricity, it heats to as high as 2500°C. The heat causes the quartz to transfer its oxygen to the carbon forming gaseous carbon monoxide, which is burned as a carbon dioxide once it escapes the reaction mixture and is combined with atmospheric oxygen:

(6.1)

The wood chips act as a loosening material so that the gas can escape. Liquid silicon and nonvolatile impurities gather at the bottom of the furnace. Every 2 hours the furnace is tapped and the liquid silicon drawn off (Figure 6.2). It then cools and hardens in a flat trough. The finished slabs are usually broken and sorted by particle size according to the customer’s request.

The electricity used for producing MG‐Si is about 12 000 kWh/metric tons of silicon produced. The global MG‐Si production (average purity of 98.5%) is about two million tons. Most of it goes to the aluminum and chemical industries. The high purity demand by the PV and semiconductor industries absorb about 10% of the production.

Phosphorus, boron, titanium, chromium, and other elements have to be removed in additional steps to obtain the purified silicon. The impurities in MG‐Si make it ineffective in solar cell production as they would lead to crystal defects and trapping levels that affect the cell power output.

The semiconductor‐grade Si is typically seven to nine 9s, whereas a purity of five to six 9s is sufficient for solar‐grade silicon. Typically 1.3–1.6 tons of MG‐Si is needed to produce 1 ton of purified silicon, and some old, inefficient, or small‐size facilities can require as much as 6 tons.

6.1.2 Production of Polysilicon (Silicon Purification)

The next step in the refining process is to react the MG‐Si with hydrochloric acid, commonly in a fluidized‐bed reactor, to form SiHCl₃ (trichlorosilane (TCS)) (Figure 6.3). This reaction, however, also produces by‐products such as SiH₂Cl₂, SiCl₄, and chlorides of impurities. Each of these liquids has its own boiling point, so they are undertaken fractional distillation to separate the SiHCl₃ from the other components. The next step is to extract the silicon from the TCS. This is done by reacting SiHCl₃ with hydrogen in a Siemens reactor (shown in Figures 6.4 and 6.5):

(6.2)

(6.3)

In this process, the TCS is fed into a reactor along with hydrogen, where thin rods of electronic‐grade silicon, of about 8–10 mm diameter, are electrically heated to over 1100°C. Silicon from TCS or silane separates on to the hot silicon rods, reaching a diameter of 15–20 cm (Figure 6.5). For this to happen, it takes several days about 50–60 hours. The Siemens process is highly energy intensive, consuming about 40–50 kWh/kg of polysilicon produced. A lot of this heat is wasted to thermal losses through the reactor wall. To reduce losses, increase productivity, and reduce costs, polysilicon manufacturers have developed large reactors that produce up to 72 rods in each batch; Figure 6.6 shows reactors with 48 rods of polysilicon.

The gases that leave the poly (Siemens) reactor contain TCS, tetrachlorosilane (TET), dichlorosilane (DCS), hydrogen (H₂), and hydrogen chloride (HCl), and optimizing the reuse of them is an interesting systems engineering problem. TCS and TET can be separated with absorption and sent to the distillation processes before the Siemens reactor (Figure 6.3). TET is a by‐product that needs to be either recycled or processed to silica for use by the silicon industry. Recycling into the poly‐Si process can be achieved by converting it to TCS at high temperatures () in the presence of H₂ (Figure 6.7). However such recycling does not currently use all the TET output, and the industry is trying to reduce the TET concentration in the reactor output to eventually close the chlorosilane loop, according to reaction 6.3:

(6.4)

Due to the high energy requirement, alternative poly‐Si manufacturing processes are being investigated. Fluidized‐bed reactor method is one such process that has been utilized in manufacturing by MEMC, REC Silicon, and others. In this process, TCS or silane is fed into the bottom of a fluid‐bed reactor along with hydrogen. The gas stream blends with small particles of silicon fluidizing them and creating what visually looks like a slow boil. Silicon from the TCS or silane deposits onto the particles and thus forms larger granules. Small seed polysilicon particles are fed into the top of the reactor, and product is withdrawn from the bottom of the reactor. Seed addition, gas feed rate, and withdrawal rates are used to maintain the targeted average particle size in the reactor. This requires process temperatures of 700°C for silane and 1000°C for TCS.

In both the Siemens process and fluidized‐bed reactor method, the highly volatile liquid TCS is produced by combining MG‐Si and hydrogen chloride and used as a feedstock. Depending on the reactor technology, it then further purified through distillation and if necessary converted to silane. The fluidized‐bed reactor method consumes significantly less energy than the Siemens process, and it can be operated continuously.

Another promising alternative is directly purified Si (Elkem Solar grade). Such production starts with a carbothermic reduction of quartz to silicon metal (silicon production furnace) and then proceeds with a high‐temperature slag treatment, a hydrometallurgical low‐temperature cleaning, and in the end a directional solidification (DS) where the cleaning steps are fulfilled by cutting away side, bottom, and top; all cutoffs are returned back into the process. This route requires only a fourth of the energy required by the Siemens process; it is pioneered by Elkem Solar (Figure 6.8).

Figure 6.9 shows the basics of these three process paths for producing polysilicon.

6.1.3. Production of Crystalline Silicon

In addition to high purity, a semiconductor should provide clear paths to the movement of electrons and holes so that they do not recombine. So in addition to high purity this requires a certain degree of crystallinity. To produce single‐crystal or multicrystalline silicon from the polycrystalline material, the silicon must be melted and recrystallized. Monocrystalline material is produced by dipping a silicon seed crystal into the melt and slowly pulling it out (Czochralski method), and multicrystalline silicon is typically produced by DS.

6.1.3.1 Single‐Crystal Silicon

The Czochralski (Cz) process starts with chunks of polysilicon stacked inside a graphite crucible lined with high purity quartz, which is inside a furnace (Figure 6.10). The machine is tightly sealed, purged to eliminate gas impurities, and fired. The silicon chunks are melted at about 1450°C and a controlled amount of dopant is added to the melt to form either p‐ or n‐type silicon; a boron precursor is used in the production of p‐type crystals and arsenic or phosphorus in the production of n‐type crystals. Thus, one of the two dopants required for the formation of a p–n junction is introduced here, and the second will be introduced after the ingot is cut into wafers (Section 6.1.3.6, fabrication of the junction).

As the furnace heater ramps to temperature, the crucible begins clockwise rotation. Once the melt has reached the desired temperature, a counterclockwise rotating silicon “seed” crystal is lowered into the molten polysilicon. The melt is slowly cooled to the recipe’s temperature as crystal growth begins around the seed. The seed is then slowly raised (pulled) from the melt, allowing controlled cooling and solidification. The temperature is controlled tightly so that silicon solidifies at the interface between the seed and the melt and the atoms arrange themselves according to the crystallographic structure of the seed. The crystal thus grows both vertically and laterally, aided by a rotation movement, yielding a cylindrical ingot of single‐crystal silicon. The level of purity increases during the growth process since most impurities tend to segregate toward the liquid phase. The growth rate in the Czochralski method (Cz) method is about 5 cm/h, and the cylindrical ingots are typically 1 m long, 15–30 cm in diameter. The crystal is allowed to cool before it is extracted from the crystal puller for further processing. Figure 6.11 shows the top piece of a Cz ingot.

Float‐zone (FZ) process is another method for producing monocrystalline silicon. It also starts from when polysilicon is slowly melted in a cylindrical bath by a coil using radio‐frequency induction. By moving the coil along the bath, the silicon adopts the crystalline structure. A very high purity and also high structural quality can be achieved by performing several passes of the coil, thus maximizing impurity segregation. The typical growth rate is 15–30 cm/h, and the typical ingot is 15 cm in diameter and 1 m in length. FZ silicon is the preferred material for the fabrication of high‐efficiency laboratory record cells, but it is not typically used in commercial production.

6.1.3.2 Multicrystalline Silicon

A simple method of producing multicrystalline silicon entails melting poly‐Si into a crucible and carefully controlling of the cooling rate. During cooling a DS takes place and relatively large crystals grow in columns (Figure 6.12). The nucleation of the silicon atoms commences in many places simultaneously, leading to a myriad of crystals (or grains) of arbitrary shape and crystallographic orientation. Because of its multiple‐grained structure, the material is called multicrystalline.

Each grain is several millimeters to centimeters across, and internally it has the same structure as single‐crystalline silicon. The boundaries between the different grains are the most obvious imperfection in the material, but they are not the only ones. Microdefects are also common and contamination from the crucible can happen as well, not to mention the possible impurities present in the starting silicon. These crystallographic defects and impurities mean that mc‐Si typically has lower electronic quality than the material produced by the CZ method, leading to a typical loss of efficiency of 1% absolute and a wider spread in the production statistics; this difference is, nevertheless, narrowing rapidly. The typical crystallization rate is 3.5 kg/h, and the growth cycle of a complete 160 kg ingot takes 46 h. This is, nevertheless, faster than the CZ method.

Figure 6.13 shows the major steps in the solar‐grade mc‐Si production followed by wafering, cell, and module production. The starting point is quartz, then polysilicon, crystalline solar‐grade silicon, wafers, solar cell, and modules. Shown in this figure are metallurgical silicon chunks produced by the Siemens or fluidized‐bed Si production, and the alternative Elkem Solar Silicon(R) blocks, both of which are precursors to the multicrystalline solar Si production.

6.1.4 Ingot Wafering

Wafering refers to slicing the cylindrical or rectangular brick of mono‐ or multicrystalline material produced from the crystallization phase to the thickness needed for solar cells. As we discussed in Chapter 2, effective absorption of photons by an indirect semiconductor requires a least a 100 µm thickness, although tricks exist for implementing smaller thickness.

The silicon block becomes what is called an “ingot” after the seed end (the top, shown in Figure 6.11) and the tapered end (the bottom) are cut off. These ends are sometimes discarded; however, to avoid a complete material loss, some ends are remelted and used in future crystal specifications. Then the ingot is cut into shorter sections and after quality testing is transferred to the slicing equipment to make thin (e.g., 130–180 µm) wafers. Before slicing, ingots have to be shaped to meet dimensional specifications. The cylindrical CZ ingots are usually reduced to a quasi‐square shape. This implies a loss of about 25% of the material but is necessary if a high packing factor of the cells in the module is required. The large cast silicon parallelepipeds (Figure 6.13) are sawn into smaller bricks. In the case of mc‐Si ingots, the shaping is also used to discard the peripheral regions that are usually heavily contaminated by the crucible, which represents approximately 15% of the ingot. Typical wafer sizes are and . Multi‐wire slurry saw (MWSS) machines can cut simultaneously whole blocks (Figure 6.14). An abrasive slurry (typically with silicon nitride) helps the steel wires cut through silicon, a very hard material indeed, and the cutting is very slow (e.g., ~8 hours). Slicing remains as one of the most costly and wasteful steps of the whole silicon solar cell fabrication. Even if very thin wires are used, approximately 30% of the silicon is wasted as saw dust, called “kerf loss.” However, the industry starts implementing diamond cutting, and this reduces kerf losses.

Since circular wafers mounted in a module leave a large amount of empty space between the wafers, often times the edges of the wafers are trimmed to make the wafers closer to a square. Also the sawing causes significant surface damage, so the wafers are chemically etched to remove any residual slurry and restore the surface. Then, the wafers proceed into a series of refining steps to make them stronger and flatter. First, the sharp, fragile edges are rounded or “profiled” to provide strength and stability to the wafer. This will ultimately prevent chipping or breakage in subsequent processing. Next, each wafer is laser‐marked with very small alphanumeric or bar code characters. This laser‐mark ID gives full traceability to the specific date, machine, and facility where the wafers were manufactured. The wafers are then loaded into a precision “lapping” machine that uses pressure from rotating plates and an abrasive slurry to ensure a more uniform simultaneous removal of saw damage present on both front and backside surfaces. This step also provides stock removal and promotes flatness uniformity—a critical foundation for the polishing manufacturing process.

The following process would be chemical etching or the removal of residual surface damage caused by lapping; it also provides some stock removal. During the etching cycle, wafers progress down another series of chemical baths and rinse tanks with precise fluid dynamics. These chemical solutions produce a flatter, stronger wafer with a glossy finish. All wafers are then sampled for mechanical parameters and for process feedback.

6.1.5 Doping/Forming the p–n Junction

The next step in producing single‐crystal silicon cells is to create the p–n junction. This is accomplished with diffusing into the wafer the dopant that was not introduced during the crystal formation. Most commonly a p‐type dopant (e.g., boron) was introduced in the melt of the Cz crystallization process, and an n‐type dopant (e.g., phosphorus) is diffused into the wafer. The conventional way to diffuse P is to use a diffusion furnace where a P source (typically liquid POCl₃) is transferred by bubbling nitrogen. The diffusion can be performed using a tube furnace in a batch process where approximately 300 wafers are loaded in a quartz boat as shown in Figure 6.15. A phosphorus‐containing gas, phosphoryl chloride (POCl₃), is introduced into the quartz tube furnace, where it reacts with O₂ to form phosphorus pentoxide (P₂O₅) that deposits on the oxidized wafer surface, providing the source of phosphorus atoms that diffuse into the wafer to form an n‐type layer on the wafer’s surface. A typical tube furnace diffusion process takes about 50 minutes and is performed at temperatures in the range of 800–900°C.³

6.1.6 Cleaning Etch

Phosphorus diffuses into all the wafer surfaces and is necessary to clean the front surface from phosphorus atoms to prevent the creation of shunting pathway between the junction and the rear surface. The shunting resistance has to be large to prevent electron losses as shown in Figure 2.23. Usually such cleaning is done by etching the rear surface by HF and HNO₃.

6.1.7 Surface Texturing to Reduce Reflection

Wafers cut from a single crystal of silicon (monocrystalline material) need to be textured to reduce reflection (as discussed in Chapter 2). This can be done by etching pyramids on the wafer surface with a chemical solution. While such etching is ideal for monocrystalline CZ wafers, it relies on the correct crystal orientation and so is only marginally effective on the randomly orientated grains of multicrystalline material. For multicrystalline Si texturing could be done with either lasers or isotropic chemical etching.

6.1.8 Antireflection Coatings and Fire‐Through Contacts

Antireflection coatings are particularly beneficial for multicrystalline material that cannot be easily textured. Two common antireflection coatings are titanium dioxide (TiO₂) and silicon nitride (SiN_x). The metal contacts can be applied at the top of the antireflective coating using screen printing with a paste containing cutting agents.

6.1.9 Edge Isolation

There are various techniques for edge isolation such as plasma etching, laser cutting, or masking the border to prevent diffusion from occurring around the edge in the first place.

6.1.10 Rear Contact

An aluminum layer is printed on the rear on the cell and with subsequent alloying through firing, it produces a back surface field (BSF) and improves the cell bulk through trapping impurities; this thermal treatment is called “gettering” and can be done with either P or Al at temperatures between 700 and 950°C under a controlled O₂ atmosphere, which allows P or Al to diffuse throughout the Si layers and to “getter” eventual metal impurities toward the phosphorus‐ or aluminum‐doped layer. A second print of Al/Ag may be required for solderable contact. In most production, the rear contact is simply made using an aluminum/silver grid printed in a single step.

6.1.11 Encapsulation

The solar cells in numbers of 36 or higher are typically interconnected in series and encapsulated to form a module. The encapsulated materials and processes should protect the module for outdoors operation of 30 years. Typically tempered glass is used for the front cover, ethylene vinyl acetate (EVA) as an adhesive, and Tedlar as a back cover.

These layers are laminated by applying heat at about and pressure under vacuum. The edges are sealed with a neoprene gasket and most often protected with an Al frame. An alternative encapsulation scheme, employed in First Solar’s thin‐film module production, is using a second glass sheet as back cover and a sealing compound without a metal frame.

Feedstock and Ingot Growth

Until about 10 years ago, purification techniques for silicon have been dictated the industry that employs electronic‐grade silicon with purity levels of less than 1 ppb. A significant shift occurred on or about 2008 when the PV industry surpassed the integrated circuit (IC) industry as the largest consumer of refined silicon. Despite decades of steady growth, this transition caused short‐term shortages and price spikes. However, silicon foundries responded by increasing capacity and examining strategies to develop “solar‐grade” silicon. Electronic‐grade silicon is produced primarily using the energy‐intensive Siemens process. As we discussed earlier, new production strategies such as fluidized‐bed technology are being investigated to upgrade MG‐Si, potentially reducing these energy requirements by up to a factor of four. Though less expensive, these techniques often retain higher levels of metals such as Fe and Al than electronic‐grade silicon. While these impurities would be catastrophic in IC manufacturing, such low levels may be tolerable in solar cells. An active area of research is focused on establishing the impurity levels that can be tolerated by solar cells, as well as devising processing strategies to mitigate and/or passivate these defects. Such improvements should reduce both the energy payback time and ecotoxicity associated with silicon production (discussed in Chapter 7).

Wafering

The cost of the silicon feedstock remains a large contributor in manufacturing costs, and kerf loss during cutting to form wafers significantly impacts this cost. To reduce the required amount of polysilicon, the wafer thickness was gradually reduced from 500 µm in 1979 to an average of 180 µm in 2016. The kerf loss, the silicon lost due to sawing, has decreased as well, to about 150 µm/wafer today. With further advances in the MWSS process, it is expected that 120 µm wafers with 120 µm kerf lost would be achieved by 2020. Aside from kerf loss, the MWSS process has the drawbacks of water contamination, high breakage, and high material consumption. To address these drawbacks, alternative wafering methods started being implemented, most notably a wire saw using a fixed diamond abrasive on the wire, instead of slurry. The kerf from diamond‐wire cutting is recyclable in contrast to kerf from the slurry‐based process that is not. However, the cost of the wire is much higher, and this can stand in the way of increasing PV market penetration in markets dominated by artificially cheap fossil fuels. To avoid kerf loss altogether, kerfless cutting and the development of ultrathin silicon (ut‐Si) are pursued.⁴ These approaches are briefly reviewed in the following section.

Kerfless Wafers

Improvements in wire‐saw technology have enabled the reduction of wafer thicknesses to 180 µm at present. However, over 50% of the silicon is lost as silicon sawdust or “kerf.” While this material can be recycled if diamond‐wire cutting is implemented, it would be desirable if the wire‐sawing step could be eliminated altogether. Techniques for the direct production of wafers from the melt include ribbon technologies and ultrathin Si technologies.

The ribbon techniques are edge‐defined film‐fed growth (EFG) and string ribbon silicon technologies. In the EFG process the Si wafers are pulled out from the melt through a graphite die using capillary action. Ribbon silicon is produced by pulling a pair of high‐temperature strings through a crucible of molten Si. These two growth techniques produce vertical sheets of mc‐Si approximately 300 µm thick and up to a 100 mm wide. These technologies were early commercialized, but they became obsolete with the advent of high‐volume, high‐throughput thin wafer production from Asia.

ut‐Si is a promising way to accomplish a kerfless production of Si. This refers to solar cell technology where the photon‐absorbing silicon layer is on the order of 5–50 µm thick. Because silicon has an indirect bandgap, it is often assumed that silicon must be thicker than 100 µm to effectively absorb light. However, theoretical studies showed that with new emitter designs and improved surface passivation strategies, 19.8% efficient devices could be obtained with only 1 m of single‐crystal silicon. If one could produce such materials using a kerfless process, it would result in an order of magnitude reduction in material cost with respect to today’s state‐of‐ the‐art wafers: thus, ut‐Si would merge the benefits of crystalline silicon with those of thin‐film solar cells. Thin silicon is also amenable to use of bifacial architectures, which harvest light from both directions.

There are a few general approaches to the fabrication of ut‐Si. The first strategy employs hetero‐epitaxial growth followed by lift‐off or removal of a sacrificial substrate. Material grown at high rates is typically polycrystalline, necessitating the use of post‐processing techniques such as laser annealing or rapid thermal processing (RTP) to produce the desired material quality. One complication is identifying low‐cost substrates with appropriate properties for these types of processes. A related approach involves deposition a‐Si directly on glass followed by thermal recrystallization. A third approach involves “peeling” ut‐Si layers off from silicon ingot. For example, Silicon Genesis introduced a process where this is achieved through a combination of ion implantation and thermal treatment, producing kerf‐free wafers as thin as 25 µm. Ion implant technology accelerates protons and shoots them into crystalline silicon, where they settle at a finite depth. The hydrogen ions line up at that finite depth, where they are then heated, resulting in a wafer that cleaves right off the substrate along the crystalline plane. The proton energy determines how deep the protons go and therefore sets the thickness of the wafer (Figure 6.16).

Substantial challenges remain once ut‐Si is produced. Achieving high efficiency will require the use of the most advanced technologies for both surface passivation and light trapping. Also commercialization of ut‐Si technologies will need to address the nontrivial challenge of mechanically handling these ultrathin wafers while maintaining high throughput and low cost.⁵

Surface recombination (discussed in Section 2.2.3.4) becomes more important as the wafer thickness decreases, so very‐high‐quality passivation schemes are needed. Excellent results have recently been achieved on thermal SiO₂/plasma‐enhanced chemical vapor deposition SiN_x stacks, but thermal growth of SiO₂ might be less favorable for very thin wafers. An effective low‐temperature approach is to use amorphous silicon (a‐Si), as in a‐Si:H/crystalline silicon heterojunction (HIT) cells. The HIT and effective passivation increase the open‐circuit voltage (V_oc) significantly: an efficiency of 23.7% has already been achieved on a 98 mm thick wafer.

Because front‐to‐rear interconnection and soldering of interconnects will induce too much stress on thin wafers, the International Technology Roadmap for Photovoltaics (ITRPV) roadmap expects 35% of all cells to be rear contact by 2020.⁶ There are three main approaches to rear‐contact cells: metal wrap‐through (MWT), emitter wrap‐through (EWT), and back‐junction (BJ). In the first two approaches, the emitter is still at the front of the device, but holes are laser drilled through the wafer that transports carriers to the rear, through either the metal contacts (MWT) or the emitter (EWT). The main difference between MWT and EWT is that the MWT still has grid lines (but no bus bars) on the front surface. In a BJ cell, the emitter is located at the rear surface, typically in an interdigitated fashion with the BSF. A BJ has the benefit that the contacts can cover almost the whole rear side of the cell, greatly reducing series resistance. All three approaches reduce contact shading, although this is especially true for the EWT and BJ types. So far, large‐area efficiencies of 24.2% have been reached on BJ solar cells and over 20% on MWT cells. An interdigitated back‐contact (IBC) silicon HIT cell (IBC‐HIT) has been reported at an efficiency of 20.2%, but simulations show that 26% conversion efficiency is achievable.

Traditional screen printing is reaching its limits too. It is a “hard contact” technique, which creates yield issues on thin wafers. Furthermore, the aspect ratio of fingers is rather low, resulting in either large contact area (which are high surface recombination areas) or small contacts with high resistance. Finally, the cost of silver in the metallization paste is becoming quite high, at 6–14 ¢/W_p today. All in all, this implies a move away from silver screen printing in the coming years. A first step may be the introduction of stencil printing, providing higher aspect ratios than screen printing, but the preferred option on the somewhat longer term seems to be plating of copper contacts. Reducing the wafer thickness relaxes the demands on the bulk diffusion length for efficient carrier collection but at the same time reduces the amount of light absorbed if no additional light trapping measures are taken. Random pyramidal textures are shown to perform quite well even at 50 µm wafer thickness, with demonstrated efficiencies of over 19%.

Encapsulation

The encapsulation step is responsible for most material and labor costs: as of 2010 it accounted for 30–40% of the total costs per W_p. Hence, there is much to gain by cutting down on material consumption and through automation and increasing throughput.

Front‐to‐rear interconnection through stringing and soldering is responsible for a large fraction of the yield losses today, and with decreasing wafer thickness, this may get worse. There are reports that interconnection yield losses are prevented in a fully automated high‐throughput module assembly line. Because for BJ cells most processing is on the back of the cell, it is possible to attach the wafers to a glass superstrate after processing of the front. This then allows for monolithic processing of the cells, which increases the yield of very thin wafers during cell processing.

6.3.1 CIGS Thin‐Film Manufacturing

The first copper chalcopyrite PV devices were introduced in 1976 in the form of copper indium diselenide (CuInSe₂) by Larry Kazmerski and his coworkers at NREL. CIS has a suboptimal bandgap of 1 eV. However, the bandgap may be continuously engineered over a very broad range (1–2.5 eV) by substituting either Ga for In or S for Se. The abbreviation CIGS(S) is now used to describe this material as current manifestations often involve all five elements. The development of CIGS followed a combination of starts and stops. The early 1990s brought a rapid succession of improvements that elevated device efficiencies to over 16%. Since then cell efficiencies in the laboratory reached a record of 21%. Several companies started production in 2007–2009 with 10–30 MW/year capacities, but as of 2016 only one company, Solar Frontier, Japan, was able to grow and maintain high‐capacity manufacturing.

Substrates used in CIGS manufacturing include soda lime glass, metal foils, or polyimide (PI). The latter has garnered substantial interest for applications where flexible substrates have an advantage like building‐integrated PV (BIPV) and portable power. However, in the case of deposition on flexible substrates, it is critical to match the coefficient of thermal expansion, with highest efficiencies obtained on titanium and stainless steel foils. The insulating nature of PI is advantageous for monolithic integration, but process temperatures are limited to less than 450°C, which limits efficiency.

The basic structure of the CIGS device is quite similar across manufacturers. Fabrication begins with the deposition of a Mo back contact followed by the p‐type CIGS absorber (1–3 µm), a thin buffer layer (50–100 nm), with doped ZnO serving as the transparent front contact (Figure 6.20). Here the similarities end. Scores of firms worked to commercialize this technology, and each appeared to employ a somewhat unique strategy, particularly with respect to the formation of the CIGS absorber. An issue of progress in PV was completely dedicated to the topic of chalcopyrite thin films,5 and the reader is directed to the papers in that issue for a more comprehensive overview of these topics. At present, the performance of commercial modules is 60–70% of the efficiency of champion cells, with much of this difference attributed to the quality of the absorber layer.

The approaches to CIGS fabrication may be classified into three basic categories: co‐evaporation, selenization/sulfurization of metal films, and non‐vacuum solution‐based techniques. Here we assess the major advantages and issues associated with each and conclude this section by addressing the other major issues that impact CIGS manufacturing.

6.3.1.1 Co‐evaporation

Co‐evaporation is the process that has produced world records. This process alternates between copper‐rich and copper‐poor conditions to produce the large grains and graded Ga/In profile characteristic of high‐efficiency material. Companies such as Q‐Cells and Global Solar are pursuing in‐line production using co‐evaporation. There are a number of important practical challenges involved in the manufacturing of CIGS solar cells. Evaporation sources typically have a cosine flux distribution, and it is difficult to introduce sharp changes in composition or maintain uniformity over large areas under the diffuse conditions of high vacuum. In addition, sources must be mounted in a top‐down configuration in order for large glass substrates to be supported and heated to (Figure 6.21).

Another challenge with co‐evaporation is that the relatively unreactive Se must always be supplied in great excess, leading to practical concerns related to condensation and material management.

6.3.2 CdTe PV Manufacturing

CdTe has a number of intrinsic advantages as a light absorber. First, its bandgap of 1.45 eV is well positioned to harness solar radiation. Its high optical absorption coefficient allows light to be fully captured using only 2 µm of material. Like many II–VI compounds, CdTe sublimes congruently: it vaporizes homogeneously, and the compound’s thermodynamic stability makes it nearly impossible to produce anything other than stoichiometric CdTe.

Close‐space sublimation employs diffusion as the transport mechanism; this is typically used in laboratory scales (Figure 6.22), while very high rates (>20 µm/m) are obtained in industrial scales using convective vapor transport deposition (VTD) (Figure 6.23).

As shown in Figure 6.21, there is a feeder providing a stream of powder into a gas flow, which then carries the powder into the hot zone. The powder vaporizes very fast and then through the use of appropriate geometries is directed to a substrate in the form of a vapor flow. The Auger feed device controls powder transport. The inert gas transports powder into the hot zone. The hot zone is created by the heated permeable membrane, and the ceramic shroud is used to control vapor flow toward the substrate as illustrated. Temperatures tend to be higher than in the lab equipment to faster vaporize the CdTe and CdS powders.

Standard CdTe‐based devices employ a superstrate configuration: production begins with a glass substrate followed by the successive deposition of the transparent conducting oxide (TCO), the n‐type window layer (CdS), the p‐type CdTe absorber, and finally the back contact (ZnTe/Cu/C) (Figure 6.24). Part of First Solar’s success has been due to their ability to integrate these various process steps into an in‐line manufacturing process.

Another general element of the CdTe PV success is that the crystallinity of the deposited films can be improved by post‐deposition thermal processing a CdCl₂ vapor; such post‐processing options are not available for CIGS.

The thermal CdCl₂ processing promotes grain growth in the CdS and CdTe films and improves the uniformity and, therefore, the production yield of the modules.

With low manufacturing costs established, the biggest opportunities for CdTe lie in the improvement of device efficiency. Champion cells convert just over 70% of their SQ potential, while commercial modules are at 16.5% power conversion efficiency. Improving efficiency will require enhancements in both current and voltage. The former is perhaps the most straightforward route, as much of the blue region of the solar spectrum is absorbed in the TCO and CdS layers that make up the front contact. In record laboratory cells the FTO may have been replaced with advanced TCOs such as cadmium stannate and ITO. Likewise, the CdS window layer (2.6 eV) absorbs a significant fraction of the blue light. Integration of advanced front contacts into manufacturing appears to be the near‐term strategy. This will not be trivial because ITO is expensive and cadmium stannate is a complex material. Furthermore, it is not clear what might be used to substitute for CdS though sulfides of zinc and indium have attracted significant interest. A new generation of CdTe devices is emerging that instead of CdS incorporate the alloy of CdSeTe in a graded structure with CdTe and ZnTe at the top of the metal contact layer.

The more daunting challenge is improving the voltage. The Voc of champion CdTe cells is well below that of similar bandgap PV materials. For example, the best Voc obtained in CdTe is 230 mV short of GaAs that has a similar bandgap. Short carrier lifetimes are the root of this limitation. The combined effect of defects and grain boundaries limits minority carrier lifetimes in polycrystalline CdTe to few nanoseconds.

A number of fundamental questions must be solved for CdTe PV to move beyond current records and go beyond the current 22.1% record efficiency. At present, the issue of extending carrier lifetime is partially addressed by chemical passivation. Examples include the introduction of O₂ during CdTe growth, post‐deposition CdCl₂ treatments, and controlled diffusion of Cu from the back contact. Fundamental research in understanding these defects and how to passivate them would be transformative, leading to improvements in one of the most promising solar cell technologies.

A final area that deserves attention is the back contact. It is difficult to contact CdTe because it has low conductivity. Moreover, the back contact has been implicated as a potential contributor to degradation. The issues discussed earlier are nontrivial and will require substantial investment and fundamental research to resolve.