3.1.1 Ebers‐Moll Representation of BJT

Figure 3.2(a1)/(a2), (b1)/(b2), and (c1)/(c2) shows the symbols, the basic structures, and the Ebers‐Moll models for NPN/PNP types of BJT, respectively. According to the Ebers‐Moll models, the emitter and collector currents of NPN/PNP‐BJTs are described as

(3.1.1a)

(3.1.1b)

where the typical values of I_SE (reverse saturation current of B‐E junction) and I_SC = α_FI_SE/α_R (reverse saturation current of B‐C junction) are in the order of 10⁻¹⁵∼10⁻¹² and those of α_F and α_R are as follows:

(3.1.2)

Note that the forward and reverse saturation leakage currents are the same as each other and the transistor saturation current I_S:

(3.1.3)

We can use these equations to write the relations between the emitter current i_E and the collector current i_C as

(3.1.4a)

(3.1.4b)

where I_EO = (1 − α_Fα_R)I_SE/I_CO = (1 − α_Fα_R)I_SC is the reverse emitter/collector current, which flows through the B‐E/B‐C junction when the junction is highly reverse biased and the collector/emitter terminal is open so that i_C = 0/i_E = 0, respectively.

Also, we can apply Kirchhoff's Current Law (KCL) to the BJT or the closed surface including its three terminals to write

(3.1.5)

Noting that the reverse emitter/collector currents I_EO/I_CO are negligibly small, the relationships among the three currents i_C, i_E, and i_B of NPN‐BJT with v_BE ≥ 0.7 (forward biased) and v_BC < 0.4 (not forward biased enough) can be written as

(3.1.6a)

(3.1.6b)

(3.1.6c)

(3.1.6d)

According to [H-2], the collector and base currents of an NPN‐BJT can be expressed as

(3.1.7a)

(3.1.7b)

where I_S = α_FI_ES, I_SC = I_S/α_R (typically within 10I_S), and V_A is the Early voltage, whose typical value is 10∼100 V. Here, compared with Eq. (3.1.1), the additional term proportional to v_CE/V_A has been included to account for the Early effect (also called the base‐width modulation effect) that I_S increases as increasing v_CE results in a decrease in the effective base width of BJT. Noting that based on these equations, the collector current i_C can be expressed in terms of v_CE, v_BE, and i_B as

(3.1.8)

we can run the following MATLAB script “plot_iC_vs_vCE.m” to plot i_C versus v_CE (with v_BE = 0.7 V) for several values of i_B as shown in Figure 3.3 where the (dotted) extrapolation of every i_C curve intersects the v_CE‐axis at common point v_CE = −V_A.

3.1.2 Operation Modes (Regions) of BJT

Table 3.1 shows the four operation modes (regions) of NPN‐BJT(Si) determined by the bias conditions of B‐E and B‐C junctions. Note the following:

• When v_BE = 0.7 V and v_CE > 0.3 V so that v_BC = v_BE − v_CE < 0.4, the BJT operates in the forward‐active region.
• v_CE is 0.3 V at the edge of saturation and becomes v_CE,sat = 0.2 V in the ‘deep’ saturation mode.
• In the forward‐active mode where v_BC < 0.4, the first terms (proportional to I_S) are dominant over the second terms (proportional to I_SC) in Eqs. (3.1.7a) and (3.1.7b) so that i_C ≈ β_Fi_B.
• In the reverse‐active mode where v_BC > 0.5, the second terms (proportional to I_SC) are dominant over the first terms (proportional to I_S) in Eqs. (3.1.7a) and (3.1.7b) so that i_C ≈ −(β_R + 1)i_B. This corresponds to Eq. (3.1.6d) where the roles of the collector and emitter terminals have been switched.

3.1.3 Parameters of BJT

To analyze BJT circuits, we need to define the following parameters for the forward‐/reverse‐active mode:

1. Forward‐active mode

   <CE (Common‐Emitter), forward large‐signal (DC) current gain>

   (3.1.9a)

   <CB (Common‐Base), forward large‐signal (DC) current gain>

   (3.1.9b)

   <CE (Common‐Emitter), forward small‐signal (AC or incremental) current gain>

   (3.1.10a)

   <CB (Common‐Base), forward small‐signal (AC or incremental) current gain>

   (3.1.10b)
2. Reverse‐active mode

   <CE (Common‐Emitter), reverse large‐signal (DC) current gain>

   (3.1.11a)

   <CB (Common‐Base), reverse large‐signal (DC) current gain>

   (3.1.11b)

3.1.4 Common‐Base Configuration

Figure 3.4(a) shows a common‐base (CB) NPN‐BJT circuit in which the input is applied to the BEJ (B‐E junction) and the output is available from the BCJ (B‐C junction) so that the base terminal is common between the input and the output. Note that since the BEJ/BCJ are forward/reverse biased, we can expect the BJT to operate in the forward‐active mode (Table 3.1). Also, note that since the BEJ and BCJ are nonlinear resistors, we may have to apply the load line analysis for both the B‐E loop and the B‐C loop.

To perform a comparatively exact analysis considering the nonlinearity of the circuit, we draw the load line on the B‐E characteristic curve (Figure 3.4(b)) where the load line equation can be obtained by applying KVL around the B‐E loop:

(3.1.12)

The intersection of the load line with the B‐E characteristic curve is the operating (bias) point Q_E:

(3.1.13)

where it does not matter which one of many B‐E characteristic curves with different values of v_CB is used to determine the operating point because B‐E characteristic curve varies little with v_CB. Then we draw the load line on the B‐C characteristic curve (Figure 3.4(c)) where the load line equation can be obtained by applying KVL around the B‐C loop:

(3.1.14)

The intersection of the load line with the B‐C emitter characteristic curve for −i_E = 9.3 mA gives the operating point Q_C:

(3.1.15)

To be strict, unless the B‐E characteristic curve varies little with v_CB, we should relocate Q_C with the B‐E characteristic curve for v_CB = 5.35 V and repeat the same process iteratively. Then this theoretical analysis becomes time‐consuming even for such a simple circuit. However, as a practical means, when the BEJ (B‐E junction) is surely forward biased, we often set the BEJ voltage as

(3.1.16)

and instead of performing the load line analysis for the B‐E loop, use Eqs. (3.1.12), (3.1.6c), (3.1.9b), and (3.1.14) together with β_F = 186 (BETADC from the PSpice simulation output file or databook) to obtain the following:

(3.1.17a)

(3.1.17b)

(3.1.17c)

Now, to perform the PSpice simulation, we create an OrCAD/PSpice project named, say, “CB_BJT.opj,” compose the schematic as depicted in Figure 3.4(a), make a Simulation Settings dialog box (with Bias Point analysis type) as depicted in Figure 3.4(d), and run it to get the PSpice simulation output some part of which is shown in Figure 3.4(e). The Bias Point analysis result can also be made seen in the schematic (Figure 3.4(a)) by clicking on the ‘Enable Bias Voltage Display’ and ‘Enable Bias Current Display’ buttons in the tool bar above the Schematic Editor window.

3.1.5 Common‐Emitter Configuration

Figure 3.5(a) shows a common‐emitter (CE) NPN‐BJT circuit in which the input is applied to the BEJ (B‐E junction) and the output is available from the CEJ (C‐E junction) so that the emitter terminal is common between the input and the output. Note that we can expect the BJT to operate in the forward‐active mode since the BEJ/BCJ are forward/reverse biased (Table 3.1).

To perform a comparatively exact analysis considering the nonlinearity of the circuit, we do the following:

• Setting the BEJ voltage to v_BE = 0.7 V, apply KVL around the B‐E loop to find the base current i_B as
  (3.1.18)

• Draw the load line on the C‐E characteristic curve(s) (Figure 3.5(b)) where the load line equation can be obtained by applying KVL around the C‐E loop:
  (3.1.19)

  

• The intersection of the load line with the C‐E characteristic curve for i_B = 50 μA gives the operating point Q_CE:
  (3.1.20)

Most often, as a more practical means instead of the load line analysis, we use Eqs. (3.1.6c), (3.1.18), and (3.1.19) together with β_F = 184 (BETADC from the PSpice simulation output file or databook) to obtain the following:

(3.1.21a)

(3.1.21b)

Whichever of the graphical or analytical methods we may use, we need to check if v_CE > 0.3 V so that the BJT will not enter the saturation mode. If v_CE turned out to be not greater than 0.3 V, then we would have to set v_CE = v_CE,sat = 0.2 V and use Eq. (3.1.19) to find the collector current i_C.

Now, to perform the PSpice simulation, we create an OrCAD/PSpice project named, say, “CE_BJT.opj,” compose the schematic as depicted in Figure 3.5(a), make a Simulation Settings dialog box (with Bias Point analysis type) as depicted in Figure 3.4(d), and run it to get the PSpice simulation result as shown in Figure 3.5(c), which is a part of the PSpice simulation output file that can be seen by selecting View>Output_File from the top menu bar. The Bias Point analysis result can also be made seen in the schematic (Figure 3.5(a)) by clicking on the ‘Enable Bias Voltage Display’ and ‘Enable Bias Current Display’ buttons in the tool bar above the Schematic Editor window.

3.1.6 Large‐Signal (DC) Model of BJT

Figure 3.6(a)/(b)/(c)/(d) shows the large‐signal (DC) models of an NPN‐BJT for the forward‐active/saturation/reverse‐active/cut‐off modes, respectively. Figure 3.7(a) shows a typical (DC driven) BJT biasing circuit. Figure 3.7(b)/(c)/(d) shows its equivalents with the BEJ biasing side replaced by its Thevenin equivalent and with the BJT replaced by its model in the forward‐active/saturation/reverse‐active mode, respectively.

The above MATLAB function ‘BJT_DC_analysis()’ can be used to analyze NPN‐BJT biasing circuits (driven by DC sources) and find the values of V_B,Q, V_E,Q, V_C,Q, I_B,Q, I_E,Q, and I_C,Q (voltages/currents at/through the base, emitter, and collector terminals) at the operating point. Note the following about its usage:

• If the emitter terminal is connected (via R_E) to another voltage source V_EE, the first input argument should be a two‐dimensional vector [V_CC V_EE].
• If the base terminal is connected (via R_B) to another voltage source V_BB, the second and third input arguments should be V_BB and R_B, respectively.

Likewise, the above MATLAB function ‘BJT_PNP_DC_analysis()’ has been composed to analyze typical (DC driven) PNP‐BJT biasing circuits.

Instead of the (linear) large‐signal model as in Figure 3.6, the exponential model of an NPN‐BJT based on Eq. (3.1.7) (with V_A = ∞ to exclude the Early effect) can be used to write KVL equations in v_BE and v_BC along the two paths V_CC‐R_C‐CBJ‐BEJ‐R_E‐V_EE and V_CC‐R_C‐CBJ‐R_B‐V_BB (for the NPN‐BJT circuit in Figure 3.8(a)) as

(3.1.22a)

(3.1.22b)

where

(3.1.23a)

(3.1.23b)

Also, KVL equations in v_EB and v_CB can be written along the two paths V_EE‐R_E‐EBJ‐BCJ‐R_C‐V_CC and V_BB‐R_B‐BCJ‐R_C‐V_CC (for the PNP‐BJT circuit in Figure 3.8(b)) as

(3.1.24a)

(3.1.24b)

where

(3.1.25a)

(3.1.25b)

The following MATLAB function ‘BJT_DC_analysis_exp()’ can be used to analyze an NPN‐BJT biasing circuit (based on the exponential model) and find the values of V_B,Q, V_E,Q, V_C,Q, I_B,Q, I_E,Q, and I_C,Q (voltages/currents at/through the base, emitter, and collector terminals) at the operating point. Note the following about ‘BJT_DC_analysis_exp()’:

• If you want to use it for analyzing a PNP‐BJT circuit, attach the minus sign to the sixth input argument beta.
• The sixth input argument beta is expected to be given as [±β_F β_R I_S].
• In this ‘nonlinear’ approach, active‐or‐saturated is not clear‐cut but only a matter of degree.

3.1.7 Small‐Signal (AC) Model of BJT

Figure 3.18(a)/(b) shows the high/low frequency small‐signal (AC) models of an NPN‐BJT for the forward‐active mode, respectively, where

• g_m: transconductance (gain)
  (3.1.26)
  (3.1.27)
• r_b: base‐spreading resistance (40∼400 Ω)
  (3.1.28)
• r_bc: incremental resistance of B‐C junction (several MΩ)
• C_be (C_D, C_π, CJ E): diffusion capacitance of B‐ E junction (tens to hundreds of pF)
• C_bc (C_T, C_μ, CJ C): transition/depletion capacitance of reverse‐biased B‐ C junction (0.1∼100 pF)

  

• Note that compared with the high‐frequency model in Figure 3.18(a), the low‐frequency model in Figure 3.18(b) has no capacitance because the magnitudes of impedance or reactance of C_be and C_bc are large enough to be regarded as virtually open:
  
  
• Note also that referring to the low‐frequency model in Figure 3.18(b), the transconductance, g_m, is related with the CE, small‐signal (AC) current gain as
  (3.1.29)

3.1.8 Analysis of BJT Circuits

For the analysis of BJT circuits, the following three steps are taken where Table 3.2 shows the notations representing the DC/AC components and total solutions:

To see how the above procedure can be applied, let us consider the BJT circuit in Figure 3.19.1(a) where the roles of the three capacitors are as follows:

• C_s is used for injecting (coupling) the AC input to the base terminal of the BJT and also for blocking the DC source to keep the bias conditions undisturbed.
• C_L is used for extracting the AC output signal from the collector terminal of the BJT without disturbing the DC Q‐point.
• C_E is used to make the AC signal bypass R_E2 so that the emitter resistance should be regarded as R_E1+R_E2 for setting the DC bias conditions and R_E1 for producing AC output signal.

Note that C_s and C_L are called coupling or blocking capacitors while C_E is called a bypass capacitor. Whatever they are called, all of the capacitors are commonly supposed to provide a very large/small impedance (or reactance X_C = 1/ωC) for DC(ω = 0)/AC(ω > 0) signals like being virtually open (X_C = ∞)/short(X_C = 0)‐circuited where ω represents the frequency of the input signal.

Now, along the procedure listed in the above box, we take the following steps:

1. DC Analysis
   • Remove every AC source (by open/short‐circuiting current/voltage sources) and open/short‐circuit every capacitor/inductor to find the DC equivalent circuit as shown in Figure 3.19.1(b).
   • Redraw Figure 3.19.1(b) as Figure 3.19.1(c) by replacing the BEJ biasing side with its Thevenin equivalent and also replacing the BJT with its large‐signal model (Figure 3.6(b)).
   • For the circuit in Figure 3.19.1(c), find the DC voltage/currents corresponding to the operating point Q where the CE, forward large‐signal (DC) current gain βF of the BJT is assumed to be 180.
   (3.1.30)

   

   (3.1.31)
   (3.1.32)
   (3.1.33)

• The DC analysis can be done by running the following statements:

>>VCC=10; betaF=180; betaR=6;
 R1=104000; R2=104000; RC=200; RE=[50 250];
 BJT_DC_analysis(VCC,R1,R2,RC,RE,[betaF,betaR]);

• This yields the following results that conform with the above hand‐calculated results:

 VCC   VEE   VBB   VBQ   VEQ   VCQ     IBQ         IEQ        ICQ
10.00  0.00  5.00  2.90  2.20  8.54  4.05e-005  7.32e-003  7.28e-003
    in the forward-active mode with VCE,Q= 6.35

2. AC Analysis
   • Determine the small‐signal parameters such as g_m, β, and r_be = r_π, r_o, ….
   (3.1.34)
   (3.1.35)
   (3.1.36)
   (3.1.37)
   (3.1.38)

• Remove every DC source (by open/short‐circuiting the current/voltage sources) and short/open‐circuit every (large) capacitor/inductor to find the AC equivalent circuit as Figure 3.19.1(d) where the BJT is replaced by its low‐frequency small‐signal model (Figure 3.18(b)).

  

• To find the voltage gain A_v=v_o/v_i, we remove R_s and R_B=R₁||R₂ and then make a V‐to‐I source transformation for node analysis to get the circuit as shown in Figure 3.19.2(b).
• Then we can set up the node equation as
  
  (3.1.39a)

• In case R_E1 = 0, we have just one‐node circuit and get the voltage gain as
  (3.1.39b)

• Once we have got the open‐loop voltage gain A_vo (with R_L = ∞) and the input/output resistances R_i/R_o (see Eq. (3.2.1)/(3.2.4)), we can easily get the overall voltage gain (considering R_s) as
  (3.1.40)

If we assume that R₁, R₂, and r_o are so large (compared with other resistors) as to be negligible as parallel elements, we can approximate the AC equivalent as Figure 3.19.1(d) so that we can write the (small‐signal) base current i_b, collector current i_c, and output voltage v_o as

(3.1.41)

(3.1.42)

The DC/AC analysis procedure, which has been cast into the MATLAB function ‘BJT_CE_analysis()’ listed above, can be carried out by running the following statements:

>>VCC=10;  Vsm=0.02;  rb=10;  betaF=180;  betaR=6;   betaAC=194;
 Rs=50; R1=104000; R2=104000; RC=200; RE=[50 250];    RL=10000;
 BJT_CE_analysis(VCC,rb,Rs,R1,R2,RC,RE,RL,[betaF betaR betaAC],Vsm);

This yields the following result that conforms with that obtained above:

 gm= 281.664[mS], rbe=  689[Ohm], ro= 1373[kOhm]
 Gv=Ri/(Rs+Ri)xAv = 0.994 x -3.64 = -3.62

Figure 3.20(a), (b), and (c) shows the PSpice schematic of the BJT circuit in Figure 3.19.1(a), its simulation result of the input/output voltage waveforms, and a part of simulation output file containing the netlist and the bias (operating) point information, respectively. Note that the voltage gain can be computed from the ratio between the negative/positive peak values of input/output signals shown in the Probe Cursor box as

(3.1.43)

where the negative sign indicates a phase shift of 180° between the input and the output.

Now, consider the following question:

Won’t the voltage gain and/or the linear input‐output relationship be changed when the amplitude (v_sm) of the AC input voltage v_s increases?

To find out the answer to this question, let us make a soft experiment of increasing v_sm to 0.3 V, 1 V, and 1.5 V. The PSpice simulation results are depicted in Figure 3.21(a), (b), and (c), which show that the upper part of the output voltage waveform is distorted for v_sm = 1 V and both the upper and lower parts of the output voltage waveform are distorted for v_sm = 1.5 V. (This explains the meaning of ‘small‐signal’, illustrating that the small‐signal analysis result based on the linear approximation is valid only within a certain range of the input signal.) Why is that? To understand why the upper and/or lower parts of the output voltage waveform to large inputs are distorted, we should use the load line analysis by drawing the DC load line to determine the operating point Q and drawing the AC load line at the operating point Q (see Figure 3.22(a)) if there exists a (bypass) capacitor (like C_E) connected in parallel with the emitter resistor R_E2 (see Figure 3.19.1(a) or 3.20(a)).

Note that the equations of the DC/AC load lines are obtained by applying KVL through V_CC‐R_C‐v_CE‐R_E as

(3.1.44)

(3.1.45)

where the bypass capacitor C_E is assumed to have a negligibly small reactance 1/ωC_E like a short‐circuit for the input signal frequency ω and the (negative) emitter current −i_E is assumed to be (almost) equal to the collector current i_C since the base current is negligibly small compared with the collector/emitter currents.

Note also that the AC input moves the instantaneous operating point along the AC load line around the quiescent operating point Q, i.e. the intersection of the DC load line and the CE characteristic curve corresponding to the base current i_B determined by the DC biasing circuit. With this background knowledge, Figure 3.22(a) together with b‐d shows how i_C (the collector current) and v_CE (the collector‐to‐emitter voltage) vary with the variation of i_B due to the AC signal. About Figure 3.22, there are several observations to make:

• A BJT crashes into the cutoff region if the amplitude of i_b (the AC component of base current i_B computed roughly by Eq. (3.1.41)) exceeds I_B,Q so that the total base current i_B = I_B,Q + i_b may become zero where

  

  (3.1.46)

• A BJT trespasses on the saturation region if the maximum variation of v_ce (the AC component of collector‐to‐emitter voltage) exceeds V_CE,Q−V_CE,sat(0.2 V) where
  (3.1.47)

• Increasing R_E1 (with the voltage gain A_v [Eq. (3.1.49)] decreased) reduces the DC base current
  (3.1.48)

• and decreases the slope 1/(R_C + R_E1 + R_E2) of the DC load line so that the operating point Q can move left (toward the saturation region) downwards (toward the cutoff region). However, the possibility of the BJT to trespass on the saturation region and/or crash into the cutoff region decreases because the maximum variations of v_ce (Eq. (3.1.47)) and i_c = (β + 1)i_b decrease more abruptly than the operating point Q moves left downwards.

• Decreasing R_E2 (with the voltage gain A_v (Eq. (3.1.49)) unaffected) increases the DC base current I_B,Q (Eq. (3.1.48)) and the slope 1/(R_C + R_E1 + R_E2) of the DC load line so that the operating point Q can move right (away from the saturation region) upwards (away from the cutoff region). Thus, the possibility of the BJT to be saturated and/or cut off decreases.
• Decreasing R_C decreases the maximum variation of v_ce (Eq. (3.1.47)) to reduce the possibility of the BJT to trespass on the saturation region, but it reduces the voltage gain
  (3.1.49)

• Increasing VCC (with the voltage gain A_v unaffected) increases the DC base current I_B,Q (3.1.48) and pushes the v_CE‐intercept rightwards so that the operating point Q can move right upwards. Thus, the possibility of the BJT to be saturated and/or cut off decreases.

The PSpice simulation results of the circuit in Figure 3.19.1(a) or 3.20(a) are depicted in Figure 3.23, which supports the observations stated above. Figure 3.23(a1)/(b1) shows the simulation results and load line analysis for the circuit with R_C = 200 Ω, R_E1 = 50 Ω, and R_E2 = 250 Ω, respectively. Figure 3.23(a2)/(b2) shows the simulation results and load line analysis for the circuit with R_C = 200 Ω, R_E1 = 200 Ω, and R_E2 = 250 Ω, respectively, supporting the observation that increasing R_E1 (with the voltage gain A_v decreased) will move the operating point Q left downwards, but will decrease the maximum variations of v_ce and i_c more abruptly so that the possibility of the BJT to trespass on the saturation region and/or crash into the cutoff region can decrease. Figure 3.23(a3)/(b3) shows the simulation results and load line analysis for the circuit with R_C = 200 Ω, R_E1 = 200 Ω, and R_E2 = 100 Ω, respectively, supporting the observation that decreasing R_E2 (with the voltage gain A_v unaffected) will move the operating point Q right upwards so that the possibility of the BJT to trespass on the saturation region and/or crash into the cutoff region can decrease. Figure 3.23(a4)/(b4) shows the simulation results and load line analysis for the circuit with R_C = 400 Ω, R_E1 = 200 Ω, and R_E2 = 100 Ω, respectively, implying that increasing R_C may increase the voltage gain A_v without trespassing on the saturation region or crashing into the cutoff region thanks to the increase of linearity margin secured by increasing R_E1 and decreasing R_E2.

Can the possibility of a BJT to trespass on the saturation region or crash into the cutoff region be predicted by the MATLAB function ‘BJT_CE_analysis()’? Let us try it for the above four cases:

 >>VCC=10;  Vsm=1.5;  rb=10;  betaF=180;  betaR=6;  betaAC=194;
 Rs=50; R1=104e3; R2=104e3; RC=200; RE=[50 250]; RL=1e4; % (1)
 BJT_CE_analysis(VCC,rb,Rs,R1,R2,RC,RE,RL,[betaF betaR betaAC],Vsm);

  VCC    VEE    VBB   VBQ    VEQ   VCQ     IBQ       IEQ       ICQ
 10.00  0.00   5.00   2.90   2.20   8.54  4.05e-05  7.32e-03  7.28e-03
  in the forward-active mode with VCE,Q= 6.35
 gm= 281.664[mS], rbe=  689[Ohm], ro= 1373[kOhm]
 Possibly crash into the cutoff region
 Possibly violate the saturation region
 Gv=Ri/(Rs+Ri)xAv = 0.994 x -3.64 =  -3.62

 >>Rs=50; R1=104e3; R2=104e3; RC=200; RE=[200 250]; RL=1e4; % (2)
 BJT_CE_analysis(VCC,rb,Rs,R1,R2,RC,RE,RL,[betaF betaR betaAC],Vsm);

  VCC    VEE   VBB   VBQ   VEQ   VCQ     IBQ       IEQ       ICQ
 10.00  0.00  5.00  3.32  2.62  8.84  3.22e-05  5.83e-03  5.80e-03
  in the forward-active mode with VCE,Q= 6.22
 gm= 224.360[mS], rbe=  865[Ohm], ro= 1724[kOhm]
 Possibly crash into the cutoff region
 Gv=Ri/(Rs+Ri)xAvo = 0.998 x -0.95 =  -0.95

 >>Rs=50; R1=104e3; R2=104e3; RC=200; RE=[200 100]; RL=1e4; % (3)
 BJT_CE_analysis(VCC,rb,Rs,R1,R2,RC,RE,RL,[betaF betaR betaAC],Vsm);

  VCC    VEE    VBB    VBQ    VEQ    VCQ    IBQ      IEQ       ICQ
 10.00   0.00   5.00   2.90   2.20   8.54 4.05e-05  7.32e-03  7.28e-03
  in the forward-active mode with VCE,Q= 6.35
 gm= 281.664[mS], rbe=  689[Ohm], ro= 1373[kOhm]
 Gv=Ri/(Rs+Ri)xAv = 0.998 x -0.96 = -0.96

 >>Rs=50; R1=104e3; R2=104e3; RC=400; RE=[200 100]; RL=1e4; % (4)
 BJT_CE_analysis(VCC,rb,Rs,R1,R2,RC,RE,RL,[betaF betaR betaAC],Vsm);

  VCC    VEE    VBB   VBQ    VEQ   VCQ     IBQ        IEQ      ICQ
 10.00   0.00   5.00   2.90   2.20  7.09  4.05e-05  7.32e-03  7.28e-03
  in the forward-active mode with VCE,Q= 4.89
 gm= 281.664[mS], rbe=  689[Ohm], ro= 1373[kOhm]
 Gv=Ri/(Rs+Ri)xAv = 0.998 x -1.88 = -1.88

For the four cases, the MATLAB function ‘BJT_CE_analysis()’ seems to have worked well in terms of its prediction about the possibility of the BJT to be saturated or cut off.

Now, to find the DC power of the BJT for the last case by using MATLAB, run the following MATLAB statements:

>>[VBQ,VEQ,VCQ,IBQ,IEQ,ICQ,Av]=BJT_CE_analysis(VCC,rb,Rs,R1,R2,RC,RE,
                                           RL, [betaF betaR betaAC],Vsm);
>>PQ_DC=(VCQ-VEQ)*ICQ+(VBQ-VEQ)*IBQ % DC power of BJT Q
   PQ_DC= 0.0356 % 35.6mW

The instantaneous (DC + AC) power of the BJT can easily be found as depicted in Figure 3.24(b2) by running the PSpice schematic (Figure 3.24(a2)) with a power (W) marker placed at the center of the device. Why is the instantaneous power p_Q(t) always below the DC power P_Q,DC =35.6 mW of BJT? It is because v_ce i_c < 0 (Figure 3.24(b1)) so that the AC power of the BJT is negative, implying that the BJT Q is acting as an AC source (active element) supplying an AC power to the other parts.

3.1.9 BJT Current Mirror

Consider the circuit of Figure 3.25(a) where the BJT Q₁ is said to be diode‐connected’ or ‘connected in diode configuration’ since its collector and base terminals are short‐circuited so that it behaves like a diode. Why is a BJT used as a diode? It is for efficiency of fabricating integrated circuit (IC) with matched devices. For proper operation of the circuit, the two BJTs Q₁ and Q₂ must be matched in the sense that they have identical current gains (α_F,β_F) and characteristic curves.

Let us analyze the circuit of Figure 3.25(a), which is called a current mirror because the currents of the two matched BJTs sharing the same v_BE are equal. Assume that the voltage sources V1 and V2 forward‐bias the B‐E junctions and reverse‐bias the B‐C junctions (v_BC < 0.4) of both BJTs to let them operate in the forward‐active mode so that v_BE1 = v_BE2 = 0.7 V and

(3.1.50)

(3.1.51)

Noting that the voltage at node 1 (the lump of terminals C1‐B1‐B2) is v_BE1 = 0.7 V, we apply KCL at the node to write

(3.1.52)

which yields the output current as

(3.1.53)

This is supported by the PSpice simulation result (with Bias Point analysis) listed in Figure 3.25(a), which shows that the current i_C2 supplied by the current mirror is constant as about 1.4 mA for different values of V2 and, therefore, the current mirror can be used as a current source.

Let us analyze the circuit of Figure 3.25(b), which is also called a circuit mirror because the currents of the two matched BJTs Q₁ and Q₂ are equal. Assume that the voltage sources V1 and V2 forward‐bias the B‐E junctions and reverse‐bias the B‐C junctions (v_BC < 0.4) of the three BJTs to let them operate in the forward‐active mode so that v_BE1 = v_BE2 = v_BE3 = 0.7 V and

(3.1.54)

(3.1.55)

Noting that the voltage at node 1 (the lump of terminals E3‐B1‐B2) is v_BE1 = 0.7 V and the voltage at node 2 (the lump of terminals C1‐B3) is v_BE1 + v_BE3 = 1.4 V, we can write

(3.1.56)

(3.1.57)

(3.1.58)

This yields the output current as

(3.1.59)

This is supported by the PSpice simulation result (with Bias Point analysis) listed in Figure 3.25(b), which shows that the current i_C2 supplied by the current mirror is constant as about 1.35 mA for different values of V2 and, therefore, the current mirror can be used as a current source.

Let us compare the sensitivities of i_C2 w.r.t. β_F for the two current sources:

(3.1.60)

(3.1.61)

This implies that the current mirror (b) has smaller sensitivity of the output current i_C2 w.r.t. β_F (roughly proportional to ) compared with that of the current mirror (a) (roughly proportional to ).

Now, to analyze the 3‐BJT current mirror (Figure 3.26(a)) and that with R replaced by a current source I (Figure 3.26(b)) by using the exponential model, we apply KCL at nodes 1 and 2 to write

(3.1.62a)

(3.1.62b)

(3.1.62c)

where i_Ck(v_BEk, v_BCk) and i_Bk(v_BEk, v_BCk) are defined by Eqs. (3.1.23a,b), and i_Ek(·,·) = i_Bk(·,·) + i_Ck(·,·) for all k. The following MATLAB function ‘BJT3_current_mirror()’ solves the set of Eqs. (3.1.62a,b) for circuit (a) or Eqs. (3.1.62a,c) for circuit (b) depending on whether the value of the third input argument R is greater than or equal to 1 or not. It returns the output current i_o = i_C2 and v = [v₁ v₂] for possibly several values of V₂ (given as the second to last elements of the fourth input argument V12). For instance, we can solve the circuit of Figure 3.25(b) to get i_o for V1 = 15 V and V2 = {1, 5, 10, 20, 40} by running the following MATLAB statements:

>>R=1e4; Is=1e-14; io=BJT3_current_mirror([100 1],Is,R,[15 1 5 10 20 40])

3.1.10 BJT Inverter/Switch

Figure 3.27(a1)/(a2) shows the PSpice schematics of BJT inverter for Transient/DC_Sweep analysis. Figure 3.27(b1) shows the input and output voltage waveforms of the inverter (obtained from the Transient analysis) where the input 1(high)/0(low) drives the BJT into the saturation/cutoff mode so that the output v_o = v_CE can go to logic 0(low)/1(high) with high‐to‐low/low‐to‐high propagation delay t_pHL/t_pLH that are defined as the times between the 50% input and 50% output.

Note that in order for the BJT to go back and forth between the saturation and cutoff modes, the collector current i_C,sat in the saturation mode should be less than β_F times the base current i_B:

(3.1.63)

This condition can easily be satisfied by taking a small R_B and a large R_C. But the following should be noted:

• A small R_B makes the input impedance small so that the fan‐in of the gate can be decreased where fan‐in is the number of logic gates that can be connected to its input without deteriorating the input signal or producing an undefined or incorrect output.
• A large R_C makes the output impedance and loading effect (due to it) large so that the (output‐high) fan‐out of the gate can be decreased where fan‐out is the number of logic gates that can be connected to its output (as loads) without producing an undefined or incorrect output.

Figure 3.27(b2) shows the input(v_i)‐output(v_o) relationship, called the VTC (voltage transfer characteristic), of the inverter (obtained from the DC Sweep analysis). In the VTC, the output low/high levels V_OH/V_OL are defined as the minimum/maximum values of output v_o corresponding to logic 1/0, respectively and V_IH/V_IL are defined as the minimum/maximum values of input v_s that can be interpreted as logic 1/0, respectively, where V_IL/V_OH are the input/output at point A with slope of −1 and V_IH/V_OL are the input/output at point B with slope of −1. Also, we define the midpoint M as the intersection of the VTC and line v_o = v_i, which can be thought of as the boundary at which the inverter switches its output from one state to the other.

Figure 3.28(a) shows a practical VTC together with an ideal VTC. As measures of how much the gate can tolerate the variation of signal levels without causing any erroneous logical state, Figure 3.28(b1)/(b2) shows the high and low noise margins for practical/ideal VTCs where the high and low noise margins are defined as

(3.1.64)

What are the physical meanings of the high/low noise margins? As can be seen in Figure 3.28(b1) or (b2), the high/low noise margin means how much the high(1)/low(0) signal can decrease/increase without being mistaken for a low(0)/high(1) signal by the next‐stage (load) gate (the same kind of inverter), i.e. without misleading (mistakenly driving) the load inverter into the cutoff/saturation mode like a low/high voltage. The absolute noise margin is defined as the smaller of the two noise margins:

(3.1.65)

Note that the noise immunity measured by the absolute noise margin is maximized by the ideal VTC with abrupt switching at V_IL = V_IH = (V_OL + V_OH)/2, which has maximum logic swing from V(0) to V(1), but no transition region.

To analyze the BJT inverter circuit in Figure 3.27(a1) by using the exponential model, we can apply KVL around the two meshes to write

(3.1.66)

where i_C(v_BE, v_BC) and i_B(v_BE, v_BC) are defined by Eqs. (3.1.23a,b).

Once we solve this set of equations to find v_BE and v_BC for a given value of the input voltage v_i, we can find the output voltage v_o as

(3.1.67)

The process of solving Eq. (3.1.66) to find v_o for v_i = 0~V_CC, finding V_IL,V_IH,V_OL, V_OH, and V_M, and plotting v_o versus v_i has been cast into the above MATLAB function ‘BJT_inverter()’. We can run the following script “plot_VTC_BJT_inverter.m” (which uses ‘BJT_inverter()’)

to get the VTC as shown in Figure 3.28(a) and the inverter parameter values as

 VIL = 0.565, VIH= 0.990, VOL= 0.151, VOH= 4.971, VM= 0.920
 NML = 0.414, NMH= 3.981, VL = 0.031
 Pavg= 12.423[mW]

3.1.11 Emitter‐Coupled Differential Pair

Figure 3.29(a) shows an emitter‐coupled (in the sense that the emitter terminals of the two BJTs are connected) or differential (in the sense that its output varies with the differential input v_d = v_BE1 − v_BE2) pair. To analyze this circuit, we assume that both BJTs operate in the forward‐active mode so that we can use Eq. (3.1.1b) to write their approximate collector/emitter currents as

(3.1.68a)

(3.1.68b)

Then their ratios can be approximately written as

(3.1.69)

Also, we apply KCL at the node E1‐E2 to write

(3.1.70)

Combining Eqs. (3.1.69) and (3.1.70) yields the expression of each collector current as

(3.1.71a)

(3.1.71b)

where these collector currents are depicted in Figure 3.29(b). Then we can write the (differential) output voltage as

(3.1.72)

This differential output voltage v_o, together with v_o1 and v_o2, is shown in Figure 3.29(c). From Figure 3.29 and Eqs. (3.1.71a,b) and (3.1.72), note the following:

• If −1.5V_T < v_d < 1.5V_T, the differential output voltage v_o and other signals vary almost linearly with the differential input v_d, allowing the emitter‐coupled pair to be used as an amplifier with a voltage gain of
  (3.1.73)

• If v_d > 4V_T, we have
  (3.1.74a)

• On the other hand, if v_d < −4V_T, we have
  (3.1.74b)

• It is implied that a large swing of the differential input v_d = ±4V_T makes the two BJTs Q₁/Q₂ operate as closed/open or open/closed switches, producing two distinct levels of differential output v_o depending on whether v_d = 4V_T or v_d = −4V_T.
• The amplifying/switching properties are extensively used in analog/digital circuits, respectively. That is why the emitter‐coupled or differential pair is one of the most important configurations employed in ICs.

  To analyze the BJT differential pair circuit in Figure 3.29(a), we can apply KCL at nodes 1, 2, and 3 to write

  (3.1.75)

  where i_Ck(v_BEk, v_BCk) and i_Bk(v_BEk, v_BCk) are defined by Eqs. (3.1.23a,b). The process of solving this set of equations to find v = [v₁ v₂ v₃] for v_d = −V_dm~V_dm and plotting v_o = v₁ − v₂, i_C1, i_C2 (together with their analytic values computed by Eqs. (3.1.72,74) versus v_d has been cast into the following MATLAB function ‘BJT_differential()’. We can run

  >>betaF=100; betaR=1; Is=1e-14; IEE=10e-3; RC=1e3; VCC=12;
   BJT_differential([betaF betaR],Is,IEE,RC,VCC);
  

  to get the graphs of i_C1, i_C2, and v_o as shown in Figure 3.29(b) and (c).

3.2.1 Common‐Emitter (CE) Amplifier

Figure 3.30 shows a CE amplifier and its low‐frequency AC equivalent (which is the same as Figure 3.19.1(d)) where the BJT has been replaced by the equivalent in Figure 3.18(b), and the biasing resistances R₁||R₂ and BJT output resistance r_o are assumed to be so large as to be negligible as parallel resistors. Let us find the input resistance, current gain, voltage gain, and output resistance.

1. Input Resistance R_i

   To find the input resistance, i.e. the equivalent resistance seen from the source side, we apply KVL for the left mesh (denoted in a gray closed curve) with R_B = R₁||R₂ neglected to write

   

   

   This yields the input resistance as

   (3.2.1)
2. Current Gain A_i

   The output current i_o through the load resistor R_L can be expressed as

   

   Thus, the current gain, i.e. the ratio of the output current i_o to the input current i_i = i_b is

   (3.2.2)
3. Voltage Gains G_vand A_v

   The overall voltage gain, i.e. the ratio of the output voltage v_o to the source voltage v_s is

   (3.2.3)
4. Output Resistance R_o

   To find the (Thevenin) equivalent resistance seen from the load side, we need to remove the (independent) voltage source v_s by short‐circuiting it. Then no current flows of itself so that we have i_b = 0, v_be = 0, and i_c = 0 even if a test voltage or current source is applied to the output port. Therefore, the output resistance turns out to be

   (3.2.4)

   This AC analysis process to find R_i, R_o, A_i, and A_v has been included in the MATLAB function ‘BJT_CE_analysis()’ presented in Section 3.1.8. If a current source supplying a BJT with its DC emitter current I_E,Q is given instead of the biasing circuit as depicted in Figure 3.31(a), the following MATLAB function ‘BJT_CE_analysis_I()’ can be used for the AC analysis.

3.2.2 Common‐Collector (CC) Amplifier (Emitter Follower)

Figure 3.32 shows a CC amplifier and its low‐frequency AC equivalent where the BJT has been replaced by the equivalent in Figure 3.18(b) and the BJT output resistance r_o is assumed to be so large as to be negligible as a parallel resistor. Let us find the input resistance, current gain, voltage gain, and output resistance.

1. Input Resistance R_i

   To find the input resistance from the relationship between v_i = v_b and i_i, we express the voltages at nodes e and b in terms of i_b as

   

   This yields the equivalent resistance R_b seen from terminals b‐G as

   

   so that we can write the input resistance (including R_B = R₁||R₂) as

   (3.2.5)
2. Current Gain A_i

   The output current i_o through the load resistor R_L can be expressed as

   

   Thus, the current gain, i.e. the ratio of the output current i_o to the input current i_i = i_b is

   (3.2.6)
3. Voltage Gains G_vand A_v

   The voltage gain (with R_s = 0) is

   (3.2.7a)

   The overall voltage gain, i.e. the ratio of the output voltage v_o to the source voltage v_s is

   (3.2.7b)

   where R_i is given by Eq. (3.2.5). This implies that if R_s ≪ R_i and r_b + r_be ≪ (β + 1)(R_E||R_L), the output voltage is almost equal to the source voltage and that is why the CC amplifier is called an emitter follower or buffer amplifier.

4. Output Resistance R_o

   To find the (Thevenin) equivalent resistance seen from the load side, we remove the (independent) voltage source v_s by short‐circuiting it and apply a test voltage source V_T to the output port. Then, the base current i_b and the test current I_T through V_T are computed as

   
   

   Thus, we find the output resistance as

   (3.2.8)

   The emitter follower has a very low output resistance (3.2.8), which enables the circuit to provide its load with much current without paying much attention to the loading effect. It also has a very high input resistance (3.2.5), which enables the circuit to save the current provided by its source (driver). In short words, the emitter follower is modest enough not to burden its source as well as generous to its load. (Isn’t the emitter follower praiseworthy? Who can blame such a nice guy for not amplifying the voltage?) That is the main feature of emitter follower with an almost unity voltage gain.

3.2.3 Common‐Base (CB) Amplifier

Figure 3.34.1 shows a CB amplifier and its low‐frequency AC equivalent where the BJT has been replaced by the equivalent in Figure 3.18(b) and the BJT output resistance r_o is assumed to be so large as to be negligible as a parallel resistor. Let us find the input resistance, current gain, voltage gain, and output resistance.

1. Input Resistance R_i

   To find the input resistance from the relationship between v_i = v_e and i_i, we apply KCL at node c to write

   

   

   Thus, we can find the input resistance as

   (3.2.9)

   This input resistance is very small compared with that (Eq. (3.2.1)) of CE amplifier and that (Eq. (3.2.5)) of CC amplifier.

2. Current Gain A_i

   The current through the emitter resistor R_E can be expressed in terms of the base current i_b through r_be‐r_b‐R_B (connected in parallel with R_E) as

   

   Applying KCL at node e yields the expression of the input current i_i in terms of i_b as

   

   The output current i_o through the load resistor R_L can be expressed as

   

   Thus, the current gain, i.e. the ratio of the output current i_o to the input current i_i is

   (3.2.10)
3. Voltage Gains G_vand A_v

   To find the voltage gain A_v = v_o/v_i (with R_s = 0), we apply KCL at node c (of the circuit in Figure 3.34.1(b)) to write the node equation and solve it as

   (3.2.11a)

   The overall voltage gain, i.e. the ratio of the output voltage v_o to the source voltage v_s is

   (3.2.11b)

   where R_i is given by Eq. (3.2.9).

4. Output Resistance R_o

   To find the equivalent resistance seen from the load side, we remove the (independent) voltage source v_s by short‐circuiting it, make a I‐to‐V source transformation of the dependent current source βi_b into the voltage source βi_br_o in series with r_o as shown in Figure 3.34.2. Then we apply a test current source of i_T = 1 A and find the voltage across it:

   (3.2.12)

   This process for analyzing a CB amplifier to find their input/output resistances and voltage/current gains has been cast into the above MATLAB function ‘BJT_CB_analysis()’ and the following one ‘BJT_CB_analysis_I()’ for the case where the amplifier is excited by current source.

The next section will show how the MATLAB functions presented above can be used to analyze a multistage amplifier.

3.2.4 Multistage Cascaded BJT Amplifier

Table 3.3 lists the formulas for finding the input/output resistances, voltage gain, and current gain of the CE/CC/CB amplifiers.

Note that to find the input/output resistance of a CC configuration requires the input/output resistance of the next/previous stage corresponding to its load/source resistance R_L/R_s as implied by Eq. (3.2.5)/(3.2.8). That is why, for a systematic analysis of a multistage amplifier containing one or more CC configurations, we should find the input/output resistance of each stage, starting from the last/first stage backwards/forwards to the first/last stage where the load resistance to each stage except the last one is the input resistance of the next stage and the source resistance to each stage except the first one is the output resistance of the previous stage.

	CE	CC	CB
Ri	RB||{rb + rbe + (β + 1)RE1} (3.2.1)	RB||{rb + rbe + (β+1)(RE||RL)} (3.2.5)	(3.2.9)
Ro	RC||ro ≈ RC (3.2.4)	(3.2.8)	RC‖ro1 (3.2.12)
Av	(3.2.3)	()	()
Ai	(3.2.2)	(3.2.6)	(3.2.10)

Each of the formulas listed in Table 3.3 has been coded in MATLAB as above so that they can be called individually as symbolic expressions whenever and wherever needed.

Let us consider the CE amplifier of Figure 3.36(a1) where the device parameters of the NPN‐BJT Q₁ are β_F = 100, β_R = 1, β_AC = 100, V_A = 10⁴ V, and r_b = 0 Ω. Its PSpice simulation result is shown in Figure 3.36(b1) where the overall voltage gain turns out to be

(3.2.13)

Note that the theoretical value of the overall voltage gain is

(3.2.14)

This can be obtained by running the following MATLAB statements:

>>rb=0; betaF=100; betaR=1; betaAC=100;
 VCC=10; Vsm=0.01; beta=[betaF betaR betaAC];
 Rs=1e4; RL=1e3; R11=7e4; R12=3e4; RC1=5e3; RE1=[0 5e3]; Rs1=Rs; RL1=RL;
 BJT_CE_analysis(VCC,rb,Rs1,R11,R12,RC1,RE1,RL1,beta,Vsm);

which yields

 VCC  VEE  VBB  VBQ  VEQ  VCQ    IBQ       IEQ      ICQ
 10.00 0.00 3.00 2.91 2.21 7.81 4.37e-06 4.42e-04 4.37e-04
 in the forward-active mode with VCE,Q= 5.61[V]
    gm= 16.915[mS], rbe= 5912[Ohm], ro= 22869.57[kOhm]
 Ri=  4.613 kOhm, Ro= 4999 Ohm
 Gv=Ri/(Rs+Ri)xAv= 0.316 x -14.10 =  -4.45

Figure 3.36(a2) and (b2) shows a CE‐CC amplifier and its PSpice simulation result where the p‐p (peak‐to‐peak) value of the overall AC output voltage has turned out to be 20.5 times that of the AC input voltage. To analyze this multistage amplifier (containing a stage of CC configuration), we first find the input resistance of each stage, starting from the last stage backwards to the first stage:

 >>rb=0; betaF=100; betaR=1; betaAC=100;
 VCC=10; Vsm=0.01; Rs=1e4; RL=1e3; beta=[betaF betaR betaAC];
 R21=4e4; R22=6e4; RC2=0; RE2=5e3;
 % Find Ri, Av, and Ai of Stage 2/1 starting from last one
 Rs2=0; RL2=RL; [VBQ,VEQ,VCQ,IBQ,IEQ,ICQ,Av2,Ai2,Ri2,Ro2_0]= ...
  BJT_CC_analysis(VCC,rb,Rs2,R21,R22,RC2,RE2,RL2,beta);
 R11=7e4; R12=3e4; RC1=5e3; RE1=[0 5e3]; Rs1=Rs; RL1=Ri2; Vsm0=Vsm;
 [VBQ,VEQ,VCQ,IBQ,IEQ,ICQ,Av1,Ai1,Ri1,Ro1]= ...
  BJT_CE_analysis(VCC,rb,Rs1,R11,R12,RC1,RE1,RL1,beta,Vsm0);
 % Now, analyze each stage forwards from the 2nd one
 Rs2=Ro1; Vsm1=Ri1/(Rs+Ri1)*Av1*Vsm0
 [VBQ,VEQ,VCQ,IBQ,IEQ,ICQ,Av2,Ai2,Ri2,Ro2]= ...
  BJT_CC_analysis(VCC,rb,Rs2,R21,R22,RC2,RE2,RL2,beta,Vsm1);
 Vom=Av2*Vsm1, Gv = Vom/Vsm, Ri1/(Rs+Ri1)*Av1*Av2

Running these statements yields

 VCC    VEE   VBB   VBQ  VEQ   VCQ     IBQ       IEQ       ICQ
10.00   0.00  3.00  2.91  2.21  7.81  4.37e-06  4.42e-04  4.37e-04
  gm= 16.915[mS], rbe= 5912[Ohm], ro= 22869.57[kOhm] % Stage 1 of CE
 Ri= 4.613kOhm, Ro= 5912Ohm, Gv=Ri/(Rs+Ri)xAv= 0.316 x -66.79 = -21.09
 Vsm1 =  -0.2109
 VCC   VEE   VBB   VBQ   VEQ   VCQ      IBQ       IEQ       ICQ
10.00  0.00  6.00  5.76  5.06  10.00  1.00e-05  1.01e-03  1.00e-03
 gm= 38.756[mS], rbe= 2580[Ohm], ro= 9981.13[kOhm] % Stage 2 of CC
 Ri= 18.799kOhm, Ro= 66 Ohm, Gv=Ri/(Rs+Ri)xAv= 0.79 x 0.97 = 0.77
 Gv = -20.4588 %Overall voltage gain of the CE-CC amplifier

This implies that the overall voltage gain of the CE‐CC stage is −20.5 (as confirmed by the PSpice simulation result G_v,s=−409.1 mV/20 mV=−20.5 in Figure 3.36(b2)), which is much greater than that (−4.45) of the CE stage (Eq. (3.2.14)) despite the additional CC stage whose voltage gain is less than one by itself.

1. (Q) Why is that?

Figure 3.37(a) and (b) shows a three‐stage BJT amplifier consisting of CE‐CE‐CC configurations and its PSpice simulation result where the overall voltage gain has turned out to be G_v,s = 6.64. To analyze this multistage amplifier (containing a CC configuration), we first find the input resistance of each stage, starting from the last stage backwards to the first stage:

>>VCC=20; Vsm=5e-3; rb=0; betaF=100; betaR=1; betaAC=100; Is=1e-16;
 Rs=100; RL=1e4; % Source resistance and Load resistance
 R31=5e4; R32=5e4; RC3=0; RE3=200; beta=[betaF,betaR,betaAC,Is];
 R21=1e5; R22=1e5; RC2=200; RE2=100;
 R11=1e5; R12=1e5; RC1=1e3; RE1=[250 50];
 Rs3=0; RL3=RL; [VBQ,VEQ,VCQ,IBQ,IEQ,ICQ,Av3,Ai3,Ri3,Ro3_0]= ...
     BJT_CC_analysis(VCC,rb,Rs3,R31,R32,RC3,RE3,RL3,beta);
 Rs2=0; RL2=Ri3; [VBQ,VEQ,VCQ,IBQ,IEQ,ICQ,Av2,Ai2,Ri2,Ro2_0]= ...
     BJT_CE_analysis(VCC,rb,Rs2,R21,R22,RC2,RE2,RL2,beta);
 Rs1=Rs; RL1=Ri2; Vsm0=Vsm;
 [VBQ,VEQ,VCQ,IBQ,IEQ,ICQ,Av1,Ai1,Ri1,Ro1]= ...
     BJT_CE_analysis(VCC,rb,Rs1,R11,R12,RC1,RE1,RL1,beta,Vsm0);

where the load resistance R_L and the input resistances R_i3/R_i2 of stage 3/2 have been put as the load resistances of stage 3 and 2/1, successively and respectively. Note that 0 has been put as the third input argument (corresponding to Rs3/Rs2) of ‘BJT_CC_analysis()’/‘BJT_CE_analysis()’ for stage 3/2 because their source or input resistances are not yet known. That is why the output resistance of the CC stage (to be computed by Eq. (3.2.8) depending on R_s) is not expected to have been found properly. However, the source resistance R_s has properly been put as the third input argument of ‘BJT_CE_analysis()’ for stage 1. Running the above MATLAB statements yields the following:

 Result of provisional analysis for Stage 3
 VCC   VEE   VBB    VBQ   VEQ   VCQ     IBQ       IEQ      ICQ
20.00  0.00  10.00  4.94  4.09  20.00  2.02e-04  2.04e-02  2.02e-02
 in the forward-active mode with VCE,Q= 15.91[V]
 where beta_forced = ICQ/IBQ = 100.00 where beta = 100.00
     gm= 782.947[mS], rbe=  128[Ohm], ro=  494.07[kOhm]
 Ri=  11.088[kOhm], Ro=   1[Ohm]
 Gv=Ri/(Rs+Ri)xAv= 1.000x  0.99 =  0.99 % Not yet meaningful
 Result of provisional analysis for Stage 2
 VCC   VEE   VBB   VBQ   VEQ   VCQ      IBQ       IEQ      ICQ
20.00  0.00  10.00  2.38  1.54  16.95  1.52e-04  1.54e-02  1.52e-02
 in the forward-active mode with VCE,Q= 15.41[V]
 where beta_forced = ICQ/IBQ = 100.00 where beta = 100.00
     gm= 589.311[mS], rbe=  170[Ohm], ro=  656.42[kOhm]
 Ri=  8.520[kOhm], Ro=  200[Ohm]
 Gv=Ri/(Rs+Ri)xAv= 1.000x  -1.91 =  -1.91 % Not yet meaningful
 Results of analysis for Stage 1
 VCC   VEE    VBB   VBQ   VEQ   VCQ     IBQ       IEQ       ICQ
20.00  0.00  10.00  4.29  3.46  8.59  1.14e-04  1.15e-02  1.14e-02
 in the forward-active mode with VCE,Q= 5.13[V]
 where beta_forced = ICQ/IBQ = 100.00 where beta = 100.00
     gm= 441.426[mS], rbe=  227[Ohm], ro=  876.33[kOhm]
 Ri=  16.877[kOhm], Ro=  999[Ohm]
 Gv=Ri/(Rs+Ri)xAv= 0.994x  -3.51 =  -3.49

Then, to find the overall voltage gain, we multiply the product of the voltage gains of every stage with the voltage gain of the front voltage divider as

(3.2.15)

 >>Gv=Ri1/(Rs+Ri1)*Av1*Av2*Av3
     ans = 6.6374

How close this is to the PSpice simulation result (6.63) shown in Figure 3.37(b)!

Now, to find the output resistance of the last stage of CC, starting from the first stage forwards to the last stage, we use ‘BJT_CE_analysis()’ (with Rs1 = Rs and RL1 = Ri2), ‘BJT_CE_analysis()’ (with Rs2 = Ro1 and RL2 = Ri3), and ‘BJT_CC_analysis()e’ (with Rs3 = Ro2 and RL3 = RL) for stage 1, 2, and 3, respectively. Here, the analysis of stage 1 does not have to be repeated since it has already been taken care of above.

>>Rs2=Ro1; RL2=Ri3; Vsm1=Av1*Vsm;
 [VBQ,VEQ,VCQ,IBQ,IEQ,ICQ,Av2,Ai2,Ri2,Ro2]= ...
 BJT_CE_analysis(VCC,rb,Rs2,R21,R22,RC2,RE2,RL2,beta,Vsm1);
 Rs3=Ro2; RL3=RL; Vsm2=Av2*Vsm1;
 BJT_CC_analysis(VCC,rb,Rs3,R31,R32,RC3,RE3,RL3,beta,Vsm2);

These MATLAB statements can be run to yield the following:

 Results of analysis for Stage 2
 Ri=  8.520[kOhm], Ro=  200[Ohm]
  Results of analysis for Stage 3
 Ri=  11.088 kOhm, Ro=   3 Ohm

All the above MATLAB statements have been put into the MATLAB function ‘CE_CE_CC()’ so that it can be run by typing the following at the MATLAB prompt:

>>Rs=100; RL=1e4; Vsm=5e-3; VCC=20;
 [Gv,Avs,Ais,Ris,Ros]=CE_CE_CC(Rs,RL,Vsm,VCC)

Note the following about it:

• The BJT parameters such as r_b(rb), β_F(betaF), β_R(betaR), β_AC(betaAC), and I_s have been set to the default values of Qbreak that can be read from the PSpice simulation output file.
• First, to find the input resistances of stage 3(CC), stage 2(CE), and stage 1(CE) (that will be load resistance to their previous stages), ‘BJT_CC_analysis()’, ‘BJT_CE_analysis()’, and ‘BJT_CE_analysis()’ with their third/eigth input arguments Rs3=0/RL3=RL, Rs2=0/RL2=Ri3, and Rs1=Rs/RL1=Ri2, respectively, have been run backwards starting from the last stage. Then the overall voltage gain can be computed as above.
• To get the proper values of Ro2 and Ro3, each stage (starting from the second one) is analyzed forwards by running the corresponding analysis function with the third/eigth input argument Rs2=Ro1/RL2=Ri3 and Rs3=Ro2/RL3=RL, respectively.

The hand calculations to find the input/output resistances can be done as follows:

(3.2.16)

Figure 3.38 shows the PSpice simulation result for measuring the overall output resistance R_o3, which yields the measured value of R_o3 as 10/2.7951 = 3.58 Ω.

Now, let us consider what will happen if we remove the third stage of CC (emitter follower) configuration to make a two‐stage amplifier as depicted in Figure 3.39(a). Then the output voltage across R_L = 100 kΩ will become a bit higher as depicted in Figure 3.39(b1), which can be thought of as a natural result from omitting the CC stage with voltage gain Av3 = 0.98 < 1. However, will we have a similar result even for a smaller load resistor like R_L = 100 Ω? To our surprise, the PSpice simulation result for R_L = 100 Ω depicted in Figure 3.39(b2) shows that the output voltage of the two‐stage amplifier has become much lower than that of the three‐stage amplifier, which reveals the potential value of the CC stage. What is the strength of the CC stage to reduce the loading effect so that the voltage drop due to a larger load (with smaller resistance) can be very small? It is the large input resistance and the small output resistance of CC stage compared with those of CE stage as mentioned in Section 3.2.2. That is why we are willing to pay the extra cost of equipping an amplifier with a CC stage as the last one even if it may lower the output voltage a bit for a normal load.

To use MATLAB for showing the strength of CC stage, we can compose the following MATLAB function ‘CE_CE()’ with R_L as an input argument, which analyzes the two‐stage amplifier consisting of CE‐CE stages. Then we run it and the above MATLAB function ‘CE_CE_CC()’ with RL = 100:

>>Rs=100; RL=100; Vsm=0.01; VCC=20;
 Gv1=CE_CE(Rs,RL,Vsm,VCC), Gv2=CE_CE_CC(Rs,RL,Vsm,VCC)

which yields

 Gv1 =  2.2669  Gv2 =  6.4350

This shows that as the load becomes larger, i.e. as R_L becomes smaller, the role of a CC stage to reduce the loading effect becomes more remarkable.

3.2.5 Composite/Compound Multi‐Stage BJT Amplifier

1. CC‐CE (Darlington) Amplifier

   Figure 3.40(a)/(b) shows CC‐CE (Darlington) amplifiers using two NPN/PNP BJTs, respectively. The amplifiers can be used to achieve a large current gain since the overall output current is the sum of the two BJT collector currents:

   (3.2.17)
2. CC‐CC (Darlington) Amplifier

   Figure 3.40(c) shows a CC‐CC (Darlington) amplifier using two NPN BJTs. This amplifier can also be used to achieve a large current gain since the overall output current is the emitter current of the second BJT:

   (3.2.18)
3. CE‐CB (Cascode) Amplifier

   Figure 3.40(d) shows a CE‐CB (cascode) amplifier using two NPN BJTs. Its output current and output voltage across the collector resistor R_C are

   (3.2.19)

   

   (3.2.20)

   Thus, the current/voltage gains are

   (3.2.21)
   (3.2.22)

   Not only the voltage/current gains but also the input/output resistances are close to those of the CE amplifier (with R_E = 0, R_B = ∞, and R_C in place of R_C||R_L) discussed in Section 3.2.1. Then what is the additional BJT for? Compared with the single‐stage CE amplifier, the load resistance of the first CE stage is the input resistance of the second CB stage, which is so small that the possibility of Q₁ to enter the saturation region can be reduced. That is one of the advantages that we gain from the additional (second) BJT.

   It may be interesting and convenient to use the MATLAB functions listed above for deriving, say, Eq. (3.2.22) (the voltage gain of the CE‐CB (cascode) amplifier shown in Figure 3.40(d)) as follows:

   >>syms  b  b1  b2  ro  ro1  ro2  rbe rbe1 rbe2 Rs RB  RC  RE  RL
    Ri2=subs(Ri_CB,{b,rbe,RB,RE},{b2,rbe2,0,inf})
             %Input resistance from last
    Ri1=subs(Ri_CE,{rbe,RB,RE},{rbe1,inf,0})
    Ro1=subs(Ro_CE,RC,inf); % Output resistance from the first stage
    Ro2=subs(Ro_CB,{b,rbe,Rs,RB,RE},{b2,rbe2,Ro1,0,inf})
    Av1=subs(Av_CE,{b,rbe,RC,RE,RL},{b1,rbe1,inf,0,Ri2})
    Av2=subs(Av_CB,{b,rbe,RB,RE,RL},{b2,rbe2,0,inf,inf})
    Ri=Ri1; Ro=Ro2; % Overall input and output resistances
    Gv=Ri/(Rs+Ri1)*Av1*Av2
   

   where the output resistance R_o1 of stage 1 (CE) has been put as the source resistance R_s2 of stage 2 (CB) to find the output resistance R_o2 of stage 2 and the input resistance R_i2 of stage 2 has been put as the load resistance R_L1 of stage 1 to find the voltage gain A_v1 of stage 1. Running these statements yields the overall input/output resistances and voltage gain as

    Ri1 = rbe1 % The input resistance of the first stage
    Ro2 = RC % The output resistance of the last stage
    Gv = -(RC*b1*b2)/((Rs + rbe1)*(b2 + 1)) % see Eq. (3.2.22)
   

   This result conforms with Eq. (3.2.22). On the other hand, if we consider the (internal) output resistance r_o (due to the Early effect) of each BJT, we can run the following statements:

   >>Ri2=subs(Ri_CB(1),{b,ro,rbe,RB,RE,RL},{b2,ro2,rbe2,0,inf,inf})
   Ri=limit(limit(limit(subs(Ri_CE(1),rbe,rbe1),RB,inf),RC,inf),RE,0)
   Ro1=subs(Ro_CE(1),{ro,RC},{ro1,inf});
   Ro=subs(Ro_CB(1),{b,ro,rbe,Rs,RB,RC,RE},{b2,ro2,rbe2,Ro1,0,inf,inf})
   Av1=limit(limit(subs(Av_CE(1),{b,ro,rbe},{b1,ro1,rbe1}),RL,Ri2),RE,0)
   Av2=subs(Av_CB(1),{b,ro,rbe,RB,RE,RL},{b2,ro2,rbe2,0,inf,inf})
   Gv=Av1*Av2; % Overall voltage gain with Rs=0
   Gvo=limit(Gv,RC,inf); % Overall onen-loop voltage gain with RC=inf
   pretty(simplify(Gvo))
   

   to get the overall input/output resistances and voltage gain of the CE‐CB amplifier with R_s = 0 and R_C = ∞ (open) as

    Ri = rbe1
    Ro = ro2 + ((b2*ro2)/rbe2 + 1)/(1/rbe2 + 1/ro1)
    b1 ro1 (rbe2 + b2 ro2)
    - - - - - - - - - - - - - - -% comparable to the results in Sec. 7.5.6 of [S-2]
    rbe1 (rbe2 + ro1)
   

   This implies

   
   
   

   Note that 1 has been put as the first input argument of the MATLAB functions such as ‘Ri_CB()’ to include the effect of r_o. Note also that the MATLAB function ‘limit()’ is more useful than ‘subs()’ for substituting a zero or an infinity into a complicated MATLAB expression.

3.3.1 DTL NAND Gate

Figure 3.45 shows a basic DTL NAND gate consisting of a diode AND gate cascaded with a BJT inverter where the binary inputs v_i1 and v_i2 are supposed to be one of the two voltage levels corresponding to low (logic 0) and high (logic 1):

(3.3.1)

Let us look over several aspects of the DTL NAND gate.

1. Logic Function

   To check if the circuit operates as a NAND gate, let us consider the following two cases:

   • At least one of the two inputs v_i1 and v_i2 is low as V(0)=V_CE,sat=0.2 V.
   • Both of the two inputs v_i1 and v_i2 are high as V(1)=V_CC=5 V.

2. Fan‐out

   When the output voltage is low, i.e. v_Y = V_CE,sat = 0.2 V with the BJT Q (in the current stage) saturated, it can let the input diode of a load gate (connected to the output node Y) forward‐biased so that the current through R₁ of a load gate (in the next stage)

   (3.3.16)

   can flow back (sink) into the BJT Q of the current stage in addition to the existing collector current (Eq. (3.3.11)) coming through R_C. Therefore, if the number of similar load gates connected to the output node Y is N, the maximum collector current of Q will be

   (3.3.17)

   From the condition that this maximum collector current should be less than β_Fi_B in order to keep Q saturated, we can determine the output‐low fan‐out of the basic NAND gate as the minimum integer satisfying the above inequality (3.3.17):

   (3.3.18)

   How about the output‐high fan‐out of the DTL gate? When the output is high, it can let the input diodes of the load gates reverse‐biased and then the additional current flowing through R_C and going into the next stage is just the sum of the reverse leakage currents that is not so large as to put a limitation on the fan‐out.

3. Role of the Pull‐down Resistor R_B

   If there were no connection through R_B between node B and ground so that i_RB = 0, the base current i_B = i_R1 − i_RB would be larger so that the fan‐out determined by Eq. (3.3.18) could be increased. Then, what is the pull‐down resistor R_B for? Its role is to decrease the turn‐off time (saturation‐to‐cutoff switching time) by providing another path (in parallel with the BE junction of Q) for the reverse base current so that excess minority carriers can be removed quickly from the base while Q enters the cutoff mode from the saturation mode. Note that a smaller value of the pull‐down resistor R_B makes the turn‐off time shorter, but on the other hand, it decreases the base current i_B = i_R1− i_RB, reducing the driving capability (measured by fan‐out).

4. Voltage Transfer Characteristic (VTC) and Noise Margin

   Table 3.4 and Figure 3.46 show the (piecewise linear) VTC of the DTL NAND gate depicted in Figure 3.45. Figure 3.46 also shows the low/high noise margins NM_L/NM_H defined as the maximum widths of the range in which the input voltage can vary without changing the high/low output voltage. Note that the (dotted) VTC for the gate using only one diode between nodes P and B implies that saving one diode results in a considerable reduction of the low noise margin NM_L.

Region	Range of vi [V]	vP [V]	vB [V]	D1‐D2	Q	vY [V]
1	0∼0.5 =	vi + VD, on 0.7∼1.2	0	OFF	Cutoff	5.0
2	0.5∼1.3 =	vi + VD, on 1.2∼2.0	0∼0.5	OFF	Cutoff	5.0
3	1.3∼1.7 =	vi + VD, on~VD, offset 2.0∼2.2	0.5∼0.8	ON	Forward‐active	5.0–0.2
4	1.7∼5.0	VBE, sat + 2VD, on 2.2 V	0.8	ON	Saturated	0.2

3.3.2 TTL NAND Gate

3.3.2.1 Basic TTL NAND Gate Using Two BJTs

Figure 3.47 shows a basic TTL NAND gate using two BJTs where the multiple BEJs (BE junctions) of BJT Q₁ replace the input diodes and the BCJ (BC junction) of BJT Q₁ replaces the diode D1 of the DTL NAND gate. Note that the input clamping diodes are placed to keep the input voltages from going below −0.7 V so that Q₁ can be protected from any large negative input voltage.

To check if the circuit operates as a NAND gate, let the forward/reverse DC current gains be

(3.3.19)

respectively, and consider the following two cases:

• At least one of the inputs is low as V(0) = V_CE,sat = 0.2 V.
• All the inputs are high as V(1) = V_CC = 5 V.

3.3.2.2 TTL NAND Gate Using Three BJTs

Figure 3.49 shows a TTL NAND gate using three BJTs where compared with the basic TTL NAND gate of Figure 3.47, Q₃ increases not only the fan‐out (by raising the overall current gain) but also the noise margin since the BEJ of Q₃ provides an additional diode offset voltage (like D2 in the TTL NAND gate). Let us look over several aspects of the TTL NAND gate.

1. Logic Function

To check if the gate operates as a NAND gate, let us consider the following two cases:

• At least one of the inputs is low as V(0) = V_CE,sat = 0.2 V.
• All the inputs are high as V(1) = V_CC = 5 V.

2. Output‐high Fan‐out

   In Figure 3.50, suppose the output voltage of the driver gate is high, i.e. v_Y = V_CC = 5 V with Q₂ and Q₃ cutoff, which can drive the BJTs (connected to the output node Y), , and of the load gate (in the next stage) into the reverse‐active, saturation, and saturation modes, respectively. Then the load current (flowing into the load gate) equal to the emitter current of can be obtained as

   

   (3.3.43)

   If the number of load gates connected to the output node Y is N, the current through R_C of the driver gate is , which will decrease the output voltage as

   (3.3.44)

   In order for the output voltage v_Y not to be lower than the minimum output voltage 3 V (corresponding to logic 1) for all the voltage drop due to the loading effect, the following condition should be met:

   (3.3.45)

   Therefore the output‐high fan‐out of the TTL NAND gate of Figure 3.49 is 7.

3. Output‐low Fan‐out

   In Figure 3.50, suppose the output voltage of the driver gate is low, i.e. v_Y = V_CE,sat = 0.2 V with the BJT Q saturated, which can drive the BJTs (connected to the output node Y), , and of the load gate (in the next stage) into the saturation, cutoff, and cutoff modes, respectively. Then the load current (flowing from the load gate) equal to the (negative) emitter current of can be obtained as

   (3.3.46)

   If the number of load gates connected to the output node Y is N, the collector current i_C3 of Q₃ in the driver gate will be

   (3.3.47)

   In order for Q₃ not to exit the saturation mode, the following condition should be met:

   (3.3.48)

   This implies that the output‐low fan‐out of the TTL NAND gate of Figure 3.49 is 54. Therefore, the fan‐out of the TTL NAND gate is 9, which is the lower of the output‐low and output‐high fan‐outs.

3.3.2.3 Totem‐Pole Output Stage

Consider again the TTL NAND gate of Figure 3.49 or 3.50 where C_L denotes the capacitive load consisting of parasitic capacitances of wires and reverse‐biased diodes (of the load gates). The capacitive load C_L may cause a long low‐to‐high transition time (as can be seen from Figure 3.27(b1)) since it must be charged from V_CE,sat = 0.2 to V_CC = 5.0 by the current through R_C. A smaller R_C reduces the output delay, but also results in a more power dissipation of (V_CC −V_CE,sat)²/R_C when the output is low, i.e. v_Y = V_CE,sat.

To resolve this dilemma, the (passive) pull‐up resistor R_C is made into an active pull‐up circuit by inserting a BJT Q₄ (together with a diode D) between R_C and Q₃ as depicted in Figure 3.51. The circuit is called a TTL NAND gate with a totem‐pole output stage where totem poles are ancient traditional sculptures that were carved as the emblem of a family or clan by the Northwest American Indian tribes. Since its logic function is the same with the previous NAND gates, let us focus on the role of the totem‐pole output stage consisting of Q₄‐D‐Q₃, especially during the low‐to‐high transition of the output voltage v_Y.

First, let all the inputs of the gate be high. Then the BJTs Q₁, Q₂, and Q₃ will be in the reverse‐active, saturation, and saturation modes, respectively, so that the output voltage can be

(3.3.49)

What difference does the additional BJT(Q₄)‐diode(D) pair make in comparison with R_C alone? It is expected to cut off the current i_RC so that R_C can dissipate no power during the low state of the output. Such an expectation comes true because the voltage difference between B4 and C3 (or Y)

(3.3.50)

is not high enough to turn on Q₄‐D. (It would be not the case without D.)

Now, suppose that at least one of the inputs becomes low. Then the BJTs Q₁, Q₂, and Q₃ operate in the saturation, cutoff, and cutoff modes, respectively, so that the voltage v_B4 = v_C2 can be pulled up high via R₂ enough to turn on (saturate) Q₄‐D where the output voltage (across C_L) will remain at 0.2 V for the moment since the capacitor voltage cannot change instantaneously. Then C_L will be charged by the emitter current of Q₄ (saturated)

(3.3.51)

till i_E4 becomes almost zero and accordingly, Q₄ and D are just at the cut‐in condition with v_BE4=V_BE,offset=0.6 and v_D=V_D,offset=0.5 so that the output will reach

(3.3.52)

1. (Q4) What is the role of the BJT Q₄ placed atop Q₃?

   (A4)

   • Static aspect: when the output voltage is high, Q₄ can afford more load current with a smaller current through and voltage drop across R₂ (with a much smaller output resistance) so that the output‐high fan‐out can be increased.
   • Dynamic aspect: when the output changes from low (with Q₃ saturated) to high (with Q₃ cutoff), Q₄ transfers from cutoff to saturation one jump ahead of the transfer of Q₃ so that it can supply current to C_L (charged to 0.2 V) as a source, reducing the low‐to‐high switching time.
2. (Q5) What is the role of the diode D placed between the two BJTs Q₃ and Q₄?
3. (A5) Without D, the voltage v_B4 − v_C3 = 0.8 V (Eq. (3.3.50)) will turn on Q₄ alone when the output voltage is low as v_Y = v_C3 = V_CE3,sat = 0.2 V so that the collector current i_C4 flowing through R_C may result in a power dissipation.
4. (Q6) What is the role of R_C?
5. (A6) With R₂ = 0, the current determined by Eq. (3.3.51) would increase to reduce the low‐to‐high switch time. However, when Q₄ turns on before Q₃ turns off, the supply voltage V_CC would be short‐circuited through C4‐E4‐D‐C3‐E3, possibly damaging Q₄, D, and Q₃. Therefore, R_C is needed to limit such current spikes.
6. (Q7) Is there any disadvantage of the totem‐pole output stage?
7. (A7) Yes. The disadvantage is a lower output voltage (Eq. (3.3.52)) corresponding to logic 1.

1. Output‐high Fan‐out

   In Figure 3.51, suppose the output voltage of the driver gate is high, i.e. v_Y = 3.9 V with Q₂/Q₃/Q₄ (in the current stage) cutoff/cutoff/saturated~cut‐in, which lets the load current of (Eq. (3.3.43)) flow into N load gates in the next stage. The BJT Q₄ is supposed to use its emitter current i_E4 = β_Fi_B4 to supply this load current while the output voltage obtained by subtracting the voltage drops R₂i_R2 = R₂i_B4, V_BE4,sat, and V_D,on from V_CC should be higher than the minimum output voltage 3 V (corresponding to logic 1):

   (3.3.53)

   Therefore, the output‐high fan‐out of the TTL NAND gate with a totem‐pole output stage of Figure 3.51 is 133. Compare this with Eq. (3.3.45) for the NAND gate without the totem‐pole output stage.

   

2. Output‐low Fan‐out

   In Figure 3.51, suppose the output voltage of the driver gate is low, i.e. v_Y = V_CE,sat = 0.2 V with Q₂/Q₃/Q₄ (in the current stage) saturated/saturated/cutoff. In order for the saturation mode of Q₃ not to be disturbed by the load current (flowing from the load gate), the condition described by Eq. with i_RC = 0 should be satisfied:

   (3.3.54)

   Compare this with Eq. (3.3.48) for the NAND gate without the totem‐pole output stage.

3. PSpice Simulation of the TTL NAND Gate with a Totem‐Pole Output Stage

   Figure 3.52(a)/(b) shows the PSpice schematic and its simulation result (for Transient Analysis with maximum stepsize 1 ns) of the TTL NAND gate with a totem‐pole output stage depicted in Figure 3.51. Here are several observations about the simulation result (Figure 3.52(b)) where one of the two input voltages is fixed as 4 V(HIGH) and the other v₁(t) is a rectangular pulse plotted as a green line:

   

   • When the input v₁(t) is LOW/HIGH, the output v_Y(t) is HIGH/LOW. This implies that the circuit works fine as a NAND gate.
   • When at least one of the inputs, say, v₁(t) plotted as a blue line is LOW (0.2 V), Q₁/Q₂/Q₃/Q₄/D are in the saturation/cutoff/cutoff/cut‐in/cut‐in modes, respectively, but Q₄ and D momentarily enter the saturation mode with v_CE4 ≤ 0.2 V and v_D ≥ 0.75 V, respectively, (before cut‐in) to charge C_L during the LOW‐to‐HIGH transition time of v_Y(t). After transients, Q₄ and D are in the cut‐in mode where v_CE4 = 0.66 V, v_BE4 = 0.66 V, v_D = 0.55 V, and i_D = 15 μA.
   • When all the inputs are HIGH (3.9 V), Q₁/Q₂/Q₃/Q₄/D are in the reverse‐active/saturation/saturation/cutoff/cutoff modes, respectively, where v_BC1 = 0.75 V, v_BE2 = 0.82 V, v_CE2 = 0.038 V, v_BE3 = 0.82 V, v_CE3 = 0.018 V, v_BE4 ≤ 0.5 V, v_CE4 = 4.6 V, and v_D ≤ 0.4 V.
   • The high output voltage is 3.8 V, being close to 3.9 V predicted by Eq. (3.3.52), but the low output voltage is 0.018 V, being lower than V_CE3,sat = 0.2 V (predicted by Eq. (3.3.49)).

3.3.2.4 Open‐Collector Output and Tristate Output

The output impedance of the TTL NAND gate (with totem‐pole output stage) is very low irrespective of whether its output is HIGH or LOW. In most cases, the low output impedance is desired because it contributes towards improving the fan‐out capability by reducing the loading effect. However, in the case of bus contention where different gates attempt to drive a wired‐OR output (as depicted in Figure 3.53(a)) into different logic states, the low output impedance is not good because it may cause an excessive current to flow from HIGH‐output gates to LOW‐output gates. Against such a happening, open‐collector outputs (as depicted in Figure 3.53(b)) can be used where each one of the gates with an open‐collector output drives the wired‐OR output LOW if it wants a LOW output; otherwise it lets its output float (leaving up to other gates’ decision) so that the wired‐OR output can be pulled up HIGH (via an external pull‐up resistor connected to VCC) only when no gate pulls down the output by asserting LOW.

Another measure against bus contention is to use the tristate output illustrated in Figure 3.53(c) where if the (low‐active) Disable input is 0.2 V (LOW), the BJTs Q₁, Q₂, and Q₃ are in the saturation, cutoff, and cutoff modes, respectively, and the diode D is ON so that v_B4=v_Dis+v_D,ON=0.2+0.7=0.9[V]. This voltage will turn on just Q₄‐R₄ so that v_B5=v_B4−0.7=0.2[V]. This voltage is not sufficient to turn on Q₅. Thus, both Q₃ and Q₅ are OFF so that the gate can let its output float with a very high output resistance when is low. Otherwise, i.e. if is high, the gate performs a usual NAND function. This gate is said to have a tristate or three‐state output because it presents three outputs, i.e. HIGH, LOW, and FLOAT (high impedance) states. The input is used to select only one gate among the gates that are wired‐OR connected. Note that the tristate outputs must be pulled up or down to keep the output from being floated, i.e. indeterminate or in the high impedance (Hi‐Z) state when all the drivers are disabled.

3.3.3 ECL (Emitter‐Coupled Logic) OR/NOR Gate

Figure 3.54 shows an ECL (Emitter‐Coupled Logic) OR/NOR gate, which consists of a differential amplifier using emitter‐coupled pair (Section 3.1.11), a reference voltage supplier, and a level shifter. Compared with the TTL family, the ECL family achieves very fast switching and short propagation delays by keeping the BJTs in the forward‐active mode (away from the saturation mode) so that there can be no excessive stored charge to remove quickly. However, it exhibits more power consumption, reduced noise margin, smaller voltage swing, and higher fan‐out capability.

Here is a rough analysis of the ECL circuit in Figure 3.54, which is designed to have all the BJTs operate in the forward‐active mode although the two input BJTs Q₁ and Q₂ may be saturated when the corresponding input voltage v_i1/v_i2 is much higher than V_ref = 2.25 [V] supplied to the base B3 of Q₃. The reference voltage supplier consisting of R_C4‐Q₄‐R₄‐Q₈‐R₈ supplies the nodes B3 and B7 with

(3.3.55a)

(3.3.55b)

The BJT Q₇, given v_B7 = 1.15 [V] at its base terminal B7, produces its emitter current

(3.3.56)

so that Q₇ makes the current i_C7 = α_Fi_RE/(1 + α_F) ≈ 1.75 [mA] through Q₁|Q₂|Q₃‐Q₇‐R_E like a current source of 1.75 [mA]. This current i_C7 ≈ 1.75 [mA] will flow through R_C (with Q₁ and/or Q₂ in the forward‐active mode and Q₃ in the cutoff mode) if any one of the two inputs v_i1 and v_i2 is higher than v_B4 = 2.25[V]= V_ref; otherwise, i.e. none of the inputs is higher than v_B4 = 2.25[V] = V_ref, the current i_C7 ≈ 1.75 [mA] will flow through R_C3 (with Q₁ and Q₂ in the cutoff mode and Q₃ in the forward‐active mode). In the former case, the emitter voltages of Q₅ and Q₆ will be

(3.3.57a)

(3.3.57b)

In the latter case, the emitter voltages of Q₅ and Q₆ will be

(3.3.58a)

(3.3.58b)

As an exception, when the input voltage v_i1/v_i2 is much higher than V_ref = 2.25[V] (supplied to the base B3 of Q₃), the corresponding BJT Q₁|Q₂ will be saturated with v_CE ≤ 0.2[V] so that v_NOR will rise with the input voltage v_i:

(3.3.59)

This rough analysis results are supported by the VTC that is obtained from the PSpice simulation (with DC Sweep analysis type) and depicted in Figure 3.55(b1). Note that the input voltages v_i1/v_i2 applied to the ECL gates should never be much higher than V_ref = 2.25 [V] to keep the BJTs Q₁|Q₂ from being saturated.

3.4.1 Design of CE Amplifier with Specified Voltage Gain

To maximize the AC swing of output voltage v_o along the AC load line (see Figure 3.56.2) of CE amplifier (Figure 3.56.1(a)), it may be good to set the collector current I_C,Q and collector‐to‐emitter voltage V_CE,Q of BJT at the operating point Q as half the maximum collector current and about one third of V_CC, respectively, and also to determine such a value of R_C that the i_C intercept of the AC load line can be about 2I_C,Q:

(3.4.1)

(3.4.2)

Here, R_E1, which is a part of the AC resistance , has been neglected because it is presumably much less than (R_C||R_L) as well as has not yet been determined.

Then, in the DC equivalent circuit, the emitter and collector resistors are supposed to share the voltage drop V_CC−V_CE,Q = (1−K_C)V_CC:

(3.4.3)

where

(3.4.4)

Now, to determine the resistances R₁ and R₂ of DC biasing circuit (Figure 3.56.1(b)), we let the equivalent base resistance R_B=R₁||R₂ be 1/10 times the equivalent emitter resistance (β_F+1)R_E:

(3.4.5)

Then, the equivalent base voltage source V_BB and the biasing resistances R₁ and R₂ are determined as follows:

(3.4.6)

(3.4.7a)

(3.4.7b)

Now, with the transconductance g_m and base‐emitter resistance r_be

(3.4.8)

Eq. (3.2.3) is used to determine the dual emitter resistance [R_E1, R_E2] so that the desired voltage gain A_v,d can be achieved:

(3.4.9)

Note that the minimum power ratings of R₁, R₂, R_C, R_E1, and R_E2 should be

(3.4.10)

This procedure of designing a CE amplifier with a specified voltage gain A_v,d gain has been cast into the following MATLAB function ‘BJT_CE_design()’ where the default values of design constant Kc and ambient temperature T are set to 1/3 and 27 [^oC], respectively.

To use the function for designing a CE BJT (Q2N2222) amplifier with voltage gain A_v,d = ‐20, we run the above MATLAB script “design_CE_BJT.m,” which yields

>>design_CE_BJT
 Design Results
   R1        R2      RC      RE1       RE2       Avd
  13945     9147    309      14        277       20
 Results of analysis using the PWL model
  VCC    VEE   VBB  VBQ   VEQ  VCQ     IBQ      IEQ      ICQ
  18.00  0.00  7.13  6.55  5.85 11.81 1.06e-04  2.01e-02  2.00e-02
  gm= 773.667[mS], rbe=  244[Ohm], ro=  5.00[kOhm]
  Gv=Ri/(Rs+Ri)xAv= 0.974 x -19.88 = -19.37

These results mean the following values of the resistances of designed CE amplifier:

(3.4.11)

where the BJT parameters, the source/load resistances, and V_CC are given as

(3.4.12)

The results of using ‘BJT_CE_analysis()’ (see Section 3.2.1) to analyze the designed circuit are

with the expected voltage gain −19.37, transconductance g_m = 0.774, and BEJ resistance r_be = 244 Ω.

Figure 3.57(a) and (b) shows the PSpice schematic of the designed CE amplifier and its simulation results. Although the resulting voltage gain A_v,PSpice = −3.7172/0.2 = −18.6 is somewhat smaller than A_v,d = −20 required by the design specification, the difference is not so big as to damage the reliability of the MATLAB design and analysis functions.

3.4.2 Design of CC Amplifier (Emitter Follower) with Specified Input Resistance

Let us consider how to determine the values of resistors constituting the CC amplifier (Figure 3.58(a)) such that the input resistance (Eq. (3.2.5)) has a given value R_i,d.

(3.4.14)

To maximize the AC swing of output voltage v_o, it may be good to let the C‐E junction and R_E share the applied voltage V_CC half and half (at the operating point Q) in the DC equivalent circuit (Figure 3.58(b) or (c)) so that

(3.4.15a,b)

KVL around the V_BB‐R_B‐0.7 V‐V_E loop yields

(3.4.16)

From Eqs. (3.4.15b) and (3.4.16), we can have the expressions of R_E and R_B in terms of I_C,Q as

(3.4.17a)

(3.4.17b)

where R₂ has been assumed to be open‐circuited to maximize the range of R_B. Then it is key to choose I_C,Q from the range (I_C,max/100, I_C,max/2) such that Eq. (3.4.14) with Eqs. (3.4.17a,b) can be satisfied. Once such a value of I_C,Q is determined, the resistances R_E, R₁=R_B, the resulting input resistance R_i, and the output resistance R_o can be computed using Eqs. where Eqs. (3.4.14) (or Eq. (3.2.5)) and (3.2.8) have been coded in the MATLAB function ‘BJT_CC_analysis()’. However, if I_C,Q turns out to be small enough to endanger the swing of AC collector current, i.e.

(3.4.18)

then another BJT with larger current gain β_F should be used. This procedure of designing a CC amplifier with a specified input resistance R_i,d has been cast into the above MATLAB function ‘BJT_CC_design()’ where the default values of I_C,max and ambient temperature T are set to 0.8 and 27[°C], respectively.

To use the function for designing a CC BJT (Q2N2222) amplifier with input resistance, R_i,d = 50 kΩ, we run the above MATLAB script “design_CC_BJT.m,” which yields

 >>design_CC_BJT
  Design Results
   R1         RE      Rid       ICQ
  98810       536    50000   0.01680
 Analysis Results
  VCC   VBQ   VEQ   VCQ      IBQ        IEQ       ICQ
 18.00  9.72  9.02 18.00  8.38e-005  1.68e-002  1.68e-002
  in the forward-active mode with VCE,Q= 8.98
 Ri= 47.175[kOhm], Ro= 2[Ohm]
 Gv=Ri/(Rs+Ri)xAv = 0.999 x 1.00 = 1.00

These results mean the following values of the resistances of the designed CC amplifier:

(3.4.19)

where the BJT parameters, the source/load resistances, and V_CC are given as

(3.4.20a)

(3.4.20b)

The results of using ‘BJT_CC_analysis()’ (see Section 3.2.2) to analyze the designed circuit are

(3.4.21)

'Is the input resistance R_i = 47.175 kΩ of designed CC amplifier close to R_i,d = 50 kΩ?

Figure 3.59(a) and (b) shows the PSpice schematics and their simulation results for measuring the input/output resistances of the designed circuit. The PSpice measured input resistance R_i,PSpice = V_s/I_s − R_s = 0.1 V/1.984 μA − 50 Ω = 50.35 kΩ is very close to R_i,d = 50 kΩ required by the design specification. The PSpice measured output resistance R_o,PSpice = 0.1 V/62.793 mA = 1.59 Ω is close to R_o = 1.8 Ω predicted by the MATLAB analysis result.

3.5.1 CE Amplifier

Figure 3.60(a) and (b) shows a CE amplifier circuit and its high‐frequency small‐signal equivalent, respectively, where one more load capacitor C_LL, in addition to the output capacitor C_L, is connected in parallel with the load resistor R_L. For the equivalent circuit shown in Figure 3.60(b), a set of three node equations in V₁, V₂ = V_c, and V₃ = V_e can be set up as

(3.5.1)

where

(3.5.2)

Here, I_Nt and Y_B are the values of Norton current source and admittance looking back into the source part from terminals 1 to 0 as shown in Figure 3.60(c1) and (c2). This equation can be rearranged into a solvable form with all the unknown terms on the LHS as

(3.5.3)

and solved for V₁, V₂, and V₃. Then the transfer function and frequency response can be found as

(3.5.4)

This process to find the transfer function and frequency response has been cast into the following MATLAB function ‘BJT_CE_xfer_ftn()’.

Note the following about the internal capacitances of a BJT, the base‐to‐emitter capacitance C_be, the base‐to‐collector capacitance C_bc, and the collector‐to‐emitter capacitance C_ce [W-7]:

• C_ce can usually be ignored since C_ce ≪ C_be.
• C_be and C_bc can be modeled as voltage‐dependent capacitors with values determined by
  (3.5.5)

• where C_be0(CJE)/C_bc0(CJC): zero‐bias B‐E/B‐C junction capacitances, V_BE,Q/V_BC,Q: quiescent B‐E/B‐C voltages[V], m_be(MJE)/m_bc(MJC): B‐E/B‐C grading coefficient, and ϕ_be(VJE)/ϕ_bc(VJC): B‐E/B‐C built‐in potential[V].

Referring to Figure 3.61, four break (pole or corner) frequencies determining roughly the frequency response magnitude can be determined as [R-2]

(3.5.6a,b)

(3.5.6c,d)

Note the following about these four break frequencies:

• ω_C1, related with the coupling capacitor C_s, is obtained as the reciprocal of the product of C_s and the equivalent resistance as seen from C_s (see Figure 3.61(a)).
• ω_C2, related with the output capacitor C_L, is obtained as the reciprocal of the product of C_L and the equivalent resistance as seen from C_L (see Figure 3.61(c)).
• ω_C3, related with the internal capacitors C_be|C_bc, is obtained as the reciprocal of the product of (C_be+C_m) and the equivalent resistance as seen from C_be (see Figure 3.61(b)).
• ω_C4, related with the internal capacitors C_bc|C_LL, is obtained as the reciprocal of the product of (C_n+C_LL) and the equivalent resistance as seen from C_LL (see Figure 3.61(d)).
• The passband of the CE amplifier will be approximately lower‐/upper‐bounded by the second/third highest break frequencies where not only the values but also the order of the frequencies varies with the values of the related capacitances and resistances.

Note also that R_i/R_o are the input/output resistances of the CE amplifier, respectively, and C_m/C_n are the Miller equivalent capacitances for capacitor C_bc seen from the input/output sides, respectively (see Eq. (1.4.2)):

(3.5.7)

The following MATLAB function ‘break_freqs_of_CE()’ uses Eqs. (3.5.6a,b) to find the four break frequencies:

3.5.2 CC Amplifier (Emitter Follower)

Figure 3.63(a) and (b) shows a CC amplifier circuit and its high‐frequency small‐signal equivalent, respectively, where one more load capacitor C_LL, in addition to the output capacitor C_L, is connected in parallel with the load resistor R_L. For the equivalent circuit shown in Figure 3.63(b), a set of three node equations in V₁, V₂ = V_e, and V₃ = V_c can be set up as

(3.5.8)

where

(3.5.9)

Solving this set of equations, we can find the transfer function and frequency response as

(3.5.10)

This process to find the transfer function and frequency response has been cast into the above MATLAB function ‘BJT_CC_xfer_ftn()’.

There are four break (pole or corner) frequencies determining roughly the frequency response magnitude:

(3.5.11a,b)

(3.5.11c,d)

where R_i/R_o are the input/output resistances of the CC amplifier, respectively, and C_m/C_n are the Miller equivalent capacitances for capacitor C_be seen from the input/output side, respectively (see Eq. (1.4.2)):

(3.5.12)

Note that Eq. (3.5.11) is just like Eq. (3.5.6) with C_bc and C_be switched.

The following MATLAB function ‘break_freqs_of_CC()’ uses Eqs. (3.5.11a,b) to find the four break frequencies:

3.5.3 CB Amplifier

Figure 3.65(a) and (b) shows a CB amplifier circuit and its high‐frequency small‐signal equivalent, respectively, where one more load capacitor C_LL, in addition to the output capacitor C_L, is connected in parallel with the load resistor R_L. Note that if the terminal B(ase) is not AC grounded via a capacitor C_B, we should let C_B = 0 in Figure 3.65(b). For the equivalent circuit shown in Figure 3.65(b), a set of three node equations in V₁ = V_e, V₂ = V_c, and V₃ = V_b can be set up as

(3.5.13)

where

(3.5.14a,b,c)

(3.5.14d,e)

Solving this set of equations, we can find the transfer function and frequency response as

(3.5.15)

This process to find the transfer function and frequency response has been cast into the above MATLAB function ‘BJT_CB_xfer_ftn()’.

There are four break (pole or corner) frequencies determining roughly the frequency response magnitude:

(3.5.16a,b)

(3.5.16c,d)

where R_i/R_o are the input/output resistances of the CB amplifier, respectively, and

(3.5.17)

The following MATLAB function ‘break_freqs_of_CB()’ uses Eqs. (3.5.16a,b) to find the four break frequencies:

Problems

1. 3.1 Circuit with an NPN‐BJT Forward Biased

   Consider the BJT biasing circuit in Figure P3.1.1(a) where the device parameters of the BJT Q₁ are β_F = 154, β_R = 6.092, and I_s(saturation current) = 14.34⁻¹⁵ A.

   1. Referring to Figure P3.1.1(b), find i_C and v_CE of the circuit with R_C = 1 kΩ, R_E = 1 kΩ, and V_CC = 5 V by hand. Then do the same thing two times, once (based on the piecewise linear [PWL] model) by using

      

      

       BJT_DC_analysis(VCC,R1,R2,RC,RE,[betaF,betaR]);
      

      and once (based on the exponential model) by using

       BJT_DC_analysis(VCC,R1,R2,RC,RE,[betaF,betaR,Is]);
      

   2. Noting that v_CE = 0.3 V at the edge of saturation, find such a value of R_C that Q₁ is just barely saturated where R_E = 1 kΩ and V_CC = 5 V.
   3. Referring to Figure P3.1.1(c), find i_B, i_C, and v_CE of the circuit with R_C = 3.3 kΩ, R_E = 1 kΩ, and V_CC = 5 V by hand. Then do the same thing two times, once (based on the PWL model) by using

       BJT_DC_analysis(VCC,R1,R2,RC,RE,[betaF,betaR]);
      

      and once (based on the exponential model) by using

       BJT_DC_analysis(VCC,R1,R2,RC,RE,[betaF,betaR,Is]);
      

   4. Referring to Figure P3.1.2, perform the PSpice simulation to see if the above two analysis results are fine and compare the results with the corresponding MATLAB analysis results.
2. 3.2 Circuit with an NPN‐BJT Reverse Biased

   Consider the BJT biasing circuit in Figure P3.2.1(a) where the device parameters of the BJT Q₁ are β_F = 154, β_R = 6.092, and I_s(saturation current) = 14.34⁻¹⁵ A. Note that the roles of the collector and emitter terminals of a BJT are switched when the BJT is reverse biased.

   

   

   1. Referring to Figure P3.2.1(b), find i_C and v_EC of the circuit with R_C = 1 kΩ, R_E = 1 kΩ, and V_CC = −5 V by hand. Then do the same thing two times, once (based on the PWL model) by using

       BJT_DC_analysis(VCC,R1,R2,RC,RE,[betaF,betaR]);
      

      or

       BJT_DC_analysis(VCC,VBB,RB,RC,RE,[betaF,betaR]);
      

      and once (based on the exponential model) by using

       BJT_DC_analysis_exp(VCC,R1,R2,RC,RE,[betaF,betaR,Is]);
      

   2. Referring to Figure P3.2.1(c), find i_C and v_EC of the circuit with R_C = 1 kΩ, R_E = 6 kΩ, and V_CC = −5 V by hand. Then do the same thing two times, once (based on the PWL model) by using

       BJT_DC_analysis(VCC,R1,R2,RC,RE,[betaF,betaR]);
      

      and once (based on the exponential model) by using

       BJT_DC_analysis(VCC,R1,R2,RC,RE,[betaF,betaR,Is]);
      

   3. Referring to Figure P3.2.2, perform the PSpice simulation to see if the above two analysis results are fine and compare the results with the corresponding MATLAB analysis results.
3. 3.3 Circuit with PNP‐BJT

   Consider the PNP‐BJT biasing circuit in Figure P3.3.1(a) where the device parameters of the PNP‐BJT Q₁ are β_F = 100, β_R = 1, and I_s(saturation current) = 10 × 10⁻¹⁵ A, respectively.

   1. Referring to Figure P3.3.1(b), find i_C and v_EC of the circuit with R_C = 1 kΩ, R_E = 1 kΩ, and V_EE = 5 V by hand. Then do the same thing two times, once (based on the PWL model) by using

       BJT_PNP_DC_analysis(VEE,R1,R2,RE,RC,[betaF,betaR]);
      

      and once (based on the exponential model) by using

       BJT_DC_analysis_exp([VCC VEE],R1,R2,RC,RE,                               -[betaF, betaR,Is]);
      

   2. Noting that v_EC = 0.3 V at the edge of saturation, find such a value of R_C that Q₁ is just barely saturated where R_E = 1 kΩ and V_EE = 5 V.
   3. Referring to Figure P3.3.1(c), find i_C and v_EC of the circuit with R_C = 3.2 kΩ, R_E = 1 kΩ, and V_EE = 5 V by hand. Then do the same thing two times, once (based on the PWL model) by using

       BJT_PNP_DC_analysis(VEE,R1,R2,RE,RC,[betaF,betaR]);
      

      and once (based on the exponential model) by using

       BJT_DC_analysis_exp([VCC VEE],R1,R2,RC,RE,                                    -[betaF, betaR,Is]);
      

   4. Referring to Figure P3.3.1(d), find i_C and v_CE of the circuit with R_C = 1 kΩ, R_E = 1 kΩ, and V_EE = −5 V by hand. Then do the same thing two times, once (based on the PWL model) by using

       BJT_PNP_DC_analysis(VEE,R1,R2,RE,RC,[betaF,betaR]);
      

      and once (based on the exponential model) by using

       BJT_DC_analysis_exp([VCC VEE],R1,R2,RC,RE,
                                 [betaF,betaR,Is]);
      

      

   5. Referring to Figure P3.3.2, perform the PSpice simulation to see if the above three analysis results are fine by comparing the results with the corresponding MATLAB analysis results obtained above. Note that the device parameters of the NPN‐BJT Q₁ (QbreakN) and PNP‐BJT Q₂ (QbreakP) picked up from the PSpice library ‘breakout.olb’ should be set in the PSpice Model Editor window as shown in Figure 3.14(b2).

   

4. 3.4 Two‐BJT Circuit

   Consider the two‐BJT circuit in Figure P3.4(a) where the device parameters of the BJTs Q₁ and Q₂ are β_F = 100, β_R = 1, and I_s = 10⁻¹⁴ A in common.

   1. Referring to Example 3.7, analyze the circuit to find I_C1, V_EC1, I_C2, and V_CE2.
   2. Use the MATLAB function ‘BJT_PNP_DC_analysis()’/ ‘BJT_DC_analysis()’ to analyze the Q₁/Q₂ part, respectively. To this end, run the following MATLAB statements:

      >>betaF=100; betaR=1; Is=1e-14; beta=[betaF betaR];
       VEE1=10; VCC2=10; R1=3e5; R2=2e5;
                RE1=55e2; RC1=5e3; RC2=4e3; RE2=4e3;
       [VB1,VE1,VC1,IB1,IE1,IC1,mode1]= ...
       BJT_PNP_DC_analysis(VEE1,R1,R2,RE1,RC1,beta);
       VBB2=???; RB2=???; % Thevenin equivalent of Q1 seen from B2
       BJT_DC_analysis(VCC2,VBB2,RB2,RC2,RE2,beta);
      

      Also, referring to the MATLAB script “elec03e07.m,” complete the above script “elec03p04.m” and run it to do the exponential‐model‐based analysis.

   3. Referring to Figure P3.4(c), use the PSpice software to simulate the circuit where the device parameters of the NPN‐BJT Q₁ (QbreakN) and PNP‐BJT Q₂ (QbreakP) picked up from the PSpice library ‘breakout.olb’ should be set in the PSpice Model Editor window as shown in Figure 3.14(b2). Fill Table P3.4 with the PSpice simulation results and the MATLAB analysis results (obtained in (b)). Which one is closer to the PSpice simulation results, the PWL‐model‐based solution or the exponential‐model‐based solution?

   

   	IC1	VEC1	IC2	VCE2
   PWL model based analysis	0.785 mA
   Exponential‐model‐based analysis		1.65 V		3.42 V
   PSpice simulation			0.808 mA

5. 3.5 Three‐BJT Circuit

   Consider the three‐BJT circuit in Figure P3.5(a) where the device parameters of the BJTs Q₁, Q₂, and Q₃ are β_F = 100, β_R = 1, and I_s = 10⁻¹⁴ A in common.

   1. Analyze the circuit to find I_C1, V_EC1, I_C2, V_CE2, I_C3, and V_EC3. Noting that the Q₁‐Q₂ part of the circuit is identical to the circuit of Figure P3.4(a), you can copy all the analysis results (except for V_C2) of Problem 3.4.

      

      	IC1 (mA)	VEC1 (V)	IC2 (mA)	VCE2 (V)	IC3 (mA)	VCE3 (V)
      PWL‐model‐based analysis	0.785	1.76	0.788	3.69	0.438	5.37
      Exponential‐model‐based analysis	0.795	1.65	0.819	3.42	0.475	4.98
      PSpice simulation	0.790	1.70	0.808	3.51	0.464	5.10

   2. With the analysis result of the Q₁/Q₂ part (except for V_C2) obtained in Problem 3.4, go on to use the MATLAB function ‘BJT_PNP_DC_analysis()’ for the analysis of the Q₃ part.
   3. Referring to Figure P3.5(b), use the PSpice software to simulate the circuit. Fill Table P3.5 with the PSpice simulation results and the MATLAB analysis results (obtained in (b)).
6. 3.6 Complementary BJT Pair Circuit

   Consider the complementary BJT pair circuit in Figure P3.6.1(a) where the device parameters of the NPN‐/PNP‐BJTs Q₁/Q₂ are β_F = 100, β_R = 1, and I_s (saturation current) = 10 × 10⁻¹⁵ A. Note that the Kirchhoff's voltage law (KVL) along the mesh B1‐E1‐E2‐B2 yields

   (P3.6.1)

   This implies that both v_BE1 and v_EB2 cannot be positive so that Q₁ and Q₂ cannot be simultaneously conducting.

   1. For v_i = 10 V, find i_i, i_o, and v_o.
   2. For v_i = 5 V, find i_i, i_o, and v_o.

      

   3. For v_i = 0 V, find i_i, i_o, and v_o.
   4. For v_i = −5 V, find i_i, i_o, and v_o.
   5. For v_i = −10 V, find i_i, i_o, and v_o.
   6. Complete the above MATLAB function ‘BJT2_complementary()’ to analyze the circuit and use it to get i_i, i_o, and v_o for v_i = {10, 5, 0,−5,−10} by running the following MATLAB statements:

      >>Ri=1e4; RL=1e3; betaF=100; betaR=1;
       Is=1e-14; beta=[betaF betaR];
       VCC1=5; VCC2=-5; VCC=[VCC1 VCC2]; vis=[10 5 0 -5 -10];
       [vs,iis,ios]=BJT2_complementary(vis,Ri,RL,VCC,beta,Is);
       fprintf(' vi v1 vo ii io
      ')
       disp([vis' vs iis' ios'])
      

   7. Referring to Figure P3.6.1(b), perform the PSpice simulation with the Analysis type of Bias Point for v_i = 5 V.
   8. Perform the PSpice simulation (with the Analysis type of DC Sweep and Sweep variable Vi) and the MATLAB analysis (using the MATLAB function ‘BJT2_complementary()’) for v_i = [−10:0.02:10]V to get the two graphs shown in Figure P3.6.2, respectively.

   

7. 3.7 Current Mirror Consisting of Two BJTs
   1. Consider the current mirror in Figure 3.25(a) where the device parameters of the NPN‐BJTs Q₁ and Q₂ are β_F = 100, β_R = 1, and I_s (saturation current) = 10 × 10⁻¹⁵ A in common. Referring to the MATLAB function ‘BJT3_current_mirror()’ presented in Section 3.1.9, compose a MATLAB function ‘BJT2_current_mirror()’ and use it to get i_o = i_C2 for V1 = 15 V and V2 = {1, 5, 10, 20, 40} by running the following MATLAB statements:

      >>betaF=100; betaR=1; Is=1e-14; beta=[betaF betaR];
       R=1e4; V1=15; V2=[1 5 10 20 40];
       io=BJT2_current_mirror(beta,Is,R,[V1 V2])
      

   2. Consider the current mirror in Figure P3.7(a) where the device parameters of the NPN‐BJTs Q₁, Q₂, and Q₃ are β_F = 100, β_R = 1, and I_s (saturation current) = 10 × 10⁻¹⁵ A in common. Show that the output current i_o = i_C3 is determined as

      

      (P3.7.1)

      This is supported by the PSpice simulation result (with DC Sweep analysis) shown in Figure P3.7(b). However, why is the output current negative for V2 < 0.66 V?

   3. Referring to the MATLAB function ‘BJT3_current_mirror()’ presented in Section 3.1.9, compose a MATLAB function ‘BJT3_current_mirror_Wilson()’ to analyze the current mirror of Figure P3.7(a) and use it to get the plot of i_o = i_C3 versus V2 = {0:0.01: 40} for V1 = 15 V.
8. 3.8 BJT Inverter

   Consider the BJT inverter in Figure P3.8(a) or 3.27(a) where the device parameters of the NPN‐BJT Q are β_F = 100, β_R = 1, and I_s (saturation current) = 10 × 10⁻¹⁵ A.

   1. Complete the following approximate v_i‐v_o relationship and find the approximate slope of the VTC of the inverter with the BJT Q₁ operating in the forward‐active mode:
      (P3.8.1)

   

   2. Complete the following MATLAB script “elec03p08b.m,” which uses the MATLAB function ‘BJT_inverter()’ presented in Section 3.1.10 to plot the VTCs and their linear approximations for R_B = 10 kΩ/20 kΩ where R_C = 1 kΩ and V_CC = 5 V as shown in Figure P3.8(b).
   3. Perform the PSpice simulation (with the Analysis type of DC Sweep and Sweep variable Vi) to plot the VTCs for R_B = 10 kΩ/20 kΩ where R_C = 1 kΩ and V_CC = 5 V as shown in Figure P3.8(c). Note that to have multiple waveforms (obtained from different simulations) plotted in a single graph in the Probe (PSpice A/D) window, select File>Append_Waveform(.DAT) on the menu bar to pick up the existing data file(s). If you want to save a data file obtained from the current simulation, say, to plot it together with another data (to be obtained afterward), rename the data file appropriately, which can be located by selecting the menu File>Append_Waveform(.DAT).
9. 3.9 ECL (Emitter‐Coupled Logic) – Differential Pair

   Consider the two BJT differential pairs, called emitter‐coupled logic (ECL), each in Figure P3.9(a1) and (a2) where the device parameters of all the NPN‐BJTs are β_F = 100, β_R = 1, and I_s (saturation current) = 10 × 10⁻¹⁵A in common.

   1. Referring to Eq. (3.1.72), which shows v_o1 and v_o2 of the ECL in Figure 3.29, and assuming that both BJTs Q₁ and Q₂ operate in the forward active region, complete the following expressions (in terms of the differential input voltage v_i) for v_o1 and v_o2 of the ECL in Figure P3.9(a1):

      

      (P3.9.1a)
      (P3.9.1b)
   2. Compared with the ECL in Figure P3.9(a1), the ECL in Figure P3.9(a2) has two more BJTs Q₃ and Q₄ that are expected to shift v_o1 and v_o2 (up/down) by one base‐emitter drop V_BE3 ≈ 0.6 V and V_BE4 ≈ 0.6 V, respectively, as can be seen by comparing the output waveforms of Figure P3.9(b1) and (b2) (MATLAB analysis results) or c1 and c2 (PSpice simulation results).
   3. To analyze the ECL circuit of Figure P3.9(a1) using the exponential model of BJT, apply KVL across each of R_C1 and R_C2 and apply KCL at node 3 to write the following equations:
   (P3.9.2a)
   (P3.9.2b)
   (P3.9.2c)

   where i_Ck(v_BEk,v_BCk) and i_Bk(v_BEk,v_BCk) are defined by Eqs. (3.1.23a,b), and i_Ek(˖,˖) = i_Bk(˖,˖) + i_Ck(˖,˖) for all k. Then complete the above MATLAB function ‘ECL1()’ so that it can analyze the ECL and run the following statements to plot the output waveforms as shown in Figure P3.9(b1).

   >>betaF=100; betaR=1; Is=1e-14; RC=2e3; IEE=3e-4;
    Vref=-0.9; VEE=-5.2;
    ECL1([betaF betaR],Is,RC,IEE,Vref,VEE);
   

   4. To analyze the ECL circuit of Figure P3.9(a2) using the exponential model of BJT, apply KVL across each of R_C1, R_C2, R₁, and R₂ and apply KCL at node 5 to write the following equations:
      (P3.9.3c)
      (P3.9.3d)
      (P3.9.3a)
      (P3.9.3b)
      (P3.9.3e)

      where i_Ck(v_BEk,v_BCk) and i_Bk(v_BEk,v_BCk) are defined by Eqs. (3.1.23a,b), and i_Ek(+,+) = i_Bk(+,+) + i_Ck(+,+) for all k. Then complete the above MATLAB function ‘ECL2()’ so that it can analyze the ECL and run the following statements to plot the output waveforms as shown in Figure P3.9(b2).

      >>betaF=100; betaR=1; Is=1e-14; RC=2e3; IEE=3e-4;              Vref=-0.9; VEE=-5.2;
       RC=2e3; R=42e3; IEE=3e-4; Vref=-0.9; VEE=-5.2;
       ECL2([betaF betaR],Is,RC,R,IEE,Vref,VEE);
      

10. 3.10 CB Amplifier

    Consider the CB amplifier in Figure P3.10(a1) or (a2) where the device parameters of the NPN‐BJT are β_F = 100, β_R = 1, β_AC = 100, r_b = 0 Ω, and I_s = 10 × 10⁻¹⁵ A.

    1. Complete the following MATLAB script “elec03p10.m” and run it to find the overall voltage gain G_v and input/output resistances R_i/R_o. Is the result of DC analysis using the PWL model of BJT closer to the PSpice simulation result shown in the schematic (Figure P3.10(a1) or (a2)) than that using the exponential model?

       

    2. Are the values of G_v, R_i, and R_o close to those obtained from the PSpice simulations shown in Figure P3.10(b1), (b2), and (b3)?
11. 3.11 CC Amplifier

    Consider the CC amplifier in Figure P3.11(a1) or (a2) where the device parameters of the NPN‐BJT are β_F = 100, β_R = 1, β_AC = 100, r_b = 0 Ω, and I_s = 10 × 10⁻¹⁵ A.

    1. Complete the following MATLAB script “elec03p11.m” and run it to find the overall voltage gain G_v and input/output resistances R_i/R_o. Is the result of DC analysis using the PWL model of BJT close to that using the exponential model?
    2. Are the values of G_v, R_i, and R_o close to those obtained from the PSpice simulation shown in Figure P3.11(b1), (b2), and (b3)?

       

12. 3.12 Two‐Stage BJT Amplifier

    Consider the two‐stage BJT amplifier in Figure P3.12(a) where the device parameters of the NPN‐BJT Q are β_F = 100, β_R = 1, β_AC = 100, and r_b = 0 Ω. Complete the following MATLAB script “elec03p12.m” and run it to find the overall voltage gain G_v and output resistance R_o2.

    • (Note) As long as no CC amplifier (whose input/output resistances are affected by the input/output resistances of the next/previous stage, respectively) is involved, it will be enough to analyze each stage starting from the last one with the source resistance of every stage (except for the first one having the true value of R_s) set to 0 and with the load resistance of every stage (except for the last one having the true value of R_L) set to the input resistance of the next stage.

    

13. 3.13 Three‐Stage BJT Amplifier

    Consider the three‐stage BJT amplifier in Figure P3.13.1(a) where the device parameters of all the NPN‐BJTs are β_F = 100, β_R = 1, β_AC = 100, r_b = 0 Ω, and I_s = 1 × 10⁻¹⁶ A in common. Note that the first two stages are identical to those of the amplifier in Figure P3.13(a), whose overall voltage gain and output resistance are G_v12 = 1329.8 and R_o2 = 6795 Ω, respectively.

    1. Complete the above MATLAB script “elec03p13.m” and run it to find the overall voltage gain G_v, and the voltage gains (A_vk's) and input/output resistances (R_ik/R_ok's) of each stage k. Is the value of G_v close to that obtained from the PSpice simulation shown in Figure P3.13.1(b1)? If you are not satisfied, try with the exponential model of BJT.
    2. Determine the values of the open‐loop voltage gains {A_{v1_o}, A_{v2_o}, A_{v3_o}} (with R_i2 = ∞, R_i3 = ∞, and R_L = ∞ to exclude its next stage) and the output resistances {R_{o1_0}, R_{o2_0}, R_{o3_0}} (with R_s = 0, R_s2 = 0, and R_s3 = 0 to exclude its previous stage) of each stage. Check if the following relations hold between the voltage gains {A_v1, A_v2, A_v3} (considering the next stage) and the open‐loop voltage gains {A_{v1_o}, A_{v2_o}, A_{v3_o}}:
       (P3.13.1)
       • Do you see that R_{ok_0}≠R_ok for any stage k? Why is that?

       

       

    3. With the values of R_{ok_0}'s and R_ik's together with the open‐loop voltage gain A_{vk_o}'s for k = 1, 2, and 3 (obtained in (b)), complete the voltage source model of the three‐stage amplifier (Figure P3.13.2) and find the overall voltage gain.
    4. Use the voltage source model to determine the overall voltage gain G_v12 of the CE‐CE stage (with the CC stage removed). Is it smaller than G_v in spite of not having a CC stage with voltage gain A_v3 = 0.991 smaller than 1? Why is that?
    5. Figure P3.13.1(b2) shows another PSpice simulation result on the current i_o for the PSpice schematic with R_L replaced by a sinusoidal voltage source of 1 mV (Figure P3.13.1(c)) and the original voltage source short‐circuited for removal. From the simulation result, find the output resistance R_o and see if it is close to the theoretical value obtained in (a).
14. 3.14 Design of CE Amplifier Circuit

    Consider the CE BJT amplifier circuit of Figure 3.52.1(a) where the forward DC/AC current gains, reverse DC current gain, and base resistance of the BJT are β_F = 162/β_AC = 176, β_R = 6, and r_b = 10 Ω, respectively.

    1. Considering the load resistance R_L = 50 kΩ, determine such resistor values that the voltage gain A_v,d = −20 can be achieved with the operating point located near Q₁ = (V_CE,Q,I_C,Q) = (3 V, 2 mA). Analyze the designed circuit with source/load resistance R_s = 50 Ω/R_L = 50 kΩ to find the voltage gain A_v. Is it close to A_v,d = −20?

       (Hint) How about running the following MATLAB statements?

       >>bF=162; bR=6; bAC=176; rb=10; T=27; % Device constants
        VCC=12; Rs=50; RL=5e4; % Circuit constants
        Avd=20; VCEQd=3; KC=VCEQd/VCC;
        ICQd=2e-3; % Design constants [R1,R2,RC,RE1,RE2]=...
        BJT_CE_design(VCC,[bF bAC],rb,Avd,ICQd,RL,T,KC);
        Vsm=0.1; beta=[bF bR bAC];
        [VBQ,VEQ,VCQ,IBQ,IEQ,ICQ,Av]=...
         BJT_CE_analysis(VCC,rb,Rs,R1,R2,RC,[RE1 RE2],RL,beta,Vsm)
       

    2. Referring to Figure P3.14(a), perform the PSpice simulation of the designed CE amplifier with Time‐Domain Analysis to see the output voltage v_o(t) to an AC input v_s(t) = V_sm sin (2000πt) (with V_sm = 0.05 V) for 2 ms (with maximum step size 1 us). Is the voltage gain V_om,p‐p/2V_sm close to A_v obtained in (a)? Also, on the collector characteristic curves of BJT Q2N2222 (used in the CE amplifier), draw the load line to find the operating point (V_CE,Q, I_C,Q) and check if it agrees with the analysis result (obtained in (a)) and PSpice simulation result.

       

    3. Perform the PSpice simulation of the designed CE amplifier twice more to see the output voltage v_o(t) to an AC input v_s(t) = V_sm sin (2000πt) with larger small‐signal input amplitudes V_sm = 0.15 V and 0.2 V. If the output voltage waveforms are distorted on the upper/lower part, discuss the reason of the distortion in connection with the possibility of the (dynamic) operating point (moved by the small‐signal input) to enter the cutoff/saturation region. Does the MATLAB function ‘BJT_CE_analysis()’ (with the input voltage amplitude V_sm = 0.15/0.2 given as the 10th input argument) give you appropriate warning messages about the possibility of saturation or cutoff regions?
    4. To reduce the distortion of v_o(t), change the resistor values so that the operating point can be located at Q₂ = (V_CE,Q, I_C,Q) = (4 V, 2 mA) and Q₃ = (V_CE,Q, I_C,Q) = (5 V, 4 mA). Perform the PSpice simulation of the designed CE amplifiers to see the output voltage v_o(t) to an AC input v_s(t) = V_sm sin (2000πt) with V_sm = 0.2 V. Discuss the relationship between the static operating point location and the possibility of distortion.
15. 3.15 Frequency Response of a BJT Cascode Amplifier

    Consider the BJT cascode amplifier with PSpice schematic and simulation result on the frequency response in Figure P3.15(a) and (b), respectively, where V_CC = 12 V, R_s = 50 Ω, C_s = 100 μF, R₁ = 100 kΩ, R₂ = 100 kΩ, R₃ = 50 kΩ, R_E = 2 kΩ, C_E = 100 μF, C_B = 100 μF, R_C = 3 kΩ, C_L = 1 μF, R_L = 100 kΩ, C_LL = 1 nF, and the values of the BJT parameters of the (high‐frequency) small‐signal equivalent in Figure P3.15(d) (based on the model in Figure 3.18) are β_F = 100, β_R = 1, β_AC = 100, V_A = 10⁴ V, I_s = 10⁻¹⁴ A, r_b = 0 Ω, C_be(C_je) = 10 pF, and C_bc(C_jc) = 1 pF.

    1. Complete the following MATLAB function ‘BJT_cascode_DC_analysis()‘, which performs the DC analysis of the BJT cascade amplifier to determine the node voltages and base/collector currents at the operating point.

    

    2. Complete the above MATLAB function ‘BJT_cascode_xfer_ftn()’, which solves a set of four or five node equations for the high‐frequency small‐signal equivalent (Figure P3.15(d)) (depending on r_be=0 or not) to find the transfer function G(s) = V_o(s)/V_s(s) of the cascade amplifier.
    3. Complete the above MATLAB script “elec03p15.m” and run it to perform the DC analysis (using ‘BJT_cascode_DC_analysis()’), then based on the DC analysis result, use ‘BJT_cascode_xfer_ftn()’ to find the transfer function G(s), and plot the frequency response magnitude 20log₁₀|G(jω)| [dB] of the cascade amplifier versus f = 1∼100 MHz as shown in Figure P3.15(c).
    4. Perform the PSpice simulation (with AC Sweep analysis) to get the frequency response magnitude curve as shown in Figure P3.15(b). Is the Bias Point analysis result (obtained as a by‐product) close to the DC analysis result obtained by using ‘BJT_cascode_DC_analysis()’ in (c)?
16. 3.16 Time Response of a BJT Inverter with another Inverter as a Load

    Consider the BJT inverter in Figure P3.16(a) where V_CC = 12 V, R_B = 1 kΩ, R_C = 5 kΩ, R_C1 = 5 kΩ, and the BJT parameters are

    • β_F = 100, β_R = 1, I_s = 10⁻¹⁴ A, r_b = 0 Ω, V_A = ∞V, C_be1(C_je) = 10 pF, and C_bc1(C_jc) = 1 pF or 10 pF for Q₁,
    • and β_F = 100, β_R = 1, I_s = 10⁻¹⁴ A, r_b = 0 Ω, V_A = ∞V, C_be2(C_je) = 10 pF, and C_bc2(C_jc) = 1 pF for Q₂.

    Figure P3.16(b1) and (b2) shows the input/output voltage waveforms obtained from PSpice simulations, each with C_bc1=1 pF and 10 pF for Q₁, respectively. Referring to Section 3.6 and Figure P3.16(b1‐b2), answer the following questions:

    

    1. During the rising period, why does v_o1 reach just 0.7 V while v_o2 reaches V_CC = 5 V?
    2. The output voltage v_o2(t) of the second inverter shows a small negative spike in the beginning of its rising period in Figure P3.16(b1), but not in Figure P3.16(b2). Explain how such a difference is made by the difference in C_bc1 = 1 pF or 10 pF.
    3. Explain how a larger value of C_bc1 makes a longer time constant of v_o1 during its rising period.