1. (Q) What advantage does the current mirror of Figure 4.14(b) get from the additional FET M₃ over that of Figure 4.14(a)?
2. (A) An advantage is a considerable flexibility in the design of current source since K_p3/K_p1 can be fixed at the will of designer by adjusting the width‐to‐length ratios (W_n/L_n) of FETs.

The following MATLAB script “elec04f14.m” can be run to get the plot of the output currents i_Oa, i_Ob, and i_Oc versus V2 = 0 ~ 40 V for the three current mirrors shown in Figure 4.14(a‐c), as depicted in Figure 4.14(d).

4.1.5.1 NMOS Inverter Using an Enhancement NMOS as a Load

Figure 4.17(a) shows an e‐NMOS inverter, that is an NMOS inverter using a diode‐connected enhancement NMOS M₂ (with its gate‐drain short‐circuited) as a load resistor where v_GD2 = 0 < V_t2 so that M₂ is always in saturation with the drain current (common to the two NMOSs):

(4.1.45)

Note that we can write a KVL equation in i_D (for path V_DD‐DS2‐DS1) or a KCL equation in v_DS2 (at node S2‐D1) as

(4.1.46a)

(4.1.46b)

where the LHS of each equation corresponds to the (nonlinear) load curve (of M₂ with V_t2 = 1 [V]), which is plotted as the red line together with the i_D‐v_DS1 characteristic curves of M₁ with V_t1 = 1 [V] in Figure 4.17(b).

To get its transfer characteristic, suppose that the input voltage v_i increases from 0 to V_DD. While v_i = v_GS1 ≤ V_t1, M₁ is cut off with i_D = 0 so that v_o = V_DD ‐ v_GS2 = V_DD‐V_t2 since v_GS2 stays at V_t2 as long as i_D = 0, as described by point A in the VTC shown in Figure 4.17(c). As v_i = v_GS > V_t1, M₁ enters the saturation region where the drain current can be expressed as

(4.1.47)

and the output voltage v_o can be determined in terms of v_i by equating this with Eq. (4.1.45) for i_D2:

(4.1.48)

This linear saturation mode (with slope −K_pr) continues till v_o becomes low enough to make v_GD1 = v_i − v_o ≥ V_t1 so that M₁ knocks on the door to the triode region, as described by point T:

(4.1.49)

(4.1.50a,b)

If v_i increases over V_IT, M₁ enters the triode region where the drain current can be expressed as

(4.1.51)

and the output voltage v_o can be determined in terms of v_i by equating Eqs. (4.1.45) and (4.1.51):

(4.1.52)

(4.1.53)

Based on these two input‐output relationships (each for the saturation/triode region), we can plot the VTC as depicted in Figure 4.17(c). The VTC can be regarded as having been obtained by taking the values of (v_GS1, v_DS1) at the operating points, i.e. the intersection points of the load curve of M₂ with the drain characteristic curves of M₁ for each value of v_i = v_GS1. Figure 4.17(d) shows the VTC obtained from the PSpice simulation, which is quite similar to that (Figure 4.17(c)) obtained from the theoretical analysis.

The switching threshold voltage V_M, also called the midpoint voltage, can be found by substituting v_i = V_M and v_i = V_M into the input–output relationship Eq. (4.1.48) (for the saturation region) and solving it for V_M as

(4.1.54)

How about V_IL (the maximum input voltage that can be interpreted as “0”) and the corresponding output voltage V_OH (the minimum output voltage that can be interpreted as “1”)? Unlike the case of the NMOS inverter with a resistive load, it can't be determined as a point of slope ‐1 because the slope of the VTC abruptly changes from zero to ‐K_pr. Instead, we determine (V_IL, V_OH) at the turn‐on point A in Figure 4.17(c):

(4.1.55a,b)

V_IH (the minimum input voltage that can be interpreted as “1”) (at point B in Figure 4.17(c)) and the corresponding output voltage V_OL (the maximum output voltage that can be interpreted as “0”) can be determined by setting the derivative of dv_i/dv_o (rather than dv_o/dv_i for a technical reason) to ‐1:

(4.1.56b)

The processes of using these formulas to find the parameters and plotting the VTC have been cast into the following MATLAB function ‘NMOS2e_inverter()’. To analyze the NMOS inverter of Figure 4.17(a), all you need to do is to run the following MATLAB statements:

>>VDD=6; Vt1=1; Vt2=1; Kp1=1e-3; Kp2=0.1e-3;
 Kp12=[Kp1 Kp2]; Vt12=[Vt1 Vt2]; NMOS2e_inverter(Kp12,Vt12,VDD);

This will yield the following analysis result and the VTC as depicted in Figure 4.17(c), which conforms with that (in Figure 4.17(d)) obtained from PSpice simulation:

 VIL= 1.00, VIH= 2.39, VOL= 0.90, VOH= 5.00, VM= 1.96, VIT= 2.20, VOT= 1.20
 Noise Margin: NML= 0.10 and NM= 2.61, Average power = 3.330e+00[mW]

4.1.5.2 NMOS Inverter Using a Depletion NMOS as a Load

Figure 4.18(a) shows a d‐NMOS inverter, that is an NMOS inverter using a depletion NMOS M₂ (with its gate‐source short‐circuited) as a load resistor where v_GS2= 0 > V_t2 so that i_D2= i_D1= i_D is determined by v_DS2=V_DD‐ v_DS1 = V_DD‐v_o as

(4.1.57)

The (nonlinear) load curve (of M₂ with V_t2= −1 [V]) is plotted as the pink line together with the i_D‐v_DS1 characteristic curves of M₁ with V_t1 = 1 [V] in (b). Note that the load curve and the i_D‐v_DS1 characteristic curve of M₁ for v_GS1 = V_t1 ‐ V_t2 = 2 are symmetric about v_DS1 = V_DD/2 because they can be switched to each other by substituting v_DS2 = V_DD ‐ v_DS1.

To get its transfer characteristic, suppose that the input voltage v_i increases from 0 to V_DD. While v_i = v_GS1 ≤ V_t1, M₁ is cut off with i_D = 0 while M₂ is turned on, but with v_DS2 = 0 (by Eq. (4.1.57b)) so that v_o = V_DD ‐ v_DS2 = V_DD. As v_i = v_GS1 > V_t1, M₂/M₁ enter the triode/saturation region where the drain current can be expressed as

(4.1.58)

and the output voltage v_o can be determined in terms of v_i by equating this with Eq. (4.1.57b):

(4.1.59a)

(4.1.59b)

From Figure 4.18(b), we can see that during this mode, the operating point moves upward from point S (via point A) along the semiparabolic load curve. When will this mode stop and M₂ enter the saturation mode? It is when v_GD2 = v_SD2 = v_DS1‐V_DD = V_t2 so that v_o = v_DS1 = V_DD + V_t2 = V_OT2. At this point T₂, we have

(4.1.60)

When will this mode stop and M₁ enter the triode mode? It is when v_GD1 = v_GS1 ‐ v_DS1 = v_i ‐ v_o = V_t1. The output voltage v_o at this point T can be determined by substituting v_i = v_o + V_t1 into Eq. (4.1.51) as

(4.1.61)

Noting that the input voltage v_i at this point is the same as V_IT (Eq. (4.1.60)) despite the different values of v_o, we can see that when v_i = V_IT, v_o may change abruptly between V_OT and V_OT2 = V_DD + V_t2. The midpoint is determined as the constant value of v_i along this SAT‐SAT segment:

(4.1.62)

As v_i = v_GS1 increases over V_IT, M₁ enters the triode region while M₂ continues to be in saturation so that their drain currents can be expressed as

and the output voltage v_o can be determined in terms of v_i by equating these two equations:

(4.1.63a)

(4.1.63b)

Based on the two input‐output relationships (Eqs. (4.1.59) and (4.1.63)), we can plot the VTC as depicted in Figure 4.18(c). The process of using these formulas to plot the VTC has been cast into the above MATLAB function ‘NMOS2d_inverter()’, which uses the MATLAB function ‘find_pars_ of_inverter()’ (Section 3.1.10) to find the values of the inverter parameters such as V_IL/V_OH, V_IH/V_OL (at the two points with the slope of the VTC equal to ‐1), and V_M (at the midpoint).

To analyze the NMOS inverter of Figure 4.18(a), all you need to do is to run the following MATLAB statements:

>>VDD=5; Vt1=1; Vt2=-1; Kp1=1e-3; Kp2=1e-3;
 Kp12=[Kp1 Kp2]; Vt12=[Vt1 Vt2]; NMOS2d_inverter(Kp12,Vt12,VDD);

This will yield the following analysis result and the VTC as depicted in Figure 4.18(c), which conforms with that (in Figure 4.18(d)) obtained from PSpice simulation:

 VIL= 1.708, VIH= 2.155, VOL= 0.577, VOH= 4.706, VM= 2.000
 NML= 1.131, NMH= 2.551, VL= 0.127, Pavg=  1.250[mW]

Comparing Figures 4.17(c) and 4.18(c), note that the VTC of a d‐NMOS inverter has a steeper transition region and, accordingly, higher noise margins than an e‐NMOS inverter.

4.1.5.3 CMOS Inverter

Figure 4.19(a) shows a CMOS (Complementary MOSFET) inverter using NMOS and PMOS fabricated on the same chip where both gates/drains are tied to the input/output, respectively, and the sources of Mp(PMOS)/Mn(NMOS) are connected to VDD/GND, respectively. Figure 4.19(b) shows the (blue‐lined) i_D‐v_DSn characteristic curves of Mn depending on v_GSn and the (red‐lined) i_D – (v_SDp = V_DD‐v_DSn) characteristic curves of Mp depending on v_SGp = V_DD ‐ v_i. A rough VTC of the inverter can be plotted by connecting the operating points (v_SGn = v_i, v_DSn = v_o) {S, A, T₂, T₁, …}, i.e. the intersection points of the characteristic curve of Mn (for v_GSn = 0~1, 1.5, 2, 2.5, 3, 3.5, and 4 ~ 5 V) with that of Mp (for v_SGp = V_DD‐v_i = 5~4, 3.5, 3, 2.5, 2, 1.5, and 1 ~ 0 V), as illustrated in Figure 4.19(b) and (c). Figure 4.19(d) shows the VTC obtained from the PSpice simulation.

Noting from Figure 4.19(b) and (c) that the operating point moves around the five regions I, II, III, IV, and V as the input voltage v_i (applied to the common gate) varies from zero to V_DD, let us analyze the inverter to find out the analytical expression of the VTC together with the transition points from a region to another region where the conduction parameters and threshold (turn‐on) voltages of the PMOS/NMOS are K_pP/K_pN and V_tP/V_tN, respectively. To this aim, we start from computing the value V_m of the input voltage v_i (belonging to region III) at which both Mp and Mn operate in the saturation region by equating the drain currents of Mp and Mn described by Eq. (4.1.13b) (with λ = 0 for simplicity):

(4.1.64)

(4.1.65)

This will be used as the boundary values of v_i between regions II and III or III and IV (see Figure 4.19(c)).

<Region II>

When V_tN < v_i ≤ V_m, Mn/Mp are assumed to be in the saturation/ohmic regions, respectively (see Figure 4.19(b)) and the operating point is computed by equating the drain currents of Mp and Mn that are described by Eqs. (4.1.13b) (with λ = 0 for simplicity) and (4.1.13a), respectively:

(4.1.66)

If the (larger) root of this quadratic equation satisfies v_o > v_i ‐ V_tP, the assumption is right. Otherwise, i.e. if

(4.1.67)

then Mp enters the saturation region and this is region III where both Mp and Mn operate in the saturation mode. The boundary between regions II and III is denoted by the pink line corresponding to v_o = v_i ‐V_tP in Figure 4.19(c).

<Region III>

The inverter stays in Region III (with Mp and Mn saturated) as long as the saturation condition of Mn is satisfied, i.e. if

(4.1.68)

<Region IV>

If v_i increases further enough to break the above condition, i.e. v_o < v_i ‐V_tN, Mn enters the ohmic region (see Figure 4.19(b)) and the operating point is computed by equating the drain currents of Mp (in the saturation region) and Mn (in the ohmic region) that are described by Eqs. (4.1.13b) (with λ = 0 for simplicity) and (4.1.13a), respectively:

(4.1.69)

The (smaller) root of this quadratic equation will be v_o as long as v_i≤ v_DD+V_tP.

<Region V>

While Mn is still in the ohmic region, Mp will be OFF if

(4.1.70)

Then almost the whole V_DD applies to Mp (with much larger resistance) so that v_o ≈ 0.

The process of finding the output voltage of the CMOS inverter to the whole range of the input has been cast into the above MATLAB function ‘CMOS_inverter()’. We have run the above MATLAB script “elec04f19.m” to get not only the following values of the inverter parameters

 VIL = 2.1250, VIH = 2.8750, VOL = 0.3750, VOH = 4.6250,
 VIT2 = 2.5000, VOT2 = 3.5000, Vm = 2.5000, VIT1 = 2.5000, VOT1 = 1.5000,
 NML = 1.7500, NMH = 1.7500, PDavg = 0.0028

but also the VTC and the drain current of the inverter as depicted in Figures 4.19(c) and 4.20(a), respectively. As can be seen from the VTC in Figure 4.19(c), the lowest/highest output voltage levels are 0/V_DD so that the CMOS inverter has the maximum output swing. This, together with the symmetry of the VTC, is the reason why a CMOS inverter can have wide noise margins.

Figure 4.20(b) shows the drain current of the inverter obtained from the PSpice simulation, which is quite similar to Figure 4.20(a). What is implied by the current curve(s) in Figure 4.20? The current (drawn from the supply voltage source V_DD) is zero when the CMOS inverter is in its output‐high/low state so that the CMOS gate can power down in its static condition, which is one of the major advantages of CMOS configuration.

One more thing to note before closing this section is that a formula to determine the geometry ratio K from the given values of V_DD, V_m (the boundary value of the input voltage between regions II and III or regions III and IV), V_tP (the threshold voltage of PMOS), and V_tN (the threshold voltage of NMOS) can be derived from Eq. (4.1.65) as

(4.1.71)

4.2.4.1 CS Amplifier with an Enhancement FET Load

Figure 4.30(a) shows a CS amplifier with an enhancement NMOS driver M_D and an enhancement NMOS load M_L, which is diode connected with its gate and drain short‐circuited so that it can act like a nonlinear resistor. The drain (output) characteristic curves of M_D (for several values of v_GS) are plotted as solid lines while the i_D,L−v_DS,L and i_D,L−v_DS,D=V_DD−v_DS,L relationships of M_L (with v_GS,L = v_DS,L) are plotted as the lines of square/circle symbols, respectively, in Figure 4.30(b) where the conduction parameter K_p, threshold voltage V_t, and CLM parameter λ of M_D and M_L are

(4.2.19)

From the locus of dynamic operating points obtained from the intersections of the (pink solid) load line and the characteristic curves of M_D (for several values of v_i = v_GS,D), the graphs of i_D(t) = i_D,L(t) = i_D,D(t) and v_o(t) = v_DS,D(t) for the sinusoidal input v_i(t) = V_sm sin (2000πt) (with V_sm = 0.5 or 1) applied to the G‐S terminals of M_D have been plotted as the green and red lines in Figure 4.30(b).

Note that the intersection of the load line of M_L and the characteristic curve of M_D for a certain value of the input v_GS,D = v_i (>V_t,D) can analytically be obtained as follows:

• (Step 1) Assuming that both NMOSs are in the saturation region, we find the smaller one of the two roots of the following quadratic equation since the larger one (>V_DD) must be invalid:
  (4.2.20)

• (Step 2) If this (tentative) solution is not in the saturation region of M_D, i.e. v_DS,D < v_GS,D‐V_t,D so that v_GD,D = v_GS,D‐v_DS,D >V_t,D, we assume that M_D is in the ohmic region and find the smaller one of the two roots of the following quadratic equation:
  (4.2.21)

This process of analyzing the CS amplifier with an enhanced FET load has been cast into the above MATLAB function ‘FET_CS_NMOSe()’. We can run the following MATLAB script “do_FET_CS_NMOSe.m” to plot the output v_o(t) to the input v_i(t) = 0.5 sin (2000πt) for t = 0 ~ 1 ms like the PSpice simulation result shown in Figure 4.30(c).

CS Amplifier with a Depletion FET Load

Figure 4.31(a) shows a CS amplifier with an enhancement NMOS driver M_D and a depletion NMOS load M_L, which is diode connected with its gate and source short‐circuited so that it can act like a current‐limited nonlinear resistor. The drain (output) characteristic curves of M_D (for several values of v_GS) are plotted as blue lines while the i_D,L – v_DS,L and i_D,L – v_DS,D = V_DD – v_DS,L relationships of M_L (with v_GS,L = 0) are plotted as the lines of square/circle symbols, respectively, in Figure 4.31(b) where the conduction parameter K_p, threshold voltage V_t, and CLM parameter λ of M_D and M_L are

(4.2.22)

From the locus of dynamic operating points obtained from the intersections of the (pink solid) load line and the characteristic curves of M_D (for several values of v_i = v_GS), the graphs of i_D(t) = i_D,L(t) = i_D,D(t) and v_o(t) = v_DS,D(t) for the sinusoidal input v_i(t) = V_sm sin (2000πt) (with V_sm = 0.5 or 1) applied to the G‐S terminals of M_D can be plotted as the green and red lines, respectively, in Figure 4.31(b).

Note that the intersection of the load line of M_L and the characteristic curve of M_D for a certain value of the input v_GS,D = v_i (>V_t,D) can analytically be found as follows:

• (Step 1) Assuming that both NMOSs are in the saturation region, find the root of the following first‐degree polynomial equation:
  (4.2.23)
• (Step 2) If this tentative solution is in the ohmic region of M_D, i.e. v_o = v_DS,D < v_GS,D − V_t,D = v_i − V_t,D, the following equation should be solved on the assumption that M_D is in the ohmic region:
  (4.2.24)
  where the smaller one of the two roots should be taken as v_o,Q = V_DS,D because the larger one must be invalid.
• (Step 3) If the tentative solution is in the ohmic region of M_L, i.e. v_o = v_DS,D > V_DD + V_t,L so that v_GD,L = ‐v_DS,L = ‐(V_DD − v_DS,D) > V_t,L, the following equation should be solved on the assumption that M_L is in the ohmic region:
  (4.2.25)
  where the larger one of the two roots should be taken as the value of v_o because the smaller one must be invalid.

This process of analyzing the CS amplifier with a depletion FET load has been cast into the above MATLAB function ‘FET_CS_NMOSd()’.

An alternative to analyze the circuit of Figure 4.31(a) is to solve the KCL at node 1:

(4.2.26)

where v_GS,D = V_GSQ,D + v_i with V_GSQ,D = V_DDR₂/(R₁ + R₂) and i_Dk(v_GSk, v_DSk) is defined as Eq. (4.1.83). This algorithm can be implemented by replacing the for loop of the above MATLAB function ‘FET_CS_NMOSd()’ by the following block of statements:

Isn't it interesting that this simple algorithm of solving just one (seemingly nonlinear) equation can replace the above individual quadratic equation approach?

We can run the following MATLAB script “do_FET_CS_NMOSd.m” to plot the output v_o(t) to the input v_i(t) = 0.5 sin (2000πt) for t = 0 ~ 1 ms like the PSpice simulation result shown in Figure 4.31(c).

Here, I_Nt and Y_B are the values of Norton current source and admittance looking back into the source part from terminals g to 0. This equation can be rearranged into a solvable form with all the unknown/known terms on the LHS/RHS as

(4.200)

and solved for V₁, V₂, and V₃. Then, the transfer function and frequency response can be found:

(4.4.4)

This process to find the transfer function and frequency response has been cast into the following MATLAB function ‘FET_CS_xfer_ftn()’.

Note the following about the internal capacitances of an FET, i.e. the gate‐to‐source capacitance C_gs, the gate‐to‐drain capacitance (sometimes called the overlap capacitance) C_gd, and the drain‐to‐source capacitance C_ds ([S-1]):

• C_ds can usually be ignored since C_ds≪C_gs. C_gs and C_gd can be modeled as voltage‐dependent capacitances with values determined by
  (4.4.5)

  where C_gs0/C_gd0[F]: zero‐bias gate‐source/gate‐drain junction capacitances, respectively, V_GS,Q/V_GD,Q[V]: quiescent gate‐source/gate‐drain voltages, respectively, m(Mj): gate p‐n grading coefficient (SPICE default = 0.5), and Vb(Pb): gate junction (barrier) potential, typically 0.6 V (SPICE default = 1 V).

• The zero bias capacitances have dimensions of [F/m]/[F] for MOSFET/JFET, respectively.

Referring to Figure 4.43, four break (pole or corner) frequencies determining roughly the frequency response magnitude can be determined as [R-2]

(4.4.6a,b)

(4.4.6c,d)

Note the following about these four break frequencies:

• ω_C1, related with the coupling capacitor C_s, is obtained as the reciprocal of the product of C_s and the equivalent resistance as seen from C_s (Figure 4.43(a)).

  

• ω_C2, related with the output capacitor C_L, is obtained as the reciprocal of the product of C_L and the equivalent resistance as seen from C_L (Figure 4.43(c)).
• ω_C3, related with the internal capacitors C_gs|C_gd, is obtained as the reciprocal of the product of (C_gs + C_m) and the equivalent resistance as seen from C_gs (Figure 4.43(b)).
• ω_C4, related with the internal capacitors C_gd|C_LL, is obtained as the reciprocal of the product of (C_n + C_LL) and the equivalent resistance as seen from C_LL (Figure 4.43(d)).
• The passband of the CS amplifier will be approximately lower‐/upper‐bounded by the second/third highest break frequencies where not only the values but also the order of the frequencies varies with the values of the related capacitances and resistances.

Note also that R_i/R_o are the input/output resistances of the CS amplifier, respectively, and C_m/C_n are the Miller equivalent capacitances for capacitor C_gd seen from the input/output side, respectively (Eq. (1.4.2):

(4.4.7)

The following MATLAB function ‘break_freqs_of_CS()’ uses Eqs. (4.4.6a,b,c,d) to find the four break frequencies.

Solving this set of equations, we can find the transfer function and frequency response:

(4.4.10)

This process to find the transfer function and frequency response has been cast into the above MATLAB function ‘FET_CD_xfer_ftn()’.

There are four break (pole or corner) frequencies determining roughly the frequency response magnitude:

(4.4.11a,b)

(4.4.11c,d)

where R_i/R_o are the input/output resistances of the CD amplifier, respectively, and C_m/C_n are the Miller equivalent capacitances for capacitor C_be seen from the input/output side, respectively (Eq. (1.4.2)):

(4.4.12)

Note that Eq. (4.4.11) is just like Eq. (4.4.6) with C_gd and C_gs switched.

The following MATLAB function ‘break_freqs_of_CD()’ uses Eqs. (4.4.11a,b,c,d) to find the four break frequencies:

1. (Q) How about if R_G = 0 or C_G is so large that R_G can be regarded as AC‐shorted?

Solving this set of equations, we can find the transfer function and frequency response:

(4.4.15)

This process to find the transfer function and frequency response has been cast into the above MATLAB function ‘FET_CG_xfer_ftn()’.

There are five break (pole or corner) frequencies determining roughly the frequency response magnitude:

(4.4.16a,b)

(4.4.16c)

(4.4.16d,e)

where R_i/R_o are the input/output resistances of the CG amplifier, respectively.

The following MATLAB function ‘break_freqs_of_CG()’ uses Eqs. (4.4.16a,b,c,d,e) to find the five break frequencies:

Problems

1. 4.1 Analysis of JFET Circuits
   1. Consider the JFET circuit in Figure P4.1(a) where the device parameters of the n‐channel JFET (NJF) J are I_DSS = 5 mA/V², V_t = −5 V, and λ = 0. Find I_D, V_G, V_D, and V_S. Also tell which one of the saturation, triode, and cutoff regions the NJF J operates in.

      (Hint)
      >>VDD=12; VG=0; RG=680e3; RD=2e3; RS=1e3;
      
       Vt=-5; IDSS=5e-3; Kp=2*IDSS/Vt^2;
       BETA=Kp/2 % SPICE parameter FET_DC_analysis(VDD,VG,RD,RS,Kp,Vt);
      

   2. Consider the JFET circuit in Figure P4.1(b) where the device parameters of the NJF J₂ are I_DSS = 8 mA/V², V_t = −4 V, and λ = 0. Find I_D, V_G, V_D, and V_S. Also tell which one of the saturation, triode, and cutoff regions the NJF J₂ operates in.

      (Hint)
      >>VDD=15; R1=1e6; R2=5e5; RD=3e3; RS=1500;
       Vt=-4; IDSS=8e-3; Kp=2*IDSS/Vt^2; BETA=Kp/2
       FET_DC_analysis(VDD,R1,R2,RD,RS,Kp,Vt);
      

      Noting that it depends on

      (P4.1.1)

      

      whether the JFET operates in the saturation or triode region, answer the following questions:

      1. (b1) Would you decrease or increase R₂ to push J₂ into the saturation region? With R₂ = 200 kΩ and the other parameter values unchanged, tell which region J₂ operates in.
      2. (b2) Would you increase or decrease R_D to push J₂ into the triode region? With R_D = 10 kΩ and the other parameter values as in (b1), tell which region J₂ operates in.
      3. (b3) Would you increase or decrease R_S to push J₂ into the saturation region? With R_S = 10 kΩ and the other parameter values as in (b2), tell which region J₂ operates in.
   3. Noting that the value of BETA, which is one of the SPICE model parameters for a JFET, is determined from I_DSS and V_t as
      (P4.1.2)

      perform the PSpice simulation (with Bias Point analysis type) for the two JFET circuits to check the validity of the circuit analyses done in (a) and (b).

2. 4.2 Design of a JFET Biasing Circuit

   Consider the JFET circuit in Figure P4.2 where the device parameters of the NJF J are I_DSS = 12.3 mA/V², V_t = −3.5 V, and λ = 0. Determine the values of R_D and R_S so that I_D = 1 mA and V_DS = 3 V. Check the validity of your design result by using the MATLAB function ‘FET_DC_analysis()’ and/or PSpice.

   

   

3. 4.3 Analysis of NMOS Circuits
   1. Consider the NMOS circuit in Figure P4.3(a) where the device parameters of the enhancement NMOS (e‐NMOS) M₁ are K_p = 0.32 mA/V², V_t = 1.2 V, and λ = 0. Find I_D, V_G, V_D, and V_S. Also tell which one of the saturation, triode, and cutoff regions the NMOS M₁ operates in.

      (Hint)
      >>VDD=5; VSS=-5; R1=330e3; R2=180e3; RD=2e4; RS=3900;
       Kp=32e-5; Vt=1.2; lambda=0;
       [VGQ,VSQ,VDQ,VGSQ,VDSQ,IDQ,mode]= ...
       FET_DC_analysis(VDD-VSS,R1,R2,RD,RS,Kp,Vt,lambda);
       fprintf('VG=%6.2fV, VD=%6.2fV, VS=%6.2fV, ID=%8.3fmA
      ',...
          VGQ+VSS,VDQ+VSS,VSQ+VSS,IDQ*1e3);
      

   2. Consider the NMOS circuit in Figure P4.3(b) where the device parameters of M₂ are K_p = 0.2 mA/V², V_t = 1 V, and λ = 0. Find I_D, V_G, V_D, and V_S. Also tell which region M₂ operates in.
   3. Consider the NMOS circuit in Figure P4.3(c) where the device parameters of the e‐NMOS M₃ are K_p = 0.5 mA/V², V_t = 1.2 V, and λ = 0. Find I_D, V_G, V_D, and V_S. Also tell which region the NMOS M₃ operates in. Plot the load line for i_D = (V_G − V_SS − v_GS)/R_S on the i_D‐v_GS characteristic curve for i_D = K_p(v_GS − V_t)²/2 and locate the operating point (V_GS,Q, I_D,Q). Also plot the load line for i_D = (V_DD − V_SS − v_DS)/(R_D + R_S) on the i_D‐v_DS characteristic curve (with v_GS = V_GS,Q) and locate the operating point. To those ends, complete and run the following script:
   1. Perform the PSpice simulation (with Bias Point analysis type) for the three NMOS circuits to check the validity of the circuit analyses done in (a), (b), and (c).
4. 4.4 Analysis PMOS Circuits
   1. Consider the PMOS circuit in Figure P4.4(a1) where the device parameters of the enhancement PMOS (e‐PMOS) M₁ are K_p = 0.2 mA/V², V_t = −0.4 V, and λ = 0. Find I_D, V_G, V_D, and V_S. Also tell which one of the saturation, triode, and cutoff regions the NMOS M₁ operates in.

      

      (Hint)
      >>VDD=5; R1=160e3; R2=200e3; RS=8.2e3; RD=12e3;
       Kp=2e-4; Vt=-0.4; lambda=0; % Device parameters
       FET_PMOS_DC_analysis(VDD,R1,R2,RS,RD,Kp,Vt,lambda);
      

   2. Consider the PMOS circuit in Figure P4.4(a2) where the device parameters of the e‐PMOS M₁ are K_p = 0.2 mA/V², V_t = −0.4 V, and λ = 0.01. Find I_D, V_G, V_D, and V_S. Also tell which region the PMOS M₁ operates in.
   3. Consider the PMOS circuit in Figure P4.4(b) where the device parameters of the e‐PMOS M₂ are K_p = 0.4 mA/V², V_t = −0.8 V, and λ = 0.01. Find I_D, V_G, V_D, and V_S. Also tell which region the PMOS M₂ operates in.
   4. Perform the PSpice simulation (with Bias Point analysis type) for the three PMOS circuits to check the validity of the circuit analyses done in (a), (b), and (c).
5. 4.5 Design of a MOSFET biasing Circuit

   Consider the MOSFET circuit in Figure P4.5 where the device parameters of the NMOS M₁ are K_p = 1 mA/V², V_t = 1.2 V, and λ = 0. Determine the values of R_D, R_S, R₁, and R₂ so that I_D = 0.4 mA, V_D = 6 V, V_DS = 3.1 V, and R_i = 100 kΩ. Check the validity of your design result by using the MATLAB function ‘FET_DC_analysis()’ and/or PSpice.

   

6. 4.6 Diode‐Connected MOSFETs Used as Nonlinear Resistors

   Consider the two NMOS circuits in Figure P4.6 where the device parameters of the enhancement NMOS (e‐NMOS) M₁ and the depletion NMOS (d‐NMOS) M₂ are K_p1 = 0.02 mA/V², V_t1 = 1 V, λ₁ = 0 and K_p2 = 0.02 mA/V², V_t2 = −3 V, λ₂ = 0, respectively.

   1. Perform the load line analysis of finding the operating points Q₁/Q₂ from the intersections between the i_Dk‐v_DSk characteristice curves of M₁/M₂ and the load line for i_Dk = (V_DD − v_DSk)/R_k where the load lines for M₁/M₂ are identical since R₁ = R₂. If helpful, complete and run the corresponding part of the following MATLAB script “elec04p06.m” to plot the related graphs and find the operating points for M₁/M₂.

      

   2. As a nonlinear approach, use the MATLAB function ‘fsolve()’ to solve the following KCL equations:
      (P4.6.1)
      (P4.6.2)

      where i_Dk(v_GSk,v_DSk) is defined as Eq. (4.1.83) and implemented by the MATLAB function ‘iD_NMOS_at_vDS_vGS()’ (see the end of Section 4.1.1), which is stored in a separate m‐file named “iD_NMOS_at_vDS_vGS.m.” If helpful, complete and run the corresponding part of the above MATLAB script “elec04p06.m” to find the operating points for M₁/M₂.

   3. Perform the PSpice simulation (with Bias Point analysis type) for the two MOSFET circuits to check the validity of the operating points found in (a) or (b). Also, perform the PSpice simulation (with DC Sweep analysis type) for the two MOSFETs (with R₁/R₂ short‐circuited for removal) to get the i_Dk‐v_DSk characteristice curves of M₁/M₂ (for V_DD = 0 : 0.01 : 8 V) and see if they conform with those obtained in (a) or plotted in Figure 4.13(c1).
7. 4.7 Cascode Current Mirror

   Consider the cascode current mirror circuit in Figure P4.7 where the four NMOSs have the device parameters K_p = 1 mA/V², V_t = 1 V, and λ = 2 mV⁻¹ in common.

   1. Noting that v_GS1 = v_DS1 = v₁ and v_GS3 = v_DS3 = v₃ − v₁, apply KCL at nodes 1, 2, and 3 to write the node equations:
      (P4.7.1a)
      (P4.7.1b)
      (P4.7.1c)

      where i_Dk(v_GSk,v_DSk) is defined as Eq. (4.1.83) and implemented by the MATLAB function ‘iD_NMOS_at_vDS_vGS()’ (see the end of Section 4.1.1). If a current source I is connected into node 3, how will Eq. (P4.7.1c) be changed?

      (P4.7.2)
   2. Noting that the small‐signal resistance of an e‐NMOS with G‐D connected is 1/g_m (Eq. (4.1.19), we can draw the small‐signal equivalent of the circuit as Figure P4.7(c). To find the output resistance R_o, we apply a test current source i_T into node D₄ and write the KCL equations at nodes D₄ and 2:
      (P4.7.3)

      

      We can solve this equation and find the output resistance:

      (P4.7.4)

      where no current flows in the left part with no source so that v₃ = v_d3 = v_g3 = v_g4 = 0 and v₁ = v_s3 = v_d1 = v_g1 = v_g2 = 0.

      (Q) In the small‐signal equivalent shown in Figure P4.7(c), why have M₁ and M₃ been modeled by just a resistor of 1/g_m (with no current source) unlike M₂ and M₄?

   3. Complete the above MATLAB function ‘FET4_current_mirror_cascode()’, which implements Eqs. (P4.7.1/2) and (P4.7.4) for analyzing a cascode current mirror (excited by a voltage source V1 or a reference current source I) and finding its output resistance. Use the MATLAB function to find the output current i_o versus V₂ = 0:0.01:40 and plot it. Also, find the output resistance R_o (when V₂ = 9 V) of the current mirror (shown in Figure P4.7(a)) two times, once when it is excited by a voltage source V1 of 9 V (with a resistance R of 1 kΩ) and once when it is excited by a current source of I = 2.5 mA.
   4. Perform the PSpice simulation of the circuit excited by a voltage source V1 of 9 V (with a resistance R of 1 kΩ) two times, once with DC Sweep analysis to get the plot of the output current i_o versus V₂ = 0:0.01:40 (sweep variable) as depicted in Figure P4.7(b1) and once with Transient analysis to get the plot of i_o versus t = 0 : 1 μs : 3 ms to the AC voltage source v_s (of amplitude 1 V and frequency 1 kHz) as depicted in Figure P4.7(b2). Is the first graph (Figure P4.7(b1)) similar to the plot of i_o versus V₂ obtained in (c)? From the second graph (Figure P4.7(b2)), find the (small‐signal) output resistance:
      (P4.7.5)

      Is it close to that obtained in (c)?

8. 4.8 CMOS Inverter

   Consider the CMOS inverter in Figure 4.19(a) where V_DD = 10 V and the NMOS/PMOS have the device parameters K_pN = 200 μA/V², V_tN = 2 V, K_pP = 80 μA/V², V_tP = −2 V, and λ = 0.

   1. To determine the point (V_IL,V_OH) with the slope of −1 in Region II (where Mn and Mp are in the saturation and ohmic regions, respectively), we write the KCL equation at the output node (Dp,Dn):
      (P4.8.1a)

      Differentiating both sides w.r.t. v_i and substituting dv_o/dv_i = −1 yields

      
      (P4.8.1b)

      Use the MATLAB function ‘fsolve()’ to solve this set of two equations and find (V_IL,V_OH) by running the following statements:

      >>VDD=10; KN=2e-4; KP=8e-5; VtN=2; VtP=-2; Kr2=KN/KP; Kr=sqrt(Kr2)
       Vm=(VDD+VtP+Kr*VtN)/(1+Kr); % Eq. (4.1.65)
       eq_VIL=...
       @(v)[(VDD-v(1)+VtP)*(VDD-v(2))-(VDD-v(2))^2/2-Kr2*(v(1)-VtN)^2/2;
       v(2)-(VDD+v(1)-VtP+Kr2*(v(1)-VtN))/2]; % Eq. (P4.8.1a,b)
       v=fsolve(eq_VIL,[Vm Vm]); VIL=v(1), VOH=v(2)
      

      Check if these values conform with those obtained by using Eq. (16.61) or (16.63) of [N-1] depending on K_pN/K_pP = 1 or not:

      (P4.8.2)

      and substituting v_i = V_IL into Eq. (P4.8.1b):

      >>VIL_Neamen=(VtN+(VDD+VtP-VtN)/(Kr2-1)*(2*sqrt(Kr2/(Kr2+3))-1))...
         *(Kr~=1) + (Kr==1)*(VtN+3/8*(VDD+VtP-VtN)); %Eq. (P4.8.2)
       VOH_Neamen=((1+Kr2)*VIL_Neamen+VDD-Kr2*VtN-VtP)/2; % Eq. (P4.8.1b)
       [VIL VIL_Neamen VOH VOH_Neamen] % Do they conform each other?
      

   2. To determine the point (V_IH,V_OL) with the slope of −1 in Region IV (where Mn and Mp are in the ohmic and saturation regions, respectively), we write the KCL equation at the output node (Dp,Dn):
      (P4.8.3a)

      Differentiating both sides w.r.t. v_i and substituting dv_o/dv_i = −1 yields

      (P4.8.3b)

      We can use the MATLAB function ‘fsolve()’ to solve this set of two equations and find (V_IH,V_OL) by running the following statements:

      >>eq_VIH=@(v)[Kr2*((v(1)-VtN)*v(2)-v(2)^2/2)-(VDD-v(1)+VtP)^2/2;
       v(2)+((VDD-v(1)+VtP)/Kr2-v(1)+VtN)/2]; % Eq. (P4.8.3a,b)
       v=fsolve(eq_VIH,[Vm Vm]); VIH=v(1), VOL=v(2)
      

      Check if these values conform with those obtained by using Eq. (16.66) or (16.69) of [N-1] depending on K_pN/K_pP = 1 or not:

      (P4.8.4)

      and substituting v_i = V_IH into Eq. (P4.8.3b):

      >>VIH_Neamen=(VtN+(VDD+VtP-VtN)/(Kr2-1)*(2*Kr2/sqrt(3*Kr2+1)-1))...
          *(Kr~=1) + (Kr==1)*(VtN+5/8*(VDD+VtP-VtN)); %Eq. (P4.8.4)
       VOL_Neamen=(VIH_Neamen*(1+1/Kr2)-VtN-(VDD+VtP)/Kr2)/2; %(P4.8.3b)
       [VIH VIH_Neamen VOL VOL_Neamen] % Do they conform each other?
      
   3. Complete and run the above MATLAB script “elec04p08.m” to plot the VTC together with the critical points as depicted in Figure P4.8(a) and the i_D‐v_DS characteristic curves (for Mn and Mp) as depicted in Figure P4.8(b).

      

   4. Find the points on the i_D‐v_DS characteristic curves (shown in Figure P4.8(b)) corresponding to each of the points A, T₁, M, T₂, and B on the VTC (shown in Figure P4.8(a)). Explain the meaning of each point.
9. 4.9 CMOS Differential (or Source‐Coupled) Pair Loaded by a Current Mirror

   Consider the CMOS differential pair loaded by a current mirror in Figure P4.9.1(a) where V_DD = 6 V, V_GG = 4 V, V_SS = 2 V, and the NMOS/PMOS have the device parameters K_pN = 2 mA/V², V_tN = 1 V, K_pP = 2 mA/V², V_tP = −1 V, and λ = 0.02 V⁻¹.

   1. Noting that v_GS1 = V_GG + v_d − v₃, v_DS1 = v₁ − v₃, v_GS2 = V_GG − v₃, v_DS2 = v₂ − v₃, and v_SG3 = v_SD3 = V_DD − v₁, v_SG4 = V_DD − v₁, and v_SD4 = V_DD − v₂, apply KCL at nodes 1, 2, and 3 to write the node equations:
      (P4.9.1a)
      (P4.9.1b)
      (P4.9.1c)

      where i_D1(v_GS1,v_DS1) = i_D2(v_GS2,v_DS2) = i_Dn(v_GS,v_DS) and i_D3(v_SG3,v_SD3) = i_D4(v_SG4,v_SD4) = i_Dp(v_SG,v_SD), defined as Eq. (4.1.83), can be implemented by the MATLAB function handles ‘iDn()’ and ‘iDp()’, respectively, in the MATLAB function ‘FET_differential_loaded_ by_current_mirror()’ below.

   2. Noting from Eqs. (3.78) and (3.79) of [C-1] that the output resistance (seen from node 2 and ground) and voltage gain of the differential pair are
      (P4.9.2)
      (P4.9.3)

      complete the above MATLAB function ‘FET_differential_loaded_by_current_mirror()’, which solves Eq. (P4.9.1) for v₁, v₂, and v₃, and also uses Eqs. (P4.9.2,3) to find the output resistance and voltage gain.

   3. Run the above MATLAB script “elec04p09.m,” which uses the MATLAB function ‘FET_ differential_loaded_by_current_mirror()’ two times, once with the fifth input argument vds = [−1.5 : 0.015 : 1.5] to plot i_D1/i_D2 versus v_d on a graph (as depicted in Figure P4.9.1(b1)) and v₁/v₂/v₃ versus v_d on another graph (as depicted in Figure P4.9.1(b2)), and once the fifth input argument vds = [v_d(t); t] (t = 0 : 1 μs : 3 ms) to plot v_d(t)/A_vv_d(t)/v_o(t) = v₂(t)‐mean(v₂(t)) versus t on another graph (as depicted in Figure P4.9.2(a1)) where v_d(t) = sin (2000πt) [mV]. You will see not only the related graphs but also the theoretical values of the output resistance and voltage gain.

      

   4. Constructing the schematic as depicted in Figure P4.9.1(a), perform the PSpice simulation of DC Sweep analysis with the sweep variable v_d = −1.5 : 0.01 : 1.5 [V] to get the plot of i_D1/i_D1 versus v_d on a graph (as depicted in Figure P4.9.1(c1)) and v₁/v₂/v₃ versus v_d on another graph (as depicted in Figure P4.9.1(c2)). Are they similar to the MATLAB analysis results shown in Figure P4.9.1(b1) and (b2)? Also perform the PSpice simulation of Transient analysis on the output voltage v₂ to the sinusoidal input differential voltage source v_dSIN = sin (2000πt) [mV] to measure the voltage gain A_v = v₂/v_dSIN. Is it close to the MATLAB analysis result obtained in (c)?
   5. Constructing the schematic (applying a test current source i_T = sin (2000πt)[μA] into the output node 2) as depicted in Figure P4.9.2(b), perform the PSpice simulation of Transient analysis on the voltage v_T across the test current source to measure the output resistance R_o = v_T/i_T. Is it close to the MATLAB analysis result obtained in (c)?

   

10. 4.10 Analysis of CS JFET Amplifier Circuit

    Consider the JFET circuit in Figure P4.10(a) where the JFET has the device parameters BETA = K_p/2 = 0.75 mA/V², VTO = V_t = −4 V, and λ = 0.008 V⁻¹.

    1. Complete the following MATLAB script “elec04p10.m” so that it can use the MATLAB function ‘FET_CS_analysis()’ to analyze the circuit three times, once with R_D = 2.7 kΩ and R_S = 2.7 kΩ (case A), once with R_D = 2.7 kΩ and R_S = 5 kΩ (case B), and once with R_D = 3.5 kΩ and R_S = 5 kΩ (case C). Then, run it to find the overall voltage gain G_v = v_o/v_i for the three cases. Noting that the three output voltage waveforms in Figure P4.10(c) have been obtained from PSpice simulations for the three cases with the small‐signal input v_i(t) = 0.1 sin (2000πt), identify which one of v_oa(t), v_ob(t), and v_oc(t) corresponds to the output voltage of three cases A, B, and C, respectively.

       

    2. Figure P4.10(b1) and (b2) shows the three Q‐points Q, Q₃, and Q₄ on the i_D‐v_GS and i_D‐v_DS characteristic curves for the three cases A, B, and C. Based on the slopes of the load lines crossing the Q‐points, rather than the DC analysis results obtained in (a), identify which one of Q, Q₃, and Q₄ corresponds to each of the three cases, respectively, and write the equations for the related load lines. From the locations of the three Q‐points, tell which case is the most susceptible to the output distortion for an increasing amplitude of the input voltage v_i(t).
    3. To see how easily the output v_o(t) gets distorted by raising the amplitude of the small‐signal input increasing v_i(t), two more Q‐points Q₁ and Q₂ with V_G = 20/3±0.2[V] have been drawn in Figure P4.10(b1) and (b2). Which one of them corresponds to each of V_G = 20/3±0.2[V], respectively?
    4. Considering the above three cases for which the small‐signal output voltage waveforms are shown in Figure P4.10(b), can you say that the maximum small‐signal output voltage that can be produced with no distortion is proportional to the voltage gain G_v?
    5. Are you going to increase or decrease the value of R_S1 to push the Q‐point rightward towards V_DD? Will the possibility of output distortion be decreased by moving the Q‐point rightward, i.e. increasing V_DS,Q? Generally speaking, if a Q‐point is too close to v_DS = V_DD, can the output easily get distorted from the lower or upper part?
    6. The output voltage waveforms shown in Figure P4.10(c) have larger/smaller magnitdes when they are negative/positive. To figure out what makes such a difference, find out the relationship among the slope of the i_D‐v_GS characteristic curve (Figure P4.10(b1)), the transconductance g_m, and the voltage gain G_v = v_o/v_i. Based on the relationship and considering the difference between the slopes of the i_D‐v_GS characteristic curve on the left/right part of a Q‐point, explain the difference between the magnitudes of v_o(t) during its positive/negative periods.
11. 4.11 Analysis of CS MOSFET Amplifier Circuit

    Consider the MOSFET circuit in Figure P4.11(a) where the NMOS has the device parameters K_p = 2 mA/V², V_t = 0.8 V, and λ = 0 V⁻¹.

    

    1. Complete the above MATLAB script “elec04p11.m” so that it can use the MATLAB function ‘FET_CS_analysis()’ to analyze the circuit three times, once with K_p = 1.6 mA/V² and without a bypass capacitor C_Sc in parallel with R_Sc (case A), once with K_p = 2 mA/V² and without C_Sc (case B), and once with K_p = 2 mA/V² and C_Sc in parallel with R_Sc (case C). Then, run it to find the voltage gain G_v = v_o/v_i for the three cases.
    2. Which case is the DC analysis result (obtained from the PSpice simulation) displayed on the schematic in Figure P4.11(a) for?
    3. Figure P4.11(b1) and (b2) shows the DC/AC load lines and Q‐points on the i_D‐v_GS characteristic curves for the cases B (without C_Sc) and C (with C_Sc). Write the equation for the DC load line and find the slopes of the AC load lines for the two cases. From the load lines and corresponding Q‐points swaying with the small‐signal input voltage v_i = Δv_G, tell which case will produce a larger small‐signal drain current i_d for the same amplitude of v_i, yielding a larger small‐signal output voltage like v_ob(t) in Figure P4.11(c).
    4. Find the small‐signal voltage gains for v_oa(t) and v_ob(t) in the PSpice simulation result (Figure P4.11(c)) and check if they are close to the MATLAB analysis result obtained in (a).
12. 4.12 Analysis of CD MOSFET Amplifier (Source Follower) Circuit

    Consider the MOSFET circuit in Figure P4.12(a) where the NMOS has the device parameters K_p = 1 mA/V², V_t = 1 V, and λ = 0.025 V⁻¹.

    1. Complete the following MATLAB script “elec04p12.m” so that it can use the MATLAB function ‘FET_CD_analysis()’ to analyze the circuit three times, once with R_D = 20 kΩ and R_S = 20 kΩ (case A), once with R_D = 35 kΩ and R_S = 20 kΩ (case B), and once with R_D = 20 kΩ and R_S = 35 kΩ (case C). Then, run it to find the voltage gain G_v = v_o/v_i and the input/output resistances for the three cases. Do the changes of the voltage gain and the input/output resistances due to the change of R_D or R_S conform with your expectation based on Eqs. (4.2.11a), (4.2.12), and (4.2.10)?

       

    2. Check if the PSpice simulation results on the voltage gain G_v = v_o/v_i (shown in Figure P4.12(b)) agree with the MATLAB analysis results.
13. 4.13 Analysis of CG MOSFET Amplifier

    Consider the MOSFET circuit in Figure P4.13(a1) or (a2) where the NMOS has the device parameters K_p = 1 mA/V², V_t = 1 V, and λ = 0.01 V⁻¹. Complete and run the following MATLAB script “elec04p13.m” to find the voltage gain G_v = v_o/v_i and the input/output resistances. Then see if they conform with the PSpice simulation results shown in Figure P4.13(b1) and (b2).

    
    

14. 4.14 Analysis of Multistage MOSFET Amplifier

    Consider the two‐stage MOSFET circuit in Figure P4.14(a) where the device parameters of the NMOSs M₁ and M₂ are K_p1 = 1 mA/V², V_t1 = 1.2 V, λ₁ = 0 V⁻¹, K_p2 = 0.4 mA/V², V_t2 = 1.2 V, and λ₂ = 0 V⁻¹. Noting that the input resistance R_i2 of stage 2 is infinite so that stage 1 (consisting of M₁, R₁₁, R₂₁, R_D1, and R_Sc) can be analyzed first, independently of stage 2 (consisting of M₂ and R_Sc2), complete and run the following MATLAB script “elec04p14.m” to find the overall voltage gain G_v = v_o/v_i and the overall input/output resistances. Then see if they conform with the PSpice simulation results shown in Figure P4.14(b).

    

15. 4.15 Analysis of a Two‐Stage MOSFET Amplifier

    Consider the MOSFET circuit in Figure P4.15(a) where the device parameters of the NMOSs M₁ and M₂ are K_p1 = 2 mA/V², V_t1 = 0.8 V, λ₁ = 0 V⁻¹, K_p2 = 1 mA/V², V_t2 = 1 V, and λ₂ = 0 V⁻¹. Noting that in general the analysis of a multistage amplifier needs performing a provisional backward analysis (starting from the last stage with the overall load resistance R_L) to determine the input resistances of each stage and then performing a forward analysis (starting from the first stage with the overall source resistance R_s) to determine the voltage gain and output resistances of each stage, complete the above MATLAB script “elec04p15.m” so that it can use the MATLAB function ‘FET_CD_ analysis()’ to analyze stage 2, ‘FET_CS_analysis()’ to analyze stage 1, and ‘FET_CD_ analysis()’ to analyze stage 2 again. Run it to find the overall voltage gain G_v = v_o/v_i and the overall input/output resistances R_I/R_O. Compare the overall voltage gain G_v with that obtained from the PSpice simulation (shown in Figure P4.15(b)) to see how close they are. Explain how the voltage gain has become larger than that of the single‐stage amplifier without the stage 2 (of CD configuration) whose voltage gain is less than 1 (Problem 4.12).

    

16. 4.16 Analysis of a Three‐Stage MOSFET Amplifier

    Consider the MOSFET circuit in Figure P4.16(a) where the device parameters of the NMOSs M₁/M₃ are K_p = 1 mA/V², V_t = 1 V, λ = 0.01 V⁻¹ in common, and those of the NPN‐BJT Q₂ are β_F = 100, β_R = 1, V_A = 100 V, and I_s = 10⁻¹⁶ V. Noting that in general the analysis of a multistage amplifier needs performing a provisional backward analysis (starting from the last stage with the overall load resistance R_L) to determine the input resistances of each stage and then performing a forward analysis (starting from the first stage with the overall source resistance R_s) to determine the voltage gain and output resistances of each stage, complete the following MATLAB script “elec04p16.m” so that it can use the MATLAB function ‘FET_CD_analysis()’ to analyze stage 3 (of CD configuration), ‘BJT_CE_analysis()’ to analyze stage 2 (of CE configuration), and ‘FET_CS_analysis()’

    

    to analyze stage 1 (of CS configuration), ‘BJT_CE_analysis()’ to analyze stage 2, and ‘FET_CD_analysis()’ to analyze stage 3. Run it to find the overall voltage gain G_v = v_o/v_i and the overall input/output resistances R_I/R_O. Compare the overall voltage gain G_v with that obtained from the PSpice simulation (shown in Figure P4.16(b1)) to see how close they are.

17. 4.17 Cascode MOSFET Amplifiers

    Consider the FET cascode amplifier circuits in Figure P4.17 where the NMOSs have the device parameters K_p = 1 mA/V², V_t = 1 V, and λ = 10⁻⁴ V⁻¹ in common.

    1. For the FET cascode amplifier A (in Figure P4.17(a)) with R₁ + R₂ + R₃ = 500 kΩ and R_S(R_Sc) = 8 kΩ, determine the values of the resistors R₁, R₂, R₃, and R_D so that I_D,Q = 0.5 mA and V_DS1,Q = V_DS2,Q = 2.5 V in the saturation mode.

       

    2. Complete the former part of the following MATLAB script “elec04p17.m” so that it can use the MATLAB function ‘FET_cascode()’ to analyze the circuit designed in (a). Run it to find the voltage gain G_v = v_o/v_i and the input/output resistances R_i/R_o.
    3. In the light of Eq. (E4.11.13) showing the voltage gain of a cascode amplifier, will a larger or smaller value of R_D be helpful in increasing the voltage gain G_v? Does it increase or decrease the output resistance R_o according to Eq. (E4.11.11)? To make sure that your answer is correct, complete and run the latter part of the MATLAB script “elec04p17.m” to find the voltage gain G_v = v_o/v_i and the input/output resistances R_i/R_o for the circuit with a larger R_D in Figure P4.17(b).
    4. Perform the PSpice simulation to find the voltage gain for the two cascode amplifier circuits and see if the results conform with those obtained from the MATLAB analysis.
18. 4.18 Design of CS JFET Amplifier Circuit

    Consider the (self‐biased) CS JFET amplifier circuit of Figure P4.18(a) where the conduction parameter, threshold voltage, and CLM parameter of the JFET are K_P= 20 mA/V², V_t= −6.25 V, and λ= 10⁻⁴V⁻¹, respectively.

    1. Considering the load resistance R_L = 50 kΩ, determine such resistor values that the voltage gain A_v,d = −10 and input resistance R_i,d = 100 kΩ can be achieved with the operating point located near Q₁ = (V_DS,Q,I_D,Q) = (6 V,10 mA). Analyze the designed circuit with source/load resistance R_s = 50 Ω/R_L = 50 kΩ to find the voltage gain A_v. Is it close to A_v,d = −10?

       (Hint) Complete and run the following MATLAB script “elec04p18.m”:

       

    2. Referring to Figure P4.18(a), perform the PSpice simulation of the designed CS JFET amplifier with Time Domain analysis to see the output voltage v_o(t) to an AC input v_s(t) = V_sm sin (2000πt) (with V_sm = 0.1 V) for t = 0–2 ms (with the maximum step size 1 us) as shown in Figure P4.18(b). Find the voltage gain and check if it agrees with the analysis result (obtained in (a)) and satisfies the design specification A_v,d = −10. Note that BETA, one of the PSpice model parameters for JFET, must be given as Kp/2.

       (Note) If the MATLAB function ‘FET_CS_design()’ turns out to work for this problem, it implies that the function can be used to design CS JFET amplifiers as well as CS MOSFET amplifiers.

19. 4.19 Design of CS MOSFET Amplifier Circuit

    Consider the CS MOSFET amplifier circuit of Figure P4.19(a) where the conduction parameter, threshold voltage, and CLM parameter of the MOSFET (IRF150) are K_P = K_PW/L = 20.53μ × 0.3/2μ = 3.08 A/V², V_t = 2.831 V, and λ = 2.2 mV⁻¹, respectively.

    1. Considering the load resistance R_L = 50 kΩ, determine such resistor values that the voltage gain A_v,d = −10 and input resistance R_i,d = 100 kΩ can be achieved with the operating point located near Q₁ = (V_DS,Q, I_D,Q) = (18/7 V, 1 mA). Analyze the designed circuit with source/load resistance R_s = 50 Ω/R_L = 50 kΩ to find the voltage gain A_v. Is it close to A_v,d = −10?

       (Hint) Complete and run the above MATLAB script “elec04p19.m”.

       

    2. Referring to Figure P4.19(a), perform the PSpice simulation of the designed CS FET amplifier with Time Domain analysis to see the output voltage v_o(t) to an AC input v_s(t) = V_sm sin (2000πt) (with V_sm = 0.01 V) for t = 0~2 ms (with the maximum step size 1 μs) as shown in Figure P4.19(b). Find the voltage gain and check if it agrees with the analysis result (obtained in (a)) and satisfies the design specification A_v,d = −10.
20. 4.20 Design of CS MOSFET Amplifier Circuit

    Consider the CS MOSFET amplifier circuit of Figure 4.36(a) where the conduction parameter, threshold voltage, and CLM parameter of the MOSFET (IRF150) are K_P = K_PW/L = 20.53μ × 0.3/2μ = 3.08 A/V², V_t = 2.831 V, and λ = 0.0075 mV⁻¹, respectively. Let us see how the location of (static) operating point depending on the design constants such as I_D,Q and V_DS,Q affects the distortion of the output voltage waveform (to an AC input v_s(t)=V_smsin(2000πt) with V_sm= 0.3 V) caused by the (dynamic) operating point infringing on the ohmic or cutoff region.

    1. In Section 4.3, a CS FET amplifier (Figure 4.36(a)) with the static operating point at Q_a = (V_DS,Q, I_D,Q) = (18/3 V, 0.3 mA) was designed so that it could have the voltage gain A_v,d = −20 and input resistance R_i,d = 100 kΩ. Perform the PSpice simulation with Time Domain analysis to see the output voltage v_o(t) to an AC input v_s(t) = V_sm sin (2000πt) (with V_sm = 0.3 V) as shown in Figure P4.20(a). If v_o(t) has any distortion, could it be predicted from the MATLAB analysis?
    2. Determine the resistor values of the CS FET amplifier with the static operating point at Q_b = (V_DS,Q, I_D,Q) = (6 V, 3 mA) so that it can have the same voltage gain A_v,d = −20 and input resistance R_i,d = 100 kΩ with I_D,Q increased from 0.3 mA to 3 mA. Use the MATLAB function ‘FET_CS_analysis()’ to analyze the designed circuit with the source/load resistance of R_s = 50 Ω/R_L = 50 kΩ. Does it give you any warning message of ohmic/cutoff regions to be trespassed on? Perform the PSpice simulation with Time Domain analysis to see the output voltage to an AC input v_s(t) = V_sm sin (2000πt) (with V_sm = 0.3 V) as shown in Figure P4.20(b). Does any distortion of v_o(t) agree with the warning message given by the MATLAB analysis?
    3. Determine the resistor values of the CS FET amplifier with the static operating point at Q_c = (V_DS,Q, I_D,Q) = (8 V, 3 mA) so that it can have the same voltage gain A_v,d = −20 and input resistance R_i,d = 100 kΩ with V_DS,Q increased from 6 V to 8 V. Use the MATLAB function ‘FET_CS_analysis()’ to analyze the designed circuit with the source/load resistance of R_s = 50 Ω/R_L = 50 kΩ. Does it give you any warning message of ohmic/cutoff regions to be trespassed on? Perform the PSpice simulation with Time Domain analysis to see the output voltage to an AC  input v_s(t) = V_sm sin (2000πt) (with V_sm = 0.3 V) as shown in Figure P4.20(c).
    4. Determine the resistor values of the CS FET amplifier with the static operating point at Q_d = (V_DS,Q, I_D,Q) = (4.5 V, 3 mA) so that it can have the same voltage gain A_v,d = −20 and input resistance R_i,d = 100 kΩ with V_DS,Q decreased from 6 V to 4.5 V. Use the MATLAB function ‘FET_CS_analysis()’ to analyze the designed circuit with the source/load resistance of R_s = 50 Ω/R_L = 50 kΩ. Does it give you any warning message of ohmic/cutoff regions to be trespassed on? Perform the PSpice simulation with Time Domain analysis to see the output voltage to an AC input v_s(t) = V_sm sin (2000πt) (with V_sm = 0.3 V) as shown in Figure P4.20(d). Does any distortion of v_o(t) agree with the warning message given by the MATLAB analysis?
    5. Determine the resistor values of the CS FET amplifier with the static operating point at Q_e = (V_DS,Q, I_D,Q) = (6 V, 20 mA) so that it can have the same voltage gain A_v,d = −20 and input resistance R_i,d = 100 kΩ with I_D,Q increased from 0.3 mA to 20 mA. Use the MATLAB function ‘FET_CS_analysis()’ to analyze the designed circuit with the source/load resistance of R_s = 50 Ω/R_L = 50 kΩ. Does it give you any warning message of ohmic/cutoff regions to be trespassed on? Perform the PSpice simulation with Time Domain analysis to see the output voltage to an AC input v_s(t) = V_sm sin (2000πt) (with V_sm = 0.3 V) as shown in Figure P4.20(e). Does any distortion of v_o(t) agree with the warning message given by the MATLAB analysis?

    

21. Frequency Response of an FET Cascode Amplifier

    Consider the FET cascode amplifier with PSpice schematic and simulation result on the frequency response in Figure P4.21(a) and (b), respectively, where V_DD = 12 V, R_s = 50 Ω, C_s = 100 μF, R₁ = 200 kΩ, R₂ = 100 kΩ, R₃ = 100 kΩ, R_S = 1 kΩ, C_S = 100 μF, C_G = 100 μF, R_D = 3 kΩ, C_L = 100 μF, R_L = 100 kΩ, C_LL = 0.1 nF, and the parameters of the enhancement type NMOSs are K_p = 10 mA/V², V_t = 1 V, and λ = 10⁻⁴ V⁻¹, C_gs0 = 10 pF, C_gd0 = 1 pF, and C_ds = 0 F.

    1. Complete the following MATLAB function ‘FET_cascode_DC_analysis()’, which performs the DC analysis to determine the node voltages and drain currents at the operating point.

       
       

    2. Complete the following MATLAB function ‘FET_cascode_xfer_ftn()’, which solves a set of 3, 4, or 5 node equations for the high‐frequency small‐signal equivalent (Figure P4.21(d)) depending on whether or not nodes 2/3 are AC grounded via capacitors C_SC/C_G, respectively, to find the transfer function G(s) = V_o(s)/V_s(s) of the cascade amplifier.
    3. Run the following MATLAB script “elec04p21.m” to perform the DC analysis (using ‘FET_cascode_DC_analysis()’), then based on the DC analysis result, use ‘FET_cascode_xfer_ftn()’ to find the transfer function G(s), and plot the frequency response magnitude 20log₁₀|G(jω)| [dB] of the cascade amplifier versus f = 1~100 MHz as shown in Figure P4.21(c).
    4. Perform the PSpice simulation (with AC Sweep analysis) to get the frequency response magnitude curve as depicted in Figure P4.21(b). Is the Bias Point analysis result (obtained as a by‐product) close to the DC analysis result obtained by using ‘FET_cascode_DC_analysis()’ in (c)?
22. Time Response of an FET Inverter with another Inverter as a Load

    Consider the FET inverter in Figure P4.22(a) where V_DD = 12 V, R_D = 10 kΩ, R_D1 = 10 kΩ, and the FET parameters are K_p = 5 mA/V², V_t = 1 V, λ = 10⁻⁴ V⁻¹, C_gs0 = 10 fF, C_gd0 = 1 fF, C_bd0 = 10 fF or 20 fF for M₁, and K_p = 5 mA/V², V_t = 1 V, λ = 10⁻⁴ V⁻¹, C_gs0 = 10 fF, C_gd0 = 1 fF, C_bd0 = 10 fF for M₂.

    Figure P4.22(b1) and (b2) shows the input/output voltage waveforms obtained from PSpice simulation, each with C_bd = 10 fF and 20 fF for M₁, respectively. Referring to Section 4.5 and Figure P4.22(b1‐b2), explain how a larger value of C_bd makes a longer time constant of v_o1 during its rising period.