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Appendix J
Diode/BJT/FET

J.1 Diode

The junction (depletion) and diffusion capacitances are

Schematic illustrating the piecewise linear current (PWL) approximation of the v–i characteristic curve of a diode (left) and circuit diagram of a PWL model of a diode consists of resistors labeled rf and Rr, etc. (right). — **Figure J.1** Piecewise linear current (PWL) approximation of the v‐i characteristic curve of a diode and the corresponding model.

Symbol for Zener diode (a), graph illustrating the v-I characteristics of a Zener diode (b), and PWL model of a Zener diode consists of 2 ideal diodes, 2 resistors, anode, cathode, and 2 battery sources (c). — **Figure J.2** Symbol, v‐i characteristic, and PWL model of a Zener diode.

Circuit diagrams illustrating high-frequency AC model of a forward-biased diode consists of capacitor labeled Cj + Cd, etc. (a) and high-frequency AC model of a reversed-biased diode consists of resistors, etc. (b). — **Figure J.3** High‐frequency AC (small‐signal) model of a diode.

Table J.1 PSpice model parameters of diode.

SPICE name	Model parameter	Default value
IS	Transport saturation current I_s	10⁻¹⁴
RS	Ohmic (series) resistance R_s	0 [Ω]
N	Emission (ideality) coefficient η	1
CJO	Zero‐bias junction capacitance C_j0	0
VJ	PN junction (built‐in) potential ϕ_B	1 [V]
MJ	PN grading coefficient m	0.5
TT	Transit time τ_t	0 [s]
BV	Reverse breakdown voltage V_Z	∞ [V]
IBV	Reverse breakdown current I_Z	10⁻³

(J.1)

J.2 BJT (Bipolar Junction Transistor)

g_m: transconductance (gain)
(J.2)

(J.3)

C_be/C_bc: zero‐bias B‐E/B‐C junction capacitances
(J.4)

C_be0(CJE)/C_bc0(CJC): zero‐bias B‐E/B‐C junction capacitances
V_BE,Q/V_BC,Q: quiescent B‐E/B‐C voltages [V]
m_be(MJE)/m_bc(MJC): B‐E/B‐C grading coefficient
ϕ_be(VJE)/ϕ_bc(VJC): B‐E/B‐C built‐in potential

Circuit diagrams illustrating high-frequency small-signal model consists of resistors labeled rbc, rb, rbe, etc. (left) and low-frequency small-signal model consists of resistors labeled rb, rbe, etc. (right). — **Figure J.4** Hybrid‐π small‐signal models of NPN‐BJT with or without frequency dependence.

Table J.2 PSpice model parameters of BJT.

SPICE name	Model parameter	Default value
BF	Forward active current gain β_F	100
BR	Reverse active current gain β_R	1
IS	Transport saturation current I_s	10⁻¹⁶
ISC	B‐C leakage saturation current I_sc	0
CJE	B‐E zero‐bias junction (depletion) capacitance C_be0	0
CJC	B‐C zero‐bias junction (depletion) capacitance C_bc0	0
VJE	B‐E built‐in potential ϕ_be	0.75 [V]
VJC	B‐C built‐in potential ϕ_bc	0.75 [V]
VAF	Forward mode Early voltage	∞ [V]
VAR	Reverse mode Early voltage	∞ [V]
NF	Forward ideality factor (current emission coefficient)	1
NR	Reverse ideality factor (current emission coefficient)	1
MJE	B‐E capacitance exponent m_be	0.33
MJC	B‐C capacitance exponent m_bc	0.33
RB	Base resistance r_b	0 [Ω]
RE	Emitter resistance r_e	0 [Ω]
RC	Collector resistance r_c	0 [Ω]

images — **Table J.3** Characteristics of CE/CC/CB amplifiers (β = g_mr_be = (I_C,Q/V_T)r_be).

	CE	CC	CB
R_i	R_B\|\|{r_b+r_be+(β+1)R_E1}(3.2.1)	R_B\|\|{r_b+r_be+(β+1)(R_E\|\|R_L)}(3.2.5)	(3.2.9)
R_o	R_C\|\|r_o≈R_C(3.2.4)	(3.2.8)	R_C\|\|r_o1(3.2.12)
A_v	(3.2.3)	(3.2.7)	(3.2.11)
A_i	(3.2.2)

function [gm,rbe,re,ro]=gmrbero_BJT(ICQ,beta,VA,VT)
if VT>0.1, VT=(273+VT)/11605; end % considering VT as T
gm=abs(ICQ)/VT; % Transconductance gain
rbe=beta/gm; re=rbe/(beta+1);
ro=VA/abs(ICQ); % Eqs.(3.1.26-28)

(J.5a)

(J.5b)

(J.5c)

function [iC,iB,iE]=iCiBiE(vBE,vCE,Is,Isc,bF,bR,T,VA)
if nargin<8, VA=1e8; end
if nargin<7, T=27; end
VT=(T+273)/11605; vBC=vBE-vCE;
iCf=@(vBE,vCE)(Is*(exp(vBE/VT)-1)-Isc*(exp(vBC/VT)-1)) ...
            .*(1+vCE/VA); % Eq. (J.5a)
iBf=@(vBE,vCE)(Is/bF*(exp(vBE/VT)-1)-Isc/(bR+1) ...*(exp(vBC/VT)-1)).*(1+vCE/VA); % Eq. (J.5b)
iEf=@(vBE,vCE)iBf(vBE,vCE)+iCf(vBE,vCE);
iB=iBf(vBE,vCE); iC=iCf(vBE,vCE); iE=iEf(vBE,vCE);

J.3 FET (Field Effect Transistor)

The body effect or substrate sensitivity^[J-1] of the threshold voltage V_t is described by

(J.6)

The gate‐source and gate‐drain capacitances are modeled as voltage‐dependent capacitances:

Circuit diagrams illustrating high-frequency small-signal model consists of capacitors labeled Cgd, Cgs, and Cds, etc. (a) and low-frequency small-signal model consists of resistor labeled ro, etc. (b). — **Figure J.5** Small‐signal models of FET.

Table J.4 PSpice model parameters of FET.

SPICE name	Model parameter	Default value
VTO	Zero‐bias threshold voltage V_t0	0 [V]
KP	Transconductance parameter K_p = μ_pC_OX(W/L)	2 × 10⁻⁵ [A/V²]
GAMMA	Bulk threshold parameter γ	0 [V^1/2]
PHI	Surface (bulk) potential ϕ	0.6 [V]
LAMBDA	Channel length modulation parameter λ	0 [V⁻¹]
PB	Built‐in potential for the bulk (substrate) junction V_b	0.8 [V]
CGSO	Gate‐source overlap capacitance per meter channel length C_gs0	0 [F/m]
CGDO	Gate‐drain overlap capacitance per meter channel length C_gd0	0 [F/m]
CGBO	Gate‐bulk overlap capacitance per meter channel length C_gb0	0 [F/m]
MJ	Bulk junction bottom grading coefficient m	0.5

Symbol of n-channel JFET. — **Table J.5** Circuit symbols and i‐v relationships of JFET and MOSFET.

Symbol of n-channel enhancement MOSFET. — **Table J.5** Circuit symbols and i‐v relationships of JFET and MOSFET.

FET type	n‐Channel	p‐Channel
Circuit symbols
Thresholdvoltage V_t	−	+	−	+	−	−
Conductionconstant K_p		Process conduction parameter		Process conduction parameter
Turn‐on condition	v_GS > V_t and v_DS > 0	v_SG > ∣V_t ∣and v_SD > 0
Triode region (Ohmic mode)	v_GD = v_G − v_D > V_t > 0	v_DG = v_D − v_G > ∣V_t∣
with overdrive voltage v_OV = v_GS − V_t	(4.1.13a) with overdrive voltage v_OV = v_SG − ∣V_t∣
Saturation region (Pinch‐off mode)	v_GD = v_G − v_D ≤ V_t	v_DG = v_D − v_G ≤ ∣V_t∣
i_D ≅ K_p(v_GS − V_t)²/2	i_D ≅ K_p(v_SG − ∣V_t∣)²/2(4.1.13b)

where C_gs0/C_gd0: zero‐bias gate‐source/gate‐drain junction capacitances, respectively, V_GS,Q/V_GD,Q [V]: quiescent gate‐source/gate‐drain voltages, respectively, m(MJ): gate p‐n grading coefficient (SPICE default = 0.5), and V_b(PB): gate junction (barrier) potential, typically 0.6 V (SPICE default = 1 V).

	CS (common source)	CD (common drain) – source follower	CG (common gate)
R_i	R₁‖R₂ (4.2.5)	R₁‖R₂ (4.2.10)	(4.2.15)
R_o	R_D‖{r_o + (1 + g_mr_o)R_S1} (4.2.7)	(4.2.12)	R_D‖{r_o + (1 + g_mr_o)(R_s‖R_S)} (4.2.17)
A_v	(4.2.6)	(4.2.11)	(4.2.16)

function [iD,mode]=iD_NMOS_at_vDS_vGS(vDS,vGS,Kp,Vt,lambda)
if nargin<5, lambda=0; end
% Kp=k'(W/L)=mu*Cox*W/L
vGD=vGS-vDS; ON=(vGS>Vt)&(vDS>0); SAT=(vGD<=Vt)&ON; TRI=(vGD>Vt)&ON;
iD = Kp*(1+lambda*vDS).*((vGS-Vt).^2/2.*SAT + ...
     ((vGS-Vt).*vDS-vDS.^2/2).*TRI); %Eq.(4.1.12,13)
iD = max(iD,0);
if SAT>0, mode='saturation';
elseif TRI>0, mode='ohmic';
 else mode='cutoff';
end

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Table of Contents for Appendix J: Diode/BJT/FETDiode/BJT/FET

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J.1 Diode

J.2 BJT (Bipolar Junction Transistor)

J.3 FET (Field Effect Transistor)

Table of Contents for
Appendix J: Diode/BJT/FETDiode/BJT/FET