TTL/LS INTEGRATED CIRCUITS

INTRODUCTION

TTL IS THE BEST ESTABLISHED AND MOST DIVERSIFIED IC FAMILY. LS IS FUNCTIONALLY IDENTICAL TO TTL BUT IS SLIGHTLY FASTER AND USES 80% LESS POWER. TTL/LS CHIPS REQUIRE A REGULATED 4.75-5.25 VOLT POWER SUPPLY. HERE’S A SIMPLE BATTERY SUPPLY:

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THE DIODE DROPS THE BATTERY VOLTAGE TO A SAFE LEVEL. BOTH CAPACITORS SHOULD BE INSTALLED ON THE TTL/LS CIRCUIT BOARD. CIRCUITS WITH LOTS OF TTL/LS CHIPS CAN USE LOTS OF CURRENT. USE A COMMERCIAL 5 VOLT LINE POWERED SUPPLY TO SAVE BATTERIES. OR MAKE YOUR OWN. (SEE THE 7805 ON PAGE 86.)

OPERATING REQUIREMENTS

1. VCC MUST NOT EXCEED 5.25 VOLTS.

2. INPUT SIGNALS MUST NEVER EXCEED VCC AND SHOULD NOT FALL BELOW GND.

3. UNCONNECTED TTL/LS INPUTS USUALLY ASSUME THE H STATE … BUT DON’T COUNT ON IT! IF AN INPUT IS SUPPOSED TO BE FIXED AT H, CONNECT IT TO VCC.

4. IF AN INPUT IS SUPPOSED TO BE FIXED AT L, CONNECT IT TO GND.

5. CONNECT UNUSED AND/NAND/OR INPUTS TO A USED INPUT OF THE SAME CHIP.

6. FORCE OUTPUTS OF UNUSED GATES H TO SAVE CURRENT (NAND–ONE INPUT H; NOR – ALL INPUTS L).

7. USE AT LEAST ONE DECOUPLING CAPACITOR (0.01–0.1 µF) FOR EVERY 5-10 GATE PACKAGES, ONE FOR EVERY 2-5 COUNTERS AND REGISTERS AND ONE FOR EACH ONE-SHOT. DECOUPLING CAPACITORS NEUTRALIZE THE HEFTY POWER SUPPLY SPIKES THAT OCCUR WHEN A TTL/LS OUTPUT CHANGES STATES. THEY MUST HAVE SHORT LEADS AND BE CONNECTED FROM VCC TO GND AS NEAR THE TTL/LS ICs AS POSSIBLE.

8. AVOID LONG WIRES WITHIN CIRCUITS

9. IF THE POWER SUPPLY IS NOT ON THE CIRCUIT BOARD, CONNECT A 1–10 µF CAPACITOR ACROSS THE POWER LEADS WHERE THEY ARRIVE AT THE BOARD.

INTERFACING TTL/LS

1. 1 TTL OUTPUT WILL DRIVE UP TO 10 TTL OR 20 LS INPUTS.

2. 1 LS OUTPUT WILL DRIVE UP TO 5 TTL OR 10 LS INPUTS.

3. TTL/LS LED DRIVERS:

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TTL/LS TROUBLESHOOTING

1. DO ALL INPUTS GO SOMEWHERE?

2. ARE ALL IC PINS INSERTED INTO THE BOARD OR SOCKET?

3. DOES THE CIRCUIT OBEY ALL TTL/LS OPERATING REQUIREMENTS?

4. HAVE YOU FORGOTTEN A CONNECTION?

5. HAVE YOU USED ENOUGH DECOUPLING CAPACITORS? ARE THEIR LEADS SHORT?

6. IS VCC AT EACH CHIP WITHIN RANGE?

QUAD NAND GATE 7400/74LS00

THE BASIC BUILDING BLOCK CHIP FOR THE ENTIRE TTL FAMILY. VERY EASY TO USE. HUNDREDS OF APPLICATIONS.

CONTROL GATE

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INVERTER

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AND GATE

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OR GATE

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AND-OR GATE

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NOTE: PIN NUMBERS CAN BE REARRANGED IF DESIRED.

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NOR GATE

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4-INPUT NAND GATE

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EXCLUSIVE-OR GATE

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EXCLUSIVE-NOR GATE

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HALF ADDER

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D FLIP-FLOP

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WHEN ENABLE (E) INPUT IS HIGH, Q OUTPUT FOLLOWS D INPUT. NO CHANGE WHEN E IS LOW.

LED DUAL FLASHER

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FLASH RATE IS 2 Hz WHEN C1 AND C2 ARE 47µF.

RS LATCH

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GATED RS LATCH

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FUNCTIONS AS RS LATCH WHEN ENABLE (E) INPUT IS HIGH. IGNORES RS INPUTS WHEN E IS LOW.

SWITCH DEBOUNCER

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PROVIDES NOISE FREE OUTPUT FROM STANDARD SPDT TOGGLE SWITCH.

8-INPUT NAND GATE

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BCD DECODER

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USE THIS METHOD TO DECODE ANY 4-BIT NIBBLE. JUST ADD OR REMOVE INPUT INVERTERS.

IC1, 2 = 7400/74LS00

UNANIMOUS VOTE DETECTOR

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LED GLOWS

WHEN ALL

INPUT SWITCHES

ARE CLOSED.

IC 1, 2 = 7404

IC 3, 4 = 7400/74LS00

QUAD AND GATE 7408/74LS08

ONE OF THE BASIC BUILDING BLOCK CHIPS. NOT AS VERSATILE, HOWEVER, AS THE 7400/74LS00 QUAD NAND GATE.

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AND GATE BUFFER

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USE FOR INTERFACING WITHOUT CHANGING LOGIC STATES.

NAND GATE

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NOR GATE

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4-INPUT NAND GATE

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DIGITAL TRANSMISSION GATE

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AND-OR-INVERT GATE

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4-INPUT AND GATE

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QUAD OR GATE 74LS32

FOUR 2-INPUT OR GATES. NOT AS VERSATILE AS 7402/74LS02 QUAD NOR GATE, BUT VERY USEFUL IN SIMPLE DATA SELECTORS.

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AND-OR CIRCUIT

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OUTPUT GOES HIGH WHEN BOTH INPUTS OF EITHER OR BOTH AND GATES ARE HIGH; OTHERWISE THE OUTPUT IS LOW. THIS BASIC CIRCUIT IS USED TO MAKE DATA SELECTORS … AS SHOWN BELOW

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NOR GATE

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NAND GATE

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2-INPUT DATA SELECTOR

SELECTS 1-OF-2 INPUTS AND TRANSMITS ITS LOGIC STATE TO THE OUTPUT.

ADDRESS DATA IN OUT
A B A  
L X L L
L X H H
H L X L
H H X H

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NOTE: FOR 3-INPUT DATA SELECTOR, USE 74LS27 NOR GATE FOLLOWED BY INVERTER AND PRECEEDED BY 74LS10 3-INPUT AND GATES.

QUAD NOR GATE 7402/74LS02

JUST AS VERSATILE AS THE 7400/74LS00 QUAD NAND GATE… BUT NOT USED AS OFTEN. ADD INVERTER (7404/74LS04) TO BOTH INPUTS OF A NOR GATE AND AN AND GATE IS FORMED.

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EXCLUSIVE-OR GATE

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THIS CIRCUIT IS EQUIVALENT

TO A BINARY HALF-ADDER.

RS LATCH

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4-INPUT NOR GATE

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ONE-SHOT

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THIS CIRCUIT IS A MONOSTABLE MULTIVIBRATOR OR PULSE STRETCHER. AN INPUT PULSE TRIGGERS AN OUTPUT PULSE WITH A DURATION DETERMINED BY R AND C. OUTPUT PULSE WIDTH IS APPROXIMATELY 0.8RC.

AND GATE

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OR GATE

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DUAL 4-INPUT NAND GATE 74LS20

MANY DECODER AND ENCODER APPLICATIONS. CAN BE USED AS DUAL 3-INPUT NAND GATE WITH ENABLE (CONTROL) INPUT FOR EACH GATE.

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BCD DECODERS

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OUTPUTS GO HIGH WHEN APPROPRIATE BCD WORD APPEARS AT INPUTS DCBA. OUTPUTS STAY LOW FOR ALL OTHER INPUTS. (OMIT FINAL INVERTER TO PROVIDE ACTIVE LOW OUTPUT.) USE THIS METHOD TO DECODE ANY 4-BIT NIBBLE.

DECIMAL-TO-BINARY CODED DECIMAL (BCD) ENCODER

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SELECTED INPUT SHOULD BE LOW AND ALL OTHER INPUTS SHOULD BE HIGH. BCD EQUIVALENT WILL APPEAR AT THE OUTPUTS.

TRIPLE 3-INPUT NOR GATE 74LS27

USEFUL FOR DATA SELECTORS AND NOR GATE FLIP-FLOPS THAT REQUIRE CLEAR AND PRESET INPUTS.

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GATED RS LATCH

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FUNCTIONS AS RS LATCH WHEN E (ENABLE) INPUT IS HIGH. IGNORES RS INPUTS WHEN E IS LOW.

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3-INPUT OR GATE

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3-INPUT DATA SELECTOR

SELECTS 1-OF-3 INPUTS AND TRANSMITS ITS LOGIC STATE TO THE OUTPUT.

ADDRESS DATA IN OUT
B A C B A  
L L X X L L
L L X X H H
L H X L X L
L H X H X H
H L L X X L
H L H X X H
H H X X X L

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8-INPUT NAND GATE 74LS30

HANDY FOR BYTE-SIZE (8-BIT) DECODING APPLICATIONS. CAN DECODE UP TO 256 INPUT COMBINATIONS. ALSO USEFUL AS PROGRAMMABLE NAND GATE.

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8-BIT DECODER

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OUTPUT GOES LOW ONLY WHEN INPUT IS LHHLLHLL (DECIMAL 100). UP TO 256 INPUTS CAN BE DECODED BY REARRANGING UP TO 8 INPUT INVERTERS.

UNANIMOUS VOTE DETECTOR

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LED GLOWS WHEN ALL INPUT SWITCHES ARE CLOSED.

PROGRAMMABLE NAND GATES

5-INPUT

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6-INPUT

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7-INPUT

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DUAL AND-OR-INVERT GATE 74LS51

VERY VERSATILE BUILDING BLOCK CHIP. IDEAL FOR CUSTOMIZED DATA SELECTORS, LATCHES AND EXPANSION OF A SINGLE INPUT TO AN AND-OR INPUT.

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LATCH WITH ENABLE INPUT

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Q OUTPUT FOLLOWS DATA INPUT WHEN ENABLE INPUT IS HIGH. NO CHANGE WHEN ENABLE IS LOW.

THIS CIRCUIT SELECTS 1-OF-2 4-BIT WORDS. NOTE THAT THE SELECTED WORD IS INVERTED AT THE OUTPUTS. THE CIRCUIT REQUIRES TWO 74LS51 CHIPS.

  INPUT  
A X X OUT
H X L H
H X H L
L L X H
L H X L

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TYPICAL AND-OR INPUT

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1-OF-2 DATA SELECTOR

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DUAL NAND SCHMITT TRIGGER 74LS13

TWO 4-INPUT NAND GATES WITH A SWITCHING THRESHOLD. OUTPUTS GO LOW WHEN INPUTS EXCEED 1.7 VOLTS. OUTPUTS GO HIGH WHEN INPUTS FALL TO 0.9 VOLT. IF ANY INPUT IS LOW, THE RESPECTIVE OUTPUT WILL STAY HIGH AND THE GATE WILL NOT TRIGGER.

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GATED THRESHOLD DETECTOR

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GATED OSCILLATOR

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OSCILLATES WHEN CONTROL IS HIGH. CHANGE R1 AND C1 TO CHANGE FREQUENCY. OK TO USE THIS CIRCUIT AS GATED CLOCK FOR LOGIC CIRCUITS.

PHOTOTRANSISTOR RECEIVER

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USE TO CLEAN UP INCOMING LIGHT PULSES.

TWO-STATE LED FLASHER

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LED FLASHES TWICE EACH SECOND WHEN CONTROL INPUT IS HIGH. LED STAYS ON AND DOES NOT FLASH WHEN CONTROL IS LOW.

HEX INVERTER 7404/74LS04

VERY IMPORTANT IN ALMOST ALL LOGIC CIRCUITS. CHANGES AN INPUT TO ITS COMPLEMENT (i.e. H → L AND L → H).

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BOUNCEFREE SWITCH

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UNIVERSAL EXPANDER

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AUDIO OSCILLATOR

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1-OF-2 DEMULTIPLEXER

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THIS CIRCUIT STEERS THE INPUT BIT TO THE OUTPUT SELECTED BY THE ADDRESS.

THIS TECHNIQUE CAN BE USED TO MAKE MULTIPLE OUTPUT DEMULTIPLEXERS.

DATA ADDRESS OUT A OUT B
L L L L
H L H L
L H L H
H H L L

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HEX 3-STATE BUS DRIVER 74LS367

EACH GATE FUNCTIONS AS A NON-INVERTING BUFFER WHEN ITS ENABLE INPUT (G1 OR G2) IS LOW. OTHERWISE EACH GATE’S OUTPUT ENTERS THE HIGH IMPEDANCE (H1-Z) STATE.

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HERE’S THE TRUTH TABLE:

G IN OUT
H X H1 - Z
L L L
L H H

1-OF-2 DATA SELECTOR

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1-OF-2 DATA SELECTOR

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ADDING 3-STATE OUTPUT TO TTL

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BIDIRECTIONAL DATA BUS

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HEX 3-STATE BUS DRIVER 74LS368

EACH GATE FUNCTIONS AS AN INVERTER WHEN ITS ENABLE INPUT (G1 OR G2) IS LOW. OTHERWISE EACH GATE’S OUTPUT ENTERS THE HIGH IMPEDANCE (H1-Z) STATE.

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HERE’S THE TRUTH TABLE:

G IN OUT
H X H1 - Z
L L H
L H L

BIDIRECTIONAL DATA BUS

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ONLY ONE INPUT GATE CAN BE ENABLED AT ONE TIME. ANY NUMBER OF OUTPUT GATES CAN BE ENABLED.

GATED TONE SOURCE

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GATED LED FLASHER

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BOUNCELESS SWITCH (WITH ENABLE)

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4-BIT MAGNITUDE COMPARATOR 74LS85

COMPARES TWO 4-BIT WORDS. INDICATES WHICH IS LARGER OR IF THEY ARE EQUAL.

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8-BIT COMPARATOR

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BINARY HI-LO GAME

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PRESS S1 FOR A FEW SECONDS TO LOAD RANDOM NUMBER IN 74193/74LS193. USE DIP SWITCH ARRAY OR TOGGLES FOR S2-S5

ENTER GUESSES IN S2-S5. AN OPEN SWITCH IS HIGH AND A CLOSED SWITCH IS LOW.

BCD-TO-DECIMAL DECODER 7441

DECODES 4-BIT BCD INPUT INTO 1-OF-10 OUTPUTS. SELECTED OUTPUT GOES LOW; ALL OTHERS STAY HIGH. ORIGINALLY DESIGNED TO DRIVE GASEOUS GLOW DISCHARGE TUBES. ALL OUTPUTS GO HIGH FOR BINARY INPUTS EXCEEDING HLLH (1001).

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1-OF-10 DECODED COUNTER

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LEDS FLASH ON SEQUENTIALLY IN RESPONSE TO DECODED COUNT. ONLY ONE LED SERIES RESISTOR IS REQUIRED.

10-NOTE TONE SEQUENCER

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INCREASE C1 TO DECREASE TEMPO. INCREASE C2 TO INCREASE TONE FREQUENCIES. TONES ARE DETERMINED BY R3-R12.

BCD-TO-7 SEGMENT DECODER/DRIVER 7447/74LS47

CONVERTS BCD DATA INTO FORMAT SUITABLE FOR PRODUCING DECIMAL DIGITS ON COMMON ANODE LED 7-SEGMENT DISPLAY. WHEN LAMP TEST INPUT IS LOW, ALL OUTPUTS ARE LOW (ON). WHEN B1/RBO (BLANKING INPUT) IS LOW, ALL OUTPUTS ARE HIGH (OFF). WHEN DCBA INPUT IS LLLL (DECIMAL 0) AND RBI (RIPPLE BLANKING INPUT) IS LOW, ALL OUTPUTS ARE HIGH (OFF). THIS PERMITS UNWANTED LEADING 0’S IN A ROW OF DIGITS TO BE BLANKED.

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MANUALLY SWITCHED DISPLAY

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DISPLAY FLASHER

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THIS SIMPLE CIRCUIT WILL FLASH DISPLAY TWICE PER SECOND.

0-9 SECOND/MINUTE TIMER

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CLOSE S1 TO START TIMING CYCLE. CALIBRATE 555 FOR 1 PULSE (COUNT) PER SECOND OR 1 COUNT PER MINUTE BY ADJUSTING R1.

BCD-TO-7-SEGMENT DECODER/DRIVER 7448

CONVERTS BCD DATA INTO FORMAT SUITABLE FOR PRODUCING DECIMAL DIGITS ON COMMON CATHODE LED 7-SEGMENT DISPLAY.

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*SEE 7447 FOR EXPLANATIONS.

DISPLAY DIMMER

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0-99 TWO DIGIT COUNTER

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3-LINE TO 8-LINE DECODER 74LS138

EACH 3-BIT ADDRESS DRIVES ONE OUTPUT LOW. ALL OTHERS STAY HIGH. THIS CHIP HAS THREE ENABLE INPUTS. WHEN E2 IS HIGH, ALL OUTPUTS ARE HIGH. WHEN E1 IS LOW, ALL OUTPUTS ARE HIGH. TO ENABLE CHIP, MAKE E1 HIGH AND E2 LOW. (NOTE: E2 = E2A + E2B.)

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1-TO-8 DEMULTIPLEXER

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INPUT DATA (H OR L) IS PASSED TO SELECTED OUTPUT.

2-TO-8 STEP SEQUENCER

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TO DESIRED SEQUENCE (e.g. CONNECT TO OUTPUT 4 AND CIRCUIT WILL CYCLE FROM 0 TO 3).

USE TO FLASH LEDS, CONTROL RELAYS, ETC.

4-LINE TO 16-LINE DECODER 74154

EACH 4-BIT ADDRESS DRIVES ONE OUTPUT LOW. ALL OTHERS STAY HIGH. ENABLE INPUTS (E1 AND E2) MUST BE LOW. IF ONE OR BOTH ARE HIGH, ALL OUTPUTS GO LOW.

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1-TO-16 DEMULTIPLEXER

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SELECTED OUTPUT IS LOW WHEN DATA IN IS LOW. IF DATA IN IS HIGH, SELECTED OUTPUT IS HIGH.

BACK AND FORTH FLASHER

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INCREASE R1 TO SLOW FLASH RATE.

QUAD 1-OF-2 DATA SELECTOR 74LS157

FOUR 2-LINE TO 1-LINE MULTIPLEXERS. MANY USES IN ROUTING DATA. ALL 4 DATA SELECTORS ARE ENABLED WHEN PIN 15 IS LOW.

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DOUBLE DUTY DISPLAY

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BUS SELECTOR

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WORD SORTER

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THIS CIRCUIT CONTINUALLY MONITORS TWO DATA BUSES. BUS WITH HIGHEST MAGNITUDE DATA WORD IS ROUTED AUTOMATICALLY TO OUTPUT.

1-OF-8 DATA SELECTOR 74LS151

EQUIVALENT TO 8-LINE TO 1-LINE MULTIPLEXER.

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PROGRAMMABLE GATE

3-BIT ADDRESS SELECTS ONE SWITCH AND APPLIES ITS STATUS (OPEN = HIGH AND CLOSED = LOW) TO THE OUTPUT. ANY 3-INPUT LOGIC FUNCTION CAN BE PROGRAMMED IN SECONDS.

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PATTERN GENERATOR

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PROGRAM ANY DESIRED LOW-HIGH BIT PATTERN. THEN PLAY IT BACK.

OCTAL KEYBOARD ENCODER

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PRESS NUMBERED SWITCH AND ITS BINARY EQUIVALENT APPEARS ON THE READOUT LEDS. THE LEDS ARE OPTIONAL.

DUAL ONE-SHOT 74LS123

TWO FULLY INDEPENDENT MONOSTABLE MULTIVIBRATORS. BOTH ARE RETRIGGERABLE. PINS DESIGNATED R AND R/C ARE FOR EXTERNAL TIMING RESISTOR AND CAPACITOR.

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BASIC ONE-SHOT

TWO WAYS TO TRIGGER:

1. KEEP INPUTS A AND B LOW; THEN MAKE B HIGH.

2. KEEP INPUTS A AND B HIGH; THEN MAKE A LOW.

TO CLEAR:

MAKE PIN 3 LOW. THIS ALSO INHIBITS TRIGGERING.

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MISSING PULSE DETECTOR

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Q OUTPUT STAYS HIGH SO LONG AS INCOMING PULSES ARRIVE BEFORE ONE-SHOT TIMING PERIOD RUNS OUT.

ADJUST R AND C TO GIVE TIMING PERIOD ABOUT 1/3 LONGER THAN THE INTERVAL BETWEEN INCOMING PULSES.

OPERATION:

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TONE STEPPER

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THIS CIRCUIT STEPS ACROSS A RANGE OF TONES WHEN R1 AND/OR R3 ARE ADJUSTED. VERY UNUSUAL SOUND EFFECTS.

CHANGE C1 AND C2 FOR OTHER TONE RANGES. ALSO, TRY PHOTORESISTORS FOR R1 AND R3.

DUAL D FLIP-FLOP 7474/74LS74

TWO D (DATA) FLIP-FLOPS IN A SINGLE PACKAGE. DATA AT D INPUT IS STORED AND MADE AVAILABLE AT Q OUTPUT WHEN CLOCK PULSE (φ) GOES HIGH. HERE’S THE TRUTH TABLE:

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PRESET CLEAR CLOCK D Q P®image
L H X X H L
H L X X L H
H H ↑ H H L
H H ↑ L L H

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2-BIT STORAGE REGISTER

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WAVE SHAPER

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PHASE DETECTOR

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THE LED GLOWS WHEN INPUT FREQUENCIES F1 AND F2 ARE UNEQUAL OR OUT OF PHASE. F1 AND F2 SHOULD BE SQUARE WAVES.

DIVIDE-BY-TWO COUNTER

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DUAL J-K FLIP-FLOP 7473

TWO JK FLIP-FLOPS IN A SINGLE PACKAGE. NOTE THE CLEAR INPUTS. THESE FLIP-FLOPS WILL TOGGLE (SWITCH OUTPUT STATES) IN RESPONSE TO INCOMING CLOCK PULSES WHEN BOTH J ANK J INPUTS ARE HIGH. HERE’S THE TRUTH TABLE:

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CLEAR CLOCK J K Q O®image
L X X X L H
H image H L H L
H image L H L H
H image H H TOGGLE

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DIVIDE-BY-TWO

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DIVIDE-BY-THREE

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BINARY COUNTERS

THE THREE CIRCUITS ON THIS PAGE ARE BINARY COUNTERS THAT COUNT UP TO THE MAXIMUM COUNT AND AUTOMATICALLY RECYCLE. CONNECT A DECODER TO OUTPUT OF DIVIDE-BY-THREE AND DIVIDE-BY-FOUR COUNTERS TO OBTAIN ONE - OF - THREE AND ONE-OF-FOUR OPERATION. THIS TRUTH TABLE SUMMARIZES OPERATION OF THESE COUNTERS:

DIVIDE-BY: TWO THREE FOUR
OUTPUTS: A B A B A
  L L L L L
  H L H L H
    H L H L
        H H

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DIVIDE-BY-FOUR

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DUAL J-K FLIP-FLOP 7476

TWO JK FLIP-FLOPS IN A SINGLE PACKAGE. SIMILAR TO 7473/74LS73 BUT HAS BOTH PRESET AND CLEAR INPUTS. FLIP-FLOPS WILL TOGGLE (SWITCH OUTPUT STATES) IN RESPONSE TO INCOMING CLOCK PULSES WHEN BOTH J AND K INPUTS ARE HIGH. HERE’S THE TRUTH TABLE:

PRE CLR CLK J K Q Q®image
L H X X X H L
H L X X X L H
H H image H L H L
H H image L H L H
H H image H H TOGGLE

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TOGGLE = FLIP-FLOP SWITCHES OUTPUT STATES IN RESPONSE TO CLOCK PULSES.

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4-BIT SERIAL SHIFT REGISTER

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4-BIT BINARY UP COUNTER

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QUAD LATCH 7475/74LS75

A 4-BIT BISTABLE LATCH. PRIMARILY USED TO STORE THE COUNT IN DECIMAL COUNTING UNITS. NOTE THAT BOTH Q AND Q¯image OUTPUTS ARE PROVIDED. ALSO NOTE THE E (ENABLE) INPUTS. WHEN E IS HIGH, Q FOLLOWS D.

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4-BIT DATA LATCH

DATA ON BUS APPEARS AT OUTPUTS WHEN LATCH INPUT IS HIGH. DATA ON BUS WHEN LATCH INPUT GOES LOW IS STORED UNTIL LATCH INPUT GOES HIGH. (LATCH INPUT CONTROLS BOTH ENABLE INPUTS.) TWO QUAD LATCHES CAN BE USED AS AN 8-BIT DATA LATCH.

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DECIMAL COUNTING UNIT

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EXPANDABLE DECADE COUNTER. FOR TWO DIGIT COUNT, CONNECT PIN 11 OF 7490/74LS90 OF FIRST UNIT TO INPUT OF SECOND UNIT. A LOW AT THE LATCH INPUT FREEZES THE DATA BEING DISPLAYED.

QUAD D FLIP-FLOP 74LS175

HANDY PACKAGE OF FOUR D-TYPE FLIP-FLOPS. DATA AT D-INPUTS IS LOADED WHEN CLOCK GOES HIGH. MAKING CLEAR INPUT LOW MAKES ALL Q OUTPUTS LOW AND Q®image OUTPUTS HIGH.

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4-BIT DATA REGISTER

DATA ON BUS IS LOADED INTO 74LS175 WHEN LOAD INPUT GOES HIGH. DATA IS THEN STORED AND MADE AVAILABLE AT OUTPUTS UNTIL NEW LOAD PULSE ARRIVES.

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MODULO-8 COUNTER

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SERIAL IN/OUT, PARALLEL OUT SHIFT REGISTER

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BCD (DECADE) COUNTER 7490/74LS90

ONE OF THE MOST POPULAR DECADE COUNTERS. EASILY USED FOR DIVIDE-BY-N COUNTERS. LESS EXPENSIVE THAN MORE SOPHISTICATED COUNTERS. RST INDICATES RESET PINS. THIS CHIP IS USUALLY USED IN DECIMAL COUNTING UNITS, BUT CIRCUITS ON THIS PAGE SHOW MANY OTHER POSSIBILITIES.

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DIVIDE-BY-5 COUNTER

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DIVIDE-BY-6 COUNTER

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DIVIDE-BY-7 COUNTER

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DIVIDE-BY-8 COUNTER

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DIVIDE-BY-9 COUNTER

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DIVIDE-BY-10 COUNTER

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BCD (DECADE) COUNTER 74LS196

MORE SOPHISTICATED VERSION OF THE POPULAR 7490/74LS90 BCD COUNTER. INCLUDES 4-PRESET INPUTS WHICH PERMIT ANY BCD NUMBER TO BE LOADED WHEN PIN 1 IS MADE LOW. THE COUNTER IS CLEARED TO LLLL WHEN PIN 13 IS MADE LOW. φ INDICATES CLOCK INPUT.

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DECADE COUNTER

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DIVIDE-BY-5 COUNTER

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0-4 COUNT IS AVAILABLE AT DCBA OUTPUTS.

4-BIT LATCH

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WHEN LOAD INPUT IS LOW, OUTPUTS FOLLOW INPUTS. NO CHANGE WHEN LOAD INPUT IS HIGH. NOTE THAT A PAIR OF 74LS196’S CAN BE USED IN A DECIMAL COUNTING UNIT (COUNTER PLUS REGISTER).

DIVIDE-BY-10 COUNTER

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DIVIDE-BY-12 BINARY COUNTER 7492

OFTEN USED TO DIVIDE CONDITIONED 60 HZ PULSES FROM AC POWER LINE INTO 10 HZ PULSES. OTHER DIVIDER APPLICATIONS ALSO. RST INDICATES RESET PINS.

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DIVIDE-BY-7 COUNTER

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DIVIDE-BY-9 COUNTER

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DIVIDE-BY-12 COUNTER

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10-HZ PULSE SOURCE

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DIVIDE-BY-120 COUNTER

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THIS METHOD OF CASCADING COUNTERS CAN BE USED TO CREATE ANY DIVIDE-BY-N COUNTER.

4-BIT (BINARY) COUNTER 7493/74LS93

EASY TO USE 4-BIT BINARY COUNTER. LESS EXPENSIVE THAN MORE SOPHISTICATED COUNTERS. RST INDICATES RESET PINS. NOTE UNUSUAL LOCATION OF POWER SUPPLY PINS.

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DIVIDE-BY-10 COUNTER

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DIVIDE-BY-11 COUNTER

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DIVIDE-BY-12 COUNTER

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DIVIDE-BY-16 COUNTER

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4-BIT BINARY COUNTER

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COUNTS FROM 0-15 IN BINARY AND RECYCLES. GLOWING LED = L (0); OFF LED = H (1). 555 TIMER IC MAKES GOOD INPUT CLOCK.

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BCD UP-DOWN COUNTER 74192

FULLY PROGRAMMABLE BCD COUNTER. OPERATION IS IDENTICAL TO 74193/74LS193 EXCEPT COUNT IS 10-STEP BCD (LLLL-HLLH) INSTEAD OF 16-STEP BINARY. MANY APPLICATIONS FOR 74192/74LS192 AND 74193/74LS193 ARE INTERCHANGEABLE.

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CASCADED COUNTERS

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SINGLE UP-DOWN INPUT

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PROGRAMMABLE COUNT DOWN TIMER

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CALIBRATE R1 AND C1 TO PROVIDE DESIRED NUMBER OF CLOCK PULSES PER MINUTE. SET DESIRED N INTO S1-S4 (CLOSED SWITCH = LOW AND OPEN SWITCH = HIGH). PRESS S5 TO LOAD N AND START (OR RESET) COUNT. LED GLOWS AT HALT.

4-BIT UP COUNTER 74LS161

GENERAL PURPOSE BINARY COUNTER WITH PROGRAMMABLE INPUTS. COUNTER ACCEPTS DATA AT INPUTS WHEN LOAD INPUT GOES LOW. A LOW AT THE CLEAR INPUT RESETS THE COUNTER TO LLLL UPON THE NEXT CLOCK PULSE. P AND T ARE COUNT ENABLE INPUTS. BOTH P AND T MUST BE HIGH TO COUNT. THESE ENABLE INPUTS ARE NOT AVAILABLE WITH THE OTHERWISE MORE ADVANCED 74LS193.

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8-BIT COUNTER

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OUTPUT A IS LOWEST ORDER BIT.

RAMP SYNTHESIZER

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REMOVE C1 TO OBTAIN THIS STAIRCASE. FREQUENCY OF RAMP AND STAIRCASE IS 1/16 CLOCK FREQUENCY.

4-BIT UP-DOWN COUNTER 74193/74LS193

VERY VERSATILE 4-BIT COUNTER WITH UP-DOWN CAPABILITY. ANY 4-BIT NUMBER AT THE DCBA INPUTS IS LOADED INTO THE COUNTER WHEN THE LOAD INPUT (PIN 11) IS MADE LOW. THE COUNTER IS CLEARED TO LLLL WHEN THE CLEAR INPUT (PIN 14) IS MADE HIGH. THE BORROW AND CARRY OUTPUTS INDICATE UNDERFLOW OR OVERFLOW BY GOING LOW.

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COUNT DOWN FROM N AND RECYCLE

SET DESIRED N INTO S1-S4 (CLOSED SWITCH = LOW AND OPEN SWITCH = HIGH). WHEN COUNT REACHES LLLL AND THEN UNDERFLOWS, THE BORROW PULSE LOADS N AND THE COUNT RECYCLES.

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COUNT UP TO N AND HALT

PRESS S1 (NORMALLY CLOSED) TO RESET.

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COUNT UP TO N AND RECYCLE

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NOTES

4-BIT SHIFT REGISTER 74LS194

BIDIRECTIONAL UNIVERSAL SHIFT REGISTER. SHIFTS RIGHT WHEN SO IS HIGH AND S1 IS LOW. SHIFTS LEFT WHEN SO IS LOW AND S1 IS HIGH. SHIFTS ONE POSITION PER CLOCK PULSE. LOADS DATA AT INPUTS WHEN SO AND S1 ARE HIGH. IMPORTANT: BYPASS POWER SUPPLY PINS WITH 0.1µF CAPACITOR!

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SEQUENCE GENERATOR

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LOAD ANY DESIRED BIT PATTERN INTO S1-S8 (OPEN = HIGH AND CLOSED = LOW). PRESS S9 (NORMALLY CLOSED) TO LOAD. DATA WILL MOVE RIGHT ONE OUTPUT PER CLOCK PULSE. LEDS ARE OPTIONAL.

BARGRAPH GENERATOR

WHEN POWER IS FIRST APPLIED, MAKE ENABLE INPUT LOW TO START CIRCUIT.

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OUTPUTS GO LOW AND STAY LOW ONE AT A TIME FROM LEFT TO RIGHT (A→D) IN SEQUENCE WITH CLOCK. WHEN FINAL OUTPUT GOES LOW, ALL OUTPUTS BUT THE FIRST GO HIGH AND RECYCLE.

8-BIT SHIFT REGISTER 74LS164

DATA AT ONE OF THE TWO SERIAL INPUTS IS ADVANCED ONE BIT FOR EACH CLOCK PULSE. DATA CAN BE EXTRACTED FROM THE 8 PARALLEL OUTPUTS OR IN SERIAL FORM AT ANY SINGLE OUTPUT. ENTER DATA AT EITHER INPUT. THE UNUSED INPUT MUST BE HELD HIGH OR CLOCKING WILL BE INHIBITED. MAKING PIN 9 LOW CLEARS THE REGISTER TO LLLL.

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8-BIT SERIAL-TO-PARALLEL DATA CONVERTER

USE FOR RECEIVING BINARY DATA SENT OVER ONE CHANNEL.

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PSEUDO-RANDOM VOLTAGE GENERATOR

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OCTAL BUFFER 74LS240

IDEAL FOR INTERFACING EXTERNAL CIRCUITS TO HOME COMPUTERS. INVERTS DATA.

CONTROL (E1, E2) OUT
L IL®image
H image

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4-BIT BUS TRANSFER

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8-BIT BUS BUFFER

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OCTAL BUFFER 74LS244

NON-INVERTING VERSION OF 74LS240. IDEAL FOR COMPUTER INTERFACING.

CONTROL (E1, E2) OUT
L IN®image
H image

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4-BIT BUS TRANSFER

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8-BIT BUS BUFFER

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OCTAL D-TYPE LATCH 74LS373

EIGHT “TRANSPARENT” D-TYPE LATCHES. OUTPUT FOLLOWS INPUT WHEN ENABLE IS HIGH. THE DATA AT THE INPUTS IS LOADED WHEN THE ENABLE INPUT IS LOW. THIS CHIP HAS 3-STATE OUTPUTS WHICH ARE CONTROLLED BY PIN 1. SEE TRUTH TABLE BELOW.

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3-STATE REGISTER

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THIS IS A GENERAL PURPOSE 8-BIT STORAGE REGISTER. HERE’S THE TRUTH TABLE:

OUTPUT CONTROL ENABLE D Q
L H H H
L H L L
L L X Q
H X X H1-Z

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DATA BUS REGISTERS

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AT ANY INSTANT ONLY ONE 74LS373 CAN WRITE DATA ON THE BUS. ANY NUMBER CAN READ DATA FROM BUS.

OCTAL D FLIP-FLOP 74LS374

EIGHT D-TYPE EDGE TRIGGERED FLIP-FLOPS. UNLIKE 74LS373, OUTPUTS DO NOT FOLLOW INPUTS. INSTEAD, A RISING CLOCK PULSE AT PIN 11 LOADS DATA APPEARING AT INPUTS. THIS CHIP HAS 3-STATE OUTPUTS WHICH ARE CONTROLLED BY PIN 1.

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CLOCKED 3-STATE REGISTER

GENERAL PURPOSE CLOCKED REGISTER. HERE’S THE TRUTH TABLE:

OUTPUT CONTROL CLOCK D Q
L image H H
L image L L
L H X Q
H X X H1-Z

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COMMON INPUT/OUTPUT BUS REGISTER

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THIS CIRCUIT GIVES 74LS374 COMMON INPUT AND OUTPUT LINES. WHEN OUTPUT CONTROL IS HIGH, DATA ON BUS IS LOADED INTO THE 74LS374 ON THE RISING EDGE (image) OF THE CLOCK PULSE. WHEN OUTPUT CONTROL IS LOW, DATA IN THE 74LS374 IS WRITTEN ONTO THE BUS.

OCTAL BUS TRANSCEIVER 74LS245

ALLOWS DATA TO BE TRANSFERRED IN EITHER DIRECTION BETWEEN TWO BUSES. INCLUDES HIGH IMPEDANCE (H1-Z) OUTPUTS.

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BUS TRANSCEIVER

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