The target architecture can be described in terms of the registers present, the instruction set, and so on. Describing each of them manually is a tedious task. TableGen is a tool for backend developers that describes their target machine with a declarative language—*.td. The *.td files will be converted to enums, DAG-pattern matching functions, instruction encoding/decoding functions, and so on, which can then be used in other C++ files for coding.
To define registers and the register set in the target description's .td files, tablegen will convert the intended .td file into .inc files, which will be #include syntax in our .cpp files referring to the registers.
Let's assume that the sample target machine has four registers, r0-r3; a stack register, sp; and a link register, lr. These can be specified in the SAMPLERegisterInfo.td file. TableGen provides the Register class, which can be extended to specify registers.
- Create a new folder in
lib/TargetnamedSAMPLE:$ mkdir llvm_root_directory/lib/Target/SAMPLE - Create a new file called
SAMPLERegisterInfo.tdin the newSAMPLEfolder:$ cd llvm_root_directory/lib/Target/SAMPLE $ vi SAMPLERegisterInfo.td
- Define the hardware encoding, namespace, registers, and register class:
class SAMPLEReg<bits<16> Enc, string n> : Register<n> { let HWEncoding = Enc; let Namespace = "SAMPLE"; } foreach i = 0-3 in { def R#i : R<i, "r"#i >; } def SP : SAMPLEReg<13, "sp">; def LR : SAMPLEReg<14, "lr">; def GRRegs : RegisterClass<"SAMPLE", [i32], 32, (add R0, R1, R2, R3, SP)>;