The instruction set of an architecture varies according to various features present in the architecture. This recipe demonstrates how instruction sets are defined for the target architecture.
Three things are defined in the instruction target description file: operands, an assembly string, and an instruction pattern. The specification contains a list of definitions or outputs and a list of uses or inputs. There can be different operand classes such as the register class, and immediate or more complex register + imm operands.
Here, a simple add instruction definition is demonstrated. It takes two registers for the input and one register for the output.
- Create a new file called
SAMPLEInstrInfo.tdin thelib/Target/SAMPLEfolder:$ vi SAMPLEInstrInfo.td - Specify the operands, assembly string, and instruction pattern for the add instruction between two register operands:
def ADDrr : InstSAMPLE<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), "add $dst, $src1, $src2", [(set i32:$dst, (add i32:$src1, i32:$src2))]>;
The add register instruction specifies $dst as the resultant operand, which belongs to the general register type class; the $src1 and $src2 inputs as two input operands, which also belong to the general register class; and the instruction assembly string as add $dst, $src1, $src2, which is of the 32-bit integer type.
So, an assembly will be generated for add between two registers, like this:
add r0, r0, r1
This tells us to add the r0 and r1 registers' content and store the result in the r0 register.
- For more detailed information on various types of instruction sets for advanced architecture, such as the x86, refer to the
X86InstrInfo.tdfile located atlib/Target/X86/ - Detailed information of how target-specific things are defined will be covered in Chapter 8, Writing an LLVM Backend. Some concepts might get repetitive, as the preceding recipes were described in brief to get a glimpse of the target architecture description and get a foretaste of the upcoming recipes