The instruction set of an architecture varies according to various features present in the architecture. This recipe demonstrates how instruction sets are defined for target architecture.
Three things are defined in the instruction target description file: operands, the assembly string and the instruction pattern. The specification contains a list of definitions or outputs, and a list of uses or inputs. There can be different operand classes, such as the Register class, and the immediate and more complex register + imm operands.
Here, a simple add instruction definition that takes two registers as operands is demonstrated.
To define an instruction set using target descriptor files, proceed with the following steps.
- Create a new file called
TOYInstrInfo.tdin thelib/Target/TOYfolder:$ vi TOYInstrInfo.td - Specify the operands, assembly string, and instruction pattern for the
addinstruction between two register operands:def ADDrr : InstTOY<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), "add $dst, $src1,z$src2", [(set i32:$dst, (add i32:$src1, i32:$src2))]>;
The add register to the register instruction specifies $dst as the result operand, which belongs to the General Register type class; inputs $src1 and $src2 as two input operands, which also belong to the General Register type class; and the instruction assembly string as "add $dst, $src1, $src2" of the 32-bit integer type.
So, an assembly will be generated for add between two registers, like this:
add r0, r0, r1
The preceding code indicates to add the r0 and r1 register contents and store the result in the r0 register.
- Many instructions will have the same type of instruction pattern—ALU instructions such as
add,sub, and so on. In cases such as this multiclass can be used to define the common properties. For more detailed information about the various types of instruction sets for advanced architecture, such as ARM, refer to thelib/Target/ARM/ARMInstrInfo.td file