Home Page Icon
Home Page
Table of Contents for
Title Page
Close
Title Page
by Pete Dice
Quick Boot
Cover
Title Page
Copyright
Contents
Chapter 1: System Firmware’s Missing Link
Start by Gathering Data
Initialization Roles and Responsibilities
System Firmware
OS Loader
Operating System
Legacy BIOS Interface, UEFI, and the Conversion
Tiano Benefits
Previous UEFI Challenges
Persistence of Change
The Next Generation
Commercial BIOS Business
Award
General Software
Phoenix Technologies Limited
American Megatrends Inc.
Insyde Software
ByoSoft
Value of BIOS
Proprietary Solutions
Making a Decision on Boot Firmware
Consider Using a BIOS Vendor
Consider Open-Source Alternatives
Consider Creating Something from Scratch
Consider a Native Boot Loader for Intel ® Architecture
Just Add Silicon Initialization
Summary
Chapter 2: Intel Architecture Basics
The Big Blocks of Intel Architecture
The CPU
The Front Side Bus
The North Bridge, PCIset, AGPset, MCH, Uncore, System Agent
The Transparent Link (Hublink, DMI, ESI)
The South Bridge, Also Known as the PIIX, I/O Controller Hub (ICH), I/O Hub (IOH), Enterprise South Bridge (ESB), and Platform Controller Hub (PCH)
Data Movement Is Fundamental
It’s a Multiprocessing System Architecture
The Memory Map
I/O Address Range
The Operating System
Summary
Chapter 3: System Firmware Terms and Concepts
Typical PC/Intel® Architecture Overview
Memory Types
Processor Cache
System Memory
Complementary Metal-Oxide Semiconductor (CMOS)
System BIOS Flash Memory (NVRAM, FWH, or SPI)
Real-Time Clock (RTC)
System Memory Map
Legacy Address Range
Main Memory Address Range
PCI Memory Address Range
Splash Screen
Status and Error Messages
Display Messages
Beep Codes
POST Codes
Master Boot Record
GUID Partition Table
Real Mode
Protected Mode
Logical Addressing
Flat Protected Mode
Reset Vector
Programmable Interrupt Controller
Advanced Programmable Interrupt Controller
The I/OxAPIC
The Local APIC
Summary
Chapter 4: Silicon-Specific Initialization
Listen to the Designer, Then Experiment, and Fix It
Chipsets
Processors
Basic Types of Initialization
Simple Bits
Standard Algorithms, Minding the Ps and Qs
Custom Algorithms: It’s All About Me
Option ROMs
Summary
Chapter 5: Industry Standard Initialization
PCI
PCI Device Enumeration
PCI BIOS
PCI IRQ Routing with ACPI Methods
PCI Recommendation
PCI Power Management
USB Enumeration and Initialization
PCI Enumeration and Initialization of USB Controllers
USB Wake from ACPI Sx (S3, S4, S5 to S0)
USB Enumeration
SATA
SATA Controller Initialization
Setting the SATA Controller Mode
Enabling SATA Ports
Setting the Programming Interface
Initializing Registers in AHCI Memory-Mapped Space
RAID Mode Initialization
Additional Programming Requirements During SATA Initialization
External SATA Programming
Compliance with Industry Specifications
Advanced Configuration and Power Interface (ACPI)
ACPI Tables
ACPI Namespace
Summary
Chapter 6: System Firmware Debug Techniques
Host/Target Debugging Techniques
Hardware Capabilities
POST Codes
Audio (Beep) Codes
Serial Port
In-Target Probe (ITP), a Form of JTAG Port
Software Debug Methods
Console Input/Output
Abstraction
Disable Optimization
Where Am I in the Firmware?
When Hardware Isn’t Stable, Where Do I Start?
Debugging Other People’s Code
Debugging PCI Option ROMs or Binary Libraries
Debugging Library Code (No Source)
Debugging Beyond Firmware
Real Mode Interrupts
System Management Mode
Industry Specifications
Pitfalls
Summary
Chapter 7: Shells and Native Applications
Pre-OS Shells
UEFI Shell Application
EFI/UEFI Script File
Different Features between Script and App
Customizing the UEFI Shell
Where to Get Shells
GUIs and the UEFI Shell
Remote Control of the UEFI Shell
Debugging Drivers and Applications in the EFI and UEFI Shells
The End for the Shell
Summary
Chapter 8: Loading an Operating System
The Boot Path
The Bus
The Device
The Partition Table
The File System
Booting via the Legacy OS Interface
Master Boot Record
Loading the Legacy OS Loader
Legacy BIOS to OS Handoff Requirements
Booting via the EFI Interface
Default EFI Boot Behavior
Direct Execution of a Linux Kernel
UEFI Runtime Services
Neither Option
Summary
Chapter 9: The Intel ® Architecture Boot Flow
Hardware Power Sequences (The Pre-Pre-Boot)
Nonhost-Based Subsystem Startup
Starting at the Host Reset Vector
Mode Selection
Early Initialization
Single-Threaded Operation
Simple Device Initialization
Memory Configuration
Post-Memory
Shadowing
Exit from No-Eviction Mode and Transfer to DRAM
Transfer to DRAM
Memory Transaction Redirection
Application Processor (AP) Initialization
Advanced Initialization
General Purpose I/O (GPIO) Configuration
Interrupt Controllers
Interrupt Vector Table (IVT)
Interrupt Descriptor Table (IDT)
Timers
Memory Caching Control
Serial Ports
Clock and Overclock Programming
PCI Device Enumeration
Graphics Initialization
Input Devices
USB Initialization
SATA Initialization
SATA Controller Initialization
Memory Map
Region Types
Region Locations
Loading the OS
Summary
Chapter 10: Bootstrapping Embedded
Optimization Using BIOS and Bootloaders
Platform Policy (What Is It and Why Is It Here?)
Case Study Summaries
Example 1
Example 2
Example 1 Details
What Are the Design Goals?
What Are the Supported Target Operating Systems?
Do We Have to Support Legacy Operating Systems?
Do We Have to Support Legacy Option ROMs?
Are We Required to Display an OEM Splash Screen?
What Type of Boot Media Is Supported?
What Is the BIOS Recovery/Update Strategy?
When Processing Things Early
Is There a Need for Pre-OS User Interaction?
A Note of Caution
Additional Details
Example 2 Details
Turn Off Debugging
Decrease Flash Size
Caching of PEI Phase
Intel SpeedStep® Technology Enabled Early
BDS Phase Optimization
Platform Memory Speed
Remove PS/2 Keyboard/Mouse
Remove BIOS Setup
Remove Video Option ROM
Remove BIOS USB Support
Divide Long Lead Pieces into Functional Blocks and Distribute Across the Boot Flow
Summary
Chapter 11: Intel’s Fast Boot Technology
The Human Factor
Responsiveness
The (Green) Machine Factor
Boot Time Analysis
First Boot versus Next Boot Concept
Boot Mode UEFI Configuration Setting
Fallback Mechanisms
Baseline Assumptions for Enabling Intel Fast Boot
Intel Fast Boot Timing Results
Summary
Chapter 12: Collaborative Roles in Quick Boot
Power Hardware Role
Power Sequencing
Power Supply Specification
Flash Subsystem
High Speed SPI Bus for Flash
Flash Component Accesses
SPI Prefetch and Buffer
SPI Flash Reads and Writes
Slow Interface and Device Access
DMI Optimizations
Processor Optimizations
CPU Turbo Enabling
Streamline CPU Reset and Initial CPU Microcode Update
Efficient APs Initialization
Caching Code and Data
Main Memory Subsystem
Memory Configuration Complexity
Fast and Safe Memory Initialization
Hardware-Based Memory Clearing
Efficient Memory Operations Instruction Usage
SMBus Optimizations (Which Applies to Memory Init)
Minimize BIOS Shadowing Size, Dual DXE Paths for Fast Path versus Full Boot
PCIe Port Disable Algorithm
Manageability Engine
Eliminating MEBx
Reducing Manageability Engine and BIOS Interactions
Graphics Subsystem
Graphics Device Selection
Graphics Output Protocol (GOP) Support for CSM-Free Operating Systems
Panel Specification
Start Panel Power Early
Storage Subsystems
Spinning Media
Utilizing Nonblocking Storage I/O
Early SATA COMRESETs: Drive Spin-Up
CSM-Free Intel® Raid Storage Technology (Intel RST) UEFI Driver
Minimizing USB Latency
Power Management
Minimizing Active State Power Management Impact
Security
Intel® Trusted Execution Technology (Intel TXT)
TPM Present Detect and Early Start
Operating System Interactions
Compatibility Segment Module and Legacy Option ROMs
OS Loader
Legacy OS Interface
Reducing Replication of Enumeration Between Firmware and OS
Other Factors Affecting Boot Speed
No Duplication in Hardware Enumeration within UEFI
Minimize Occurrences of Hardware Resets
Intel Architecture Coding Efficiency
Network Boot Feature
Value-Add, But Complex Features
Tools and the User Effect
Human Developer’s Resistance to Change
Summary
Chapter 13: Legal Decisions
Proprietary License
Berkeley Software Distribution (BSD) License
Key Four Clauses to the Original License
Three-Clause BSD
General Public License (GPL)
Lesser GPL (LGPL)
Separating and Segregating Code
Conclusion
Appendix A: Generating Serial Presence Detection Data for Down Memory Configurations
Analyzing the Design’s Memory Architecture
Calculating DIMM Equivalents
ECC Calculation
SDRAM Width Determination
SDRAM Chip Datasheet
SDRAM Architecture Analysis Example
Calculating Specific SPD Data Based on SDRAM Datasheet
SPD Field 0x00: Number of Bytes
SPD Field 0×01: SPD Revision
Byte 1: SPD Revision
SPD Field 0×02: Device Type
SPD Field 0×03: Module Type
SPD Field 0×04: SDRAM Density and Banks
SPD Field 0×05: SDRAM Rows and Columns
SPD Field 0×06: Nominal Voltage, VDD
SPD Field 0×07: Ranks & Device DQ Count
SPD Field 0×08: Module Bus Width
SPD Field 0×09: Fine Timebase Dividend/Divisor
SPD Field 0×0A and 0×0B: Medium Timebase Dividend/Divisor
SPD Field 0x0C: Cycle Time (tCKmin)
SPD Field 0×0E and 0×0F: CAS Latencies Supported
SPD Field 0×10: CAS Latency Time (tAAmin or tCL)
SPD Field 0×11: Write Recovery Time (twrmin)
SPD Field 0×12 RAS# to CAS# Delay (tRCDmin)
SPD Field 0x13: Min. Row Active to Row Active Delay (tRRDmin)
SPD Field 0×14: Min. Row Precharge Delay (tRPmin)
SPD Field 0×15: Upper Nibble of tRAS & tRC
SPD Field 0×16: Min. Active to Precharge Delay (tRASmin) LSB
SPD Field 0×17: Min. Active to Active Refresh Delay (tRCmin) LSB
SPD Field 0×18 and 0×19: Min. Refresh Recovery Delay (tRFCmin)
SPD Field 0×1A: Min. Write to Read Command Delay (tWTRmin)
SPD Field 0×1B: Min. Read to Precharge Command Delay (tRTPmin)
SPD Field 0×1C: tFAW Upper Nibble
SPD Field 0×1D: Min. Four Activate Window Delay (tFAWmin) LSB
SPD Field 0x1E: SDRAM Optional Features
SPD Field 0×1F: SDRAM Thermal and Refresh Options
SPD Field 0×20: Module Thermal Sensor
SPD Field 0x21: SDRAM Device Type
SPD Field 0×22–0×3B: Reserved
Module-Specific Section: Bytes 60–116
SPD Field 0×3C: (Unbuffered): Module Nominal Height
SPD Field 0×3D: (Unbuffered): Module Max. Thickness
SPD Field 0x3E: (Unbuffered): Reference Raw Card Used
SPD Field 0×3F: Unbuff Addr. Mapping from Edge Connector to DRAM
SPD Field 0×40-0×74: Reserved
SPD Field 0×75 and 0×76: Module Manufacturer ID Code, LSB
SPD Field 0×77: Module Manufacturer Location
SPD Field 0×78 and 0×79: Module Manufacturing Date
SPD Field 0x7A–0x7D: Module Serial Number
SPD Field 0×7E and 0×7F: CRC Bytes
Bytes 126–127: SPD Cyclical Redundancy Code (CRC)
SPD Field 0×80–0×91
SPD Field 0×92 and 0×93: Module Revision Code
SPD Field 0×94 and 0×95: DRAM Manufacturer ID Code
SPD Field 0×96–0×AF: Manufacturer’s Specific Data
SPD Field 0×B0–0×FF: Open for Customer Use
References for Appendix A
Index
Search in book...
Toggle Font Controls
Playlists
Add To
Create new playlist
Name your new playlist
Playlist description (optional)
Cancel
Create playlist
Sign In
Email address
Password
Forgot Password?
Create account
Login
or
Continue with Facebook
Continue with Google
Sign Up
Full Name
Email address
Confirm Email Address
Password
Login
Create account
or
Continue with Facebook
Continue with Google
Prev
Previous Chapter
Halftitle Page
Next
Next Chapter
Copyright
Add Highlight
No Comment
..................Content has been hidden....................
You can't read the all page of ebook, please click
here
login for view all page.
Day Mode
Cloud Mode
Night Mode
Reset