Contents
Chapter 1: System Firmware’s Missing Link
Initialization Roles and Responsibilities
Legacy BIOS Interface, UEFI, and the Conversion
Making a Decision on Boot Firmware
Consider Open-Source Alternatives
Consider Creating Something from Scratch
Consider a Native Boot Loader for Intel ® Architecture
Just Add Silicon Initialization
Chapter 2: Intel Architecture Basics
The Big Blocks of Intel Architecture
The North Bridge, PCIset, AGPset, MCH, Uncore, System Agent
The Transparent Link (Hublink, DMI, ESI)
It’s a Multiprocessing System Architecture
Chapter 3: System Firmware Terms and Concepts
Typical PC/Intel® Architecture Overview
Complementary Metal-Oxide Semiconductor (CMOS)
System BIOS Flash Memory (NVRAM, FWH, or SPI)
Programmable Interrupt Controller
Advanced Programmable Interrupt Controller
Chapter 4: Silicon-Specific Initialization
Listen to the Designer, Then Experiment, and Fix It
Standard Algorithms, Minding the Ps and Qs
Custom Algorithms: It’s All About Me
Chapter 5: Industry Standard Initialization
PCI IRQ Routing with ACPI Methods
USB Enumeration and Initialization
PCI Enumeration and Initialization of USB Controllers
USB Wake from ACPI Sx (S3, S4, S5 to S0)
SATA Controller Initialization
Setting the SATA Controller Mode
Setting the Programming Interface
Initializing Registers in AHCI Memory-Mapped Space
Additional Programming Requirements During SATA Initialization
Compliance with Industry Specifications
Advanced Configuration and Power Interface (ACPI)
Chapter 6: System Firmware Debug Techniques
Host/Target Debugging Techniques
In-Target Probe (ITP), a Form of JTAG Port
When Hardware Isn’t Stable, Where Do I Start?
Debugging PCI Option ROMs or Binary Libraries
Debugging Library Code (No Source)
Chapter 7: Shells and Native Applications
Different Features between Script and App
Remote Control of the UEFI Shell
Debugging Drivers and Applications in the EFI and UEFI Shells
Chapter 8: Loading an Operating System
Booting via the Legacy OS Interface
Legacy BIOS to OS Handoff Requirements
Direct Execution of a Linux Kernel
Chapter 9: The Intel ® Architecture Boot Flow
Hardware Power Sequences (The Pre-Pre-Boot)
Nonhost-Based Subsystem Startup
Starting at the Host Reset Vector
Exit from No-Eviction Mode and Transfer to DRAM
Memory Transaction Redirection
Application Processor (AP) Initialization
General Purpose I/O (GPIO) Configuration
Interrupt Descriptor Table (IDT)
Clock and Overclock Programming
SATA Controller Initialization
Chapter 10: Bootstrapping Embedded
Optimization Using BIOS and Bootloaders
Platform Policy (What Is It and Why Is It Here?)
What Are the Supported Target Operating Systems?
Do We Have to Support Legacy Operating Systems?
Do We Have to Support Legacy Option ROMs?
Are We Required to Display an OEM Splash Screen?
What Type of Boot Media Is Supported?
What Is the BIOS Recovery/Update Strategy?
Is There a Need for Pre-OS User Interaction?
Intel SpeedStep® Technology Enabled Early
Divide Long Lead Pieces into Functional Blocks and Distribute Across the Boot Flow
Chapter 11: Intel’s Fast Boot Technology
First Boot versus Next Boot Concept
Boot Mode UEFI Configuration Setting
Baseline Assumptions for Enabling Intel Fast Boot
Intel Fast Boot Timing Results
Chapter 12: Collaborative Roles in Quick Boot
Slow Interface and Device Access
Streamline CPU Reset and Initial CPU Microcode Update
Memory Configuration Complexity
Fast and Safe Memory Initialization
Hardware-Based Memory Clearing
Efficient Memory Operations Instruction Usage
SMBus Optimizations (Which Applies to Memory Init)
Minimize BIOS Shadowing Size, Dual DXE Paths for Fast Path versus Full Boot
Reducing Manageability Engine and BIOS Interactions
Graphics Output Protocol (GOP) Support for CSM-Free Operating Systems
Utilizing Nonblocking Storage I/O
Early SATA COMRESETs: Drive Spin-Up
CSM-Free Intel® Raid Storage Technology (Intel RST) UEFI Driver
Minimizing Active State Power Management Impact
Intel® Trusted Execution Technology (Intel TXT)
TPM Present Detect and Early Start
Compatibility Segment Module and Legacy Option ROMs
Reducing Replication of Enumeration Between Firmware and OS
Other Factors Affecting Boot Speed
No Duplication in Hardware Enumeration within UEFI
Minimize Occurrences of Hardware Resets
Intel Architecture Coding Efficiency
Value-Add, But Complex Features
Human Developer’s Resistance to Change
Berkeley Software Distribution (BSD) License
Key Four Clauses to the Original License
Separating and Segregating Code
Appendix A: Generating Serial Presence Detection Data for Down Memory Configurations
Analyzing the Design’s Memory Architecture
SDRAM Architecture Analysis Example
Calculating Specific SPD Data Based on SDRAM Datasheet
SPD Field 0x00: Number of Bytes
SPD Field 0×04: SDRAM Density and Banks
SPD Field 0×05: SDRAM Rows and Columns
SPD Field 0×06: Nominal Voltage, VDD
SPD Field 0×07: Ranks & Device DQ Count
SPD Field 0×08: Module Bus Width
SPD Field 0×09: Fine Timebase Dividend/Divisor
SPD Field 0×0A and 0×0B: Medium Timebase Dividend/Divisor
SPD Field 0x0C: Cycle Time (tCKmin)
SPD Field 0×0E and 0×0F: CAS Latencies Supported
SPD Field 0×10: CAS Latency Time (tAAmin or tCL)
SPD Field 0×11: Write Recovery Time (twrmin)
SPD Field 0×12 RAS# to CAS# Delay (tRCDmin)
SPD Field 0x13: Min. Row Active to Row Active Delay (tRRDmin)
SPD Field 0×14: Min. Row Precharge Delay (tRPmin)
SPD Field 0×15: Upper Nibble of tRAS & tRC
SPD Field 0×16: Min. Active to Precharge Delay (tRASmin) LSB
SPD Field 0×17: Min. Active to Active Refresh Delay (tRCmin) LSB
SPD Field 0×18 and 0×19: Min. Refresh Recovery Delay (tRFCmin)
SPD Field 0×1A: Min. Write to Read Command Delay (tWTRmin)
SPD Field 0×1B: Min. Read to Precharge Command Delay (tRTPmin)
SPD Field 0×1C: tFAW Upper Nibble
SPD Field 0×1D: Min. Four Activate Window Delay (tFAWmin) LSB
SPD Field 0x1E: SDRAM Optional Features
SPD Field 0×1F: SDRAM Thermal and Refresh Options
SPD Field 0×20: Module Thermal Sensor
SPD Field 0x21: SDRAM Device Type
Module-Specific Section: Bytes 60–116
SPD Field 0×3C: (Unbuffered): Module Nominal Height
SPD Field 0×3D: (Unbuffered): Module Max. Thickness
SPD Field 0x3E: (Unbuffered): Reference Raw Card Used
SPD Field 0×3F: Unbuff Addr. Mapping from Edge Connector to DRAM
SPD Field 0×75 and 0×76: Module Manufacturer ID Code, LSB
SPD Field 0×77: Module Manufacturer Location
SPD Field 0×78 and 0×79: Module Manufacturing Date
SPD Field 0x7A–0x7D: Module Serial Number
SPD Field 0×7E and 0×7F: CRC Bytes
Bytes 126–127: SPD Cyclical Redundancy Code (CRC)
SPD Field 0×92 and 0×93: Module Revision Code
SPD Field 0×94 and 0×95: DRAM Manufacturer ID Code
SPD Field 0×96–0×AF: Manufacturer’s Specific Data