Following our system- and architecture-level studies in previous chapters, we move farther down to the circuit level in this and subsequent chapters. Beginning with the receive path, we describe the design of low-noise amplifiers. While our focus is on CMOS implementations, most of the concepts can be applied to other technologies as well. The outline of the chapter is shown below.

As the first active stage of receivers, LNAs play a critical role in the overall performance and their design is governed by the following parameters.

The noise figure of the LNA directly adds to that of the receiver. For a typical RX noise figure of 6 to 8 dB, it is expected that the antenna switch or duplexer contributes about 0.5 to 1.5 dB, the LNA about 2 to 3 dB, and the remainder of the chain about 2.5 to 3.5 dB. While these values provide a good starting point in the receiver design, the exact partitioning of the noise is flexible and depends on the performance of each stage in the chain. In modern RF electronics, we rarely design an LNA in isolation. Rather, we view and design the RF chain as one entity, performing many iterations among the stages.

To gain a better feel for a noise figure of 2 dB, consider the simple example in Fig. 5.1(a), where the noise of the LNA is represented by only a voltage source. Rearranging the input network as shown in Fig. 5.1(b), we have from Chapter 2

Thus, a noise figure of 2 dB with respect to a source impedance of 50Ω translates to , an extremely low value. For the gate-referred thermal noise voltage of a MOSFET, 4*kTγ*/*g _{m}*, to reach this value, the

The low noise required of LNAs limits the choice of the circuit topology. This often means that *only one transistor*—usually the input device—can be the dominant contributor to NF, thus ruling out configurations such as emitter or source followers.

The gain of the LNA must be large enough to minimize the noise contribution of subsequent stages, specifically, the downconversion mixer(s). As described in Chapter 2, the choice of this gain leads to a compromise between the noise figure and the linearity of the receiver as a higher gain makes the nonlinearity of the subsequent stages more pronounced. In modern RF design, the LNA directly drives the downconversion mixer(s) with no impedance matching between the two. Thus, it is more meaningful and simpler to perform the chain calculations in terms of the voltage gain—rather than power gain—of the LNA.

It is important to note that the noise and IP_{3} of the stage following the LNA are divided by *different* LNA gains. Consider the LNA/mixer cascade shown in Fig. 5.3(a), where the input-referred noise voltages are denoted by and and input noise currents are neglected. Assuming a unity voltage gain for the mixer for simplicity, we write the total output noise as . The overall noise figure is thus equal to

In other words, for NF calculations, the noise of the second stage is divided by the gain from the input voltage source to the LNA output.

Now consider the same cascade repeated in Fig. 5.3(b) with the nonlinearity of the LNA expressed as a third-order polynomial. From Chapter 2, we have^{1}

In this case, *α*_{1} denotes the voltage gain from the *input of the LNA* to its output. With input matching, we have *R _{in}* =

The interface between the antenna and the LNA entails an interesting issue that divides analog designers and microwave engineers. Considering the LNA as a *voltage* amplifier, we may expect that its input impedance must ideally be infinite. From the noise point of view, we may precede the LNA with a transformation network to obtain minimum NF. From the signal *power* point of view, we may realize *conjugate* matching between the antenna and the LNA. Which one of these choices is preferable?

We make the following observations. (1) the (off-chip) band-select filter interposed between the antenna and the LNA is typically designed and characterized as a high-frequency device and with a standard termination of 50Ω. If the load impedance seen by the filter (i.e., the LNA input impedance) deviates from 50Ω significantly, then the pass-band and stopband characteristics of the filter may exhibit loss and ripple. (2) Even in the absence of such a filter, the antenna itself is designed for a certain real load impedance, suffering from uncharacterized loss if its load deviates from the desired real value or contains an imaginary component. Antenna/LNA co-design could improve the overall performance by allowing even non-conjugate matching, but it must be borne in mind that, if the antenna is shared with the transmitter, then its impedance must contain a negligible imaginary part so that it *radiates* the PA signal. (3) In practice, the antenna signal must travel a considerable distance on a printed-circuit board before reaching the receiver. Thus, poor matching at the RX input leads to significant reflections, an uncharacterized loss, and possibly voltage attenuation. For these reasons, the LNA is designed for a 50-Ω resistive input impedance. Since none of the above concerns apply to the other interfaces within the RX (e.g., between the LNA and the mixer or between the LO and the mixer), they are typically designed to maximize *voltage* swings rather than power transfer.

The quality of the input match is expressed by the input “return loss,” defined as the reflected power divided by the incident power. For a source impedance of *R _{S}*, the return loss is given by

where *Z _{in}* denotes the input impedance. An input return loss of −10 dB signifies that one-tenth of the power is reflected—a typically acceptable value. Figure 5.4 plots contours of constant Γ in the

Unlike the other circuits in a receiver, the LNA must interface with the “outside world,” specifically, a poorly-controlled source impedance. For example, if the user of a cell phone wraps his/her hand around the antenna, the antenna impedance changes.^{3} For this reason, the LNA must remain stable for all source impedances at *all frequencies*. One may think that the LNA must operate properly only in the frequency band of interest and not necessarily at other frequencies, but if the LNA begins to oscillate at any frequency, it becomes highly nonlinear and its gain is very heavily compressed.

A parameter often used to characterize the stability of circuits is the “Stern stability factor,” defined as

where Δ = *S*_{11}*S*_{22} − *S*_{12}*S*_{21}. If *K >* 1 and Δ *<* 1, then the circuit is unconditionally stable, i.e., it does not oscillate with any combination of *source* and *load* impedances. In modern RF design, on the other hand, the load impedance of the LNA (the input impedance of the on-chip mixer) is relatively well-controlled, making *K* a pessimistic measure of stability. Also, since the LNA output is typically not matched to the input of the mixer, *S*_{22} is not a meaningful quantity in such an environment.

The above example suggests that LNAs can be stabilized by maximizing their reverse isolation. As explained in Section 5.3, this point leads to two robust LNA topologies that are naturally stable and hence can be optimized for other aspects of their performance with no stability concerns. A high reverse isolation is also necessary for suppressing the LO leakage to the input of the LNA.

LNAs may become unstable due to ground and supply parasitic inductances resulting from the packaging (and, at frequencies of tens of gigahertz, the on-chip line inductances). For example, if the gate terminal of a common-gate transistor sees a large series inductance, the circuit may suffer from substantial feedback from the output to the input and become unstable at some frequency. For this reason, precautions in the design and layout as well as accurate package modeling are essential.

In most applications, the LNA does not limit the linearity of the receiver. Owing to the cumulative gain through the RX chain, the latter stages, e.g., the baseband amplifiers or filters tend to limit the overall input IP_{3} or *P*_{1dB}. We therefore design and optimize LNAs with little concern for their linearity.

An exception to the above rule arises in “full-duplex” systems, i.e., applications that transmit and receive simultaneously (and hence incorporate FDD). Exemplified by the CDMA systems studied in Chapter 3, full-duplex operation must deal with the leakage of the strong transmitted signal to the receiver. To understand this issue, let us consider the front end shown in Fig. 5.5, where a duplexer separates the TX and RX bands. Modeling the duplexer as a three-port network, we note that *S*_{31} and *S*_{21} represent the losses in the RX and TX paths, respectively, and are about 1 to 2 dB. Unfortunately, leakages through the filter and the package yield a finite isolation between ports 2 and 3, as characterized by an *S*_{32} of about −50 dB. In other words, if the PA produces an average output power of +30 dBm (1 W), then the LNA experiences a signal level of −20 dBm in the TX band while sensing a much smaller received signal. Since the TX signal exhibits a variable envelope, its peak level may be about 2 dB higher. Thus, the receiver must remain uncompressed for an input level of −18 dBm. We must therefore choose a *P*_{1dB} of about −15 dBm to allow some margin.

Such a value for *P*_{1dB} may prove difficult to realize in a receiver. With an LNA gain of 15 to 20 dB, an input of −15 dBm yields an output of 0 to +5 dBm (632 to 1124 mV* _{pp}*), possibly compressing the LNA at

The linearity of the LNA also becomes critical in wideband receivers that may sense a large number of strong interferers. Examples include “ultra-wideband” (UBW), “software-defined,” and “cognitive” radios.

The LNA must provide a relatively flat response for the frequency range of interest, preferably with less than 1 dB of gain variation. The LNA −3-dB bandwidth must therefore be substantially larger than the actual band so that the roll-off at the edges remains below 1 dB.

In order to quantify the difficulty in achieving the necessary bandwidth in a circuit, we often refer to its “fractional bandwidth,” defined as the total −3-dB bandwidth divided by the center frequency of the band. For example, an 802.11g LNA requires a fractional bandwidth greater than 80 MHz/2.44 GHz = 0.0328.

LNA designs that must achieve a relatively large fractional bandwidth may employ a mechanism to *switch* the center frequency of operation. Depicted in Fig. 5.7(a) is an example, where an additional capacitor, *C*_{2}, can be switched into the tank, thereby changing the center frequency from to [Fig. 5.7(b)]. We return to this concept in Section 5.5.

The LNA typically exhibits a direct trade-off among noise, linearity, and power dissipation. Nonetheless, in most receiver designs, the LNA consumes only a small fraction of the overall power. In other words, the circuit’s noise figure generally proves much more critical than its power dissipation.

As explained in Section 5.1, LNAs are typically designed to provide a 50-Ω input resistance and negligible input reactance. This requirement limits the choice of LNA topologies. In other words, we cannot begin with an arbitrary configuration, design it for a certain noise figure and gain, and then decide how to create input matching.

Let us first consider the simple common-source stage shown in Fig. 5.8, where *C _{F}* represents the gate-drain overlap capacitance. At very low frequencies,

Is it possible to select the circuit parameters so as to obtain *Re*{*Y _{in}*} = 1/(50Ω)? For example, if

Can we employ simple resistive termination at the input? Illustrated in Fig. 5.9(a), such a topology is designed in three steps: (1) *M*_{1} and *R _{D}* provide the required noise figure and gain, (2)

where channel-length modulation is neglected. Since the voltage gain from *V _{in}* to

For *R _{P}* ≈

The key point in the foregoing study is that the LNA must provide a 50-Ω input resistance *without* the thermal noise of a physical 50-Ω resistor. This becomes possible with the aid of active devices.

In summary, proper input (conjugate) matching of LNAs requires certain circuit techniques that yield a real part of 50Ω in the input impedance without the noise of a 50-Ω resistor. We study such techniques in the next section.

Our preliminary studies thus far suggest that the noise figure, input matching, and gain constitute the principal targets in LNA design. In this section, we present a number of LNA topologies and analyze their behavior with respect to these targets. Table 5.1 provides an overview of these topologies.

As noted in Section 5.1, a CS stage with resistive load (Fig. 5.8) proves inadequate because it does not provide proper matching. Furthermore, the output node time constant may prohibit operation at high frequencies. In general, the trade-off between the voltage gain and the supply voltage in this circuit makes it less attractive as the latter scales down with technology. For example, at low frequencies,

where *V _{RD}* denotes the dc voltage drop across

In order to circumvent the trade-off expressed by Eq. (5.29) and also operate at higher frequencies, the CS stage can incorporate an inductive load. Illustrated in Fig. 5.11(a), such a topology operates with very low supply voltages because the inductor sustains a smaller dc voltage drop than a resistor does. (For an ideal inductor, the dc drop is zero.) Moreover, *L*_{1} resonates with the total capacitance at the output node, affording a much higher operation frequency than does the resistively-loaded counterpart of Fig. 5.8.

How about the input matching? We consider the more complete circuit shown in Fig. 5.11(b), where *C _{F}* denotes the gate-drain overlap capacitance. Ignoring the gate-source capacitance of

and the tank voltage by (*I _{X}* −

Substitution of *Z _{T}* from (5.30) gives

For *s* = *jω*,

Since the real part of a complex fraction (*a* + *jb*)/(*c* + *jd*) is equal to (*ac* + *bd*)/(*c*^{2} + *d*^{2}), we have

where *D* is a positive quantity. It is thus possible to select the values so as to obtain *Re*{*Z _{in}*} = 50Ω.

While providing the possibility of *Re*{*Z _{in}*} = 50Ω at the frequency of interest, the feedback capacitance in Fig. 5.11(b) gives rise to a

We note that the numerator falls to zero at a frequency given by

Thus, at this frequency (if it exists), *Re*{*Z _{in}*} changes sign. For example, if

It is possible to “neutralize” the effect of *C _{F}* in some frequency range through the use of parallel resonance (Fig. 5.12), but, since

If the frequency of operation remains an order of magnitude lower than the *f _{T}* of the transistor, the feedback CS stage depicted in Fig. 5.13(a) may be considered as a possible candidate. Here,

If channel-length modulation is neglected, we have from Fig. 5.13(b),

because *R _{F}* is simply in series with an ideal current source and

Figure 5.13(b) also implies that the small-signal drain current of *M*_{1}, *g _{m}*

and hence

In practice, *R _{F}*

In contrast to the resistively-loaded CS stage of Fig. 5.8, this circuit does not suffer from a direct trade-off between gain and supply voltage because *R _{F}* carries no bias current.

Let us determine the noise figure of the circuit, assuming that *g _{m}*

The noise currents of *M*_{1} and *M*_{2} flow through the output impedance of the circuit, *R _{out}*, as shown in Fig. 5.14(b). The reader can prove that

The noise of *R _{S}* is multiplied by the gain when referred to the output, and the result is divided by the gain when referred to the input. We thus have

For *γ* ≈ 1, the NF exceeds 3 dB even if 4*R _{S}*/

The low input impedance of the common-gate (CG) stage makes it attractive for LNA design. Since a resistively-loaded stage suffers from the same gain-headroom trade-off as its CS counterpart, we consider only a CG circuit with inductive loading [Fig. 5.16(a)]. Here, *L*_{1} resonates with the total capacitance at the output node (including the input capacitance of the following stage), and *R*_{1} represents the loss of *L*_{1}. If channel-length modulation and body effect are neglected, *R _{in}* = 1/

and hence *V _{out}*/

Let us now determine the noise figure of the circuit under the condition *g _{m}* = 1/

The output noise due to *R*_{1} is simply equal to 4*kTR*_{1}. To obtain the noise figure, we divide the output noise due to *M*_{1} and *R*_{1} by the gain and 4*kTR _{S}* and add unity to the result:

Even if 4*R _{S}*/

In deep-submicron CMOS technologies, channel-length modulation significantly impacts the behavior of the CG stage. As shown in Fig. 5.19, the positive feedback through *r _{O} raises* the input impedance. Since the drain-source current of

That is,

If the intrinsic gain, *g _{m}r_{O}*, is much greater than unity, then

With the strong effect of *R*_{1} on *R _{in}*, we must equate the actual input resistance to

The reader can prove that the voltage gain of the CG stage shown in Fig. 5.16(a) with a finite *r _{O}* is expressed as

which, from Eq. (5.65), reduces to

This is a disturbing result! If *r _{O}* and

In summary, the input impedance of the CG stage is too low if channel-length modulation is neglected and too high if it is not! A number of circuit techniques have been introduced to deal with the former case (Section 5.3.5), but in today’s technology, we face the latter case.

In order to alleviate the above issue, the channel length of the transistor can be increased, thus reducing channel-length modulation and raising the achievable *g _{m}r_{O}*. Since the device width must also increase proportionally so as to retain the transconductance value, the gate-source capacitance of the transistor rises considerably, degrading the input return loss.

An alternative approach to lowering the input impedance is to incorporate a cascode device as shown in Fig. 5.21. Here, the resistance seen looking into the source of *M*_{2} is given by Eq. (5.64):

This load resistance is now transformed to a lower value by *M*_{1}, again according to (5.64):

If *g _{m}r_{O}* 1, then

Since *R*_{1} is divided by the product of two intrinsic gains, its effect remains negligible. Similarly, the third term is much less than the first if *g _{m}*

The addition of the cascode device entails two issues: the noise contribution of *M*_{2} and the voltage headroom limitation due to stacking two transistors. To quantify the former, we consider the equivalent circuit shown in Fig. 5.22(a), where *R _{S}* ( = 1/

Figure 5.22(b) plots the frequency response, implying that the noise contribution of *M*_{2} is negligible for frequencies up to the zero frequency, (2*r _{O}*

The second issue stemming from the cascode device relates to the limited voltage headroom. To quantify this limitation, let us determine the required or allowable values of *V _{b}*

It may appear that, so long as *V _{DD} > V_{GS}*

In order to avoid the noise-headroom trade-off imposed by *R _{B}*, and also cancel the input capacitance of the circuit, CG stages often employ an inductor for the bias path. Illustrated in Fig. 5.24 with proper biasing for the input transistor, this technique minimizes the additional noise due to the biasing element (

With so many devices present in the circuit of Fig. 5.24, how do we begin the design? We describe a systematic procedure that provides a “first-order” design, which can then be refined and optimized.

The design procedure begins with two knowns: the frequency of operation and the supply voltage. In the first step, the dimensions and bias current of *M*_{1} must be chosen such that a transconductance of (50Ω)^{−1} is obtained. The length of the transistor is set to the minimum allowable by the technology, but how should the width and the drain current be determined?

Using circuit simulations, we plot the transconductance and *f _{T}* of an NMOS transistor with a given width,

With *W*_{0} and *I _{D}*

In the second step, we compute the necessary value of *L _{B}* in Fig. 5.24. As shown in Fig. 5.26, the input of the circuit sees a pad capacitance to the substrate.

Does *L _{B}* affect the performance of the circuit at resonance? Accompanying

In the third step, the bias of *M*_{1} is defined by means of *M _{B}* and

Next, the width of *M*_{2} in Fig. 5.24 must be chosen (the length is the minimum allowable value). With the bias current known (*I _{D}*

In order to minimize the capacitance at node *X* in Fig. 5.24, transistors *M*_{1} and *M*_{2} can be laid out such that the drain area of the former is shared with the source area of the latter. Furthermore, since no other connection is made to this node, the shared area need not accommodate contacts and can therefore be minimized. Depicted in Fig. 5.27 and feasible only if *W*_{1} = *W*_{2}, such a structure can be expanded to one with multiple gate fingers.

In the last step, the value of the load inductor, *L*_{1}, must be determined (Fig. 5.24). In a manner similar to the choice of *L _{B}*, we compute

The design procedure outlined above leads to a noise figure around 3 dB [Eq. (5.58)] and a voltage gain, *V _{out}*/

Our study of the CS stage of Fig. 5.11(a) indicates that the feedback through the gate-drain capacitance many be exploited to produce the required real part, but it also leads to a negative resistance at lower frequencies. We must therefore seek a topology in which the input is “isolated” from the inductive load *and* the input resistance is established by means other than *C _{GD}*.

Let us first develop the latter concept. As mentioned in Section 5.2, we must employ active devices to provide a 50-Ω input resistance without the noise of a 50-Ω resistor. One such method employs a CS stage with inductive degeneration, as shown in Fig. 5.31(a). We first compute the input impedance of the circuit while neglecting *C _{GD}* and

Since *V _{X}* =

Interestingly, the input impedance contains a frequency-independent real part given by *g _{m}L*

The third term in Eq. (5.77) carries a profound meaning: since *g _{m}*/

In practice, the degeneration inductor is often realized as a bond wire with the reasoning that the latter is inevitable in packaging and must be incorporated in the design. To minimize the inductance, a “downbond” can directly connect the source pad to a ground plane in the package [Fig. 5.31(b)], but even this geometry yields a value in the range of 0.5 to 1 nH—far from the 50-pH amount calculated above! That is, the input resistance provided by modern MOSFETs tends to be substantially higher than 50Ω if a bond wire inductance is used.^{10}

How do we obtain a 50-Ω resistance with *L*_{1} ≈ 0.5 nH? At operation frequencies far below *f _{T}* of the transistor, we can

In addition to *C _{GD}*, the input pad capacitance of the circuit also lowers the input resistance. To formulate this effect, we construct the equivalent circuit shown in Fig. 5.33(a), where

We now merge the two parallel reactances into *jX*_{1}*X*_{2}/(*X*_{1} + *X*_{2}) and transform the resulting circuit to a series combination [Fig. 5.33(c)], where

In most cases, we can assume *L*_{1}*ω* 1/(*C _{GS}*

For example, if *C _{GS}*

We can now make two observations. First, the effect of the gate-drain and pad capacitance suggests that the transistor *f _{T}* need not be reduced so much as to create

Let us now compute the noise figure of the CS circuit, excluding the effect of channel-length modulation, body effect, *C _{GD}*, and

Also, since *L*_{1} sustains a voltage of *L*_{1}*s*(*I _{out}* +

Substituting for *V*_{1} from (5.86) gives

The input network is designed to resonate at the frequency of interest, *ω*_{0}. That is, and hence, (*L*_{1} + *L _{G}*)

The coefficient of *I _{out}* represents the transconductance gain of the circuit (including

Now, recall from Eq. (5.77) that, for input matching, *g _{m}L*

Interestingly, the transconductance of the circuit remains independent of *L*_{1}, *L _{G}*, and

Setting *V _{in}* to zero in Eq. (5.89), we compute the output noise due to

which, for *g _{m}L*

and hence

Dividing the output noise current by the transconductance of the circuit and by 4*kTR _{S}* and adding unity to the result, we arrive at the noise figure of the circuit [2]:

It is important to bear in mind that this result holds only at the input resonance frequency and if the input is matched.

The above example suggests that maximizing *L _{G}* can minimize the noise figure by providing voltage

Note that *L _{G}ω*

We now turn our attention to the output node of the circuit. As explained in Section 5.3.1, an inductive load attached to a common-source stage introduces a negative resistance due to the feedback through *C _{GD}*. We therefore add a cascode transistor in the output branch to suppress this effect. Figure 5.37 shows the resulting circuit, where

The effect of *C _{GD}*

Using the transconductance expression in (5.90) and *V _{G}*/

Since *R _{S}*

In the foregoing noise figure calculation, we have not included the noise contribution of *M*_{2}. As formulated for the cascode CG stage in Section 5.3.3, the noise of the cascode device begins to manifest itself if the frequency of operation exceeds roughly (2*r _{O}*

Having developed a good understanding of the cascode CS LNA of Fig. 5.37, we now describe a procedure for designing the circuit. The reader is encouraged to review the CG design procedure. The procedure begins with four knowns: the frequency of operation, *ω*_{0}, the value of the degeneration inductance, *L*_{1}, the input pad capacitance, *C _{pad}*, and the value of the input series inductance,

Governing the design are the following equations:

With *ω*_{0} known, *C _{GS}*

In the next step, the dimensions of the cascode device are chosen equal to those of the input transistor. As mentioned in Section 5.3.3 for the cascode CG stage, the width of the cascode device only weakly affects the performance. Also, the layout of *M*_{1} and *M*_{2} can follow the structure shown in Fig. 5.27 to minimize the capacitance at node *X*.

The design procedure now continues with selecting a value for *L _{D}* such that it resonates at

In the last step of the design, we must examine the input match. Due to the Miller multiplication of *C _{GD}*

The foregoing procedure typically leads to a design with a relatively low noise figure, around 1.5 to 2 dB—depending on how large *L _{G}* can be without displaying excessive parasitic capacitances. Alternatively, the design procedure can begin with known values for NF and

where the noise of the cascode transistor and the load is neglected. The necessary values of *ω _{T}* and

The overall LNA appears as shown in Fig. 5.38, where the antenna is capacitively tied to the receiver to isolate the LNA bias from external connections. The bias current of *M*_{1} is established by *M _{B}* and

The choice between the CG and CS LNA topologies is determined by the trade-off between the robustness of the input match and the lower bound on the noise figure. The former provides an accurate input resistance that is relatively independent of package parasitics, whereas the latter exhibits a lower noise figure. We therefore select the CG stage if the required LNA noise figure can be around 4 dB, and the CS stage for lower values.

An interesting point of contrast between the CG and CS LNAs relates to the contribution of the load resistor, *R*_{1}, to the noise figure. Equation (5.58) indicates that in a CG stage, this contribution, 4*R _{S}*/

As revealed by Eq. (5.57), the noise figure and input matching of the CG stage are inextricably related if channel-length modulation is negligible, a common situation in older CMOS technologies. For this reason, a number of efforts have been made to add another degree of freedom to the design so as to avoid this relationship. In this section, we describe two such examples.

Figure 5.43 shows a topology incorporating voltage-voltage feedback [3].^{13} The block having a gain (or attenuation factor) of *α* senses the output voltage and subtracts a fraction thereof from the input. (Note that *M*_{1} operates as a subtractor because *I _{D}*

At resonance,

The input resistance can therefore be substantially *higher* than 1/*g _{m}*, but how about the noise figure? We first calculate the gain with the aid of the circuit depicted in Fig. 5.44(a). The voltage gain from

which reduces to *R*_{1}/(2*R _{S}*) if the input is matched.

For output noise calculation, we construct the circuit of Fig. 5.44(b), where *V _{n}*

The noise current of *R*_{1} is multiplied by the output impedance of the circuit, *R _{out}*. The reader can show that

That is, the NF can be lowered by raising *g _{m}*. Note that this result is identical to that expressed by Eq. (5.57) for the simple CG stage, except that

Another variant of the CG LNA employs *feedforward* to avoid the tight relationship between the input resistance and the noise figure [4]. Illustrated in Fig. 5.45(a), the idea is to amplify the input by a factor of −*A* and apply the result to the gate of *M*_{1}. For an input voltage change of Δ*V*, the gate-source voltage changes by −(1 + *A*)Δ*V* and the drain current by −(1 + *A*)*g _{m}*Δ

We now compute the noise figure with the aid of the equivalent circuit shown in Fig. 5.45(b). Since the current flowing through *R _{S}* is equal to −

and hence

This expression reduces to −*g _{m}R*

This equation reveals that the NF can be lowered by raising *A* with the constraint (for input matching).

The above analysis has neglected the noise of the gain stage *A* in Fig. 5.45(a). We show in Problem 5.17 that the input-referred noise of this stage, , is multiplied by *A* and added to *V _{n}*

In other words, is referred to the input by a factor of *A*^{2}/(1 + *A*)^{2}, which is not much less than unity. For this reason, it is difficult to realize *A* by an active circuit.

It is possible to obtain the voltage gain through the use of an on-chip transformer. As shown in Fig. 5.46 [4], for a coupling factor of *k* between the primary and the secondary and a turns ratio of , the transformer provides a voltage gain of *kn*. The direction of the currents is chosen so as to yield a negative sign. However, on-chip transformer geometries make it difficult to achieve a voltage gain higher than roughly 3, even with stacked spirals [5]. Also, the loss in the primary and secondary contributes noise.

In our previous derivations of the noise figure of LNAs, we have observed three terms: a value of unity arising from the noise of *R _{S}* itself, a term representing the contribution of the input transistor, and another related to the noise of the load resistor. “Noise-cancelling LNAs” aim to cancel the second term [6]. The underlying principle is to identify

The CS stage with resistive feedback studied in Section 5.3.2 serves as a good candidate for noise cancellation because, as shown in Fig. 5.48(a), the noise current of *M*_{1} flows through *R _{F}* and

if the input is matched. The gain *V _{out}*/

Let us now compute the noise figure of the circuit, assuming that the auxiliary amplifier exhibits an input-referred noise voltage *V _{nA}*

Since *A*_{1} = 1 + *R _{F}*/

The NF can therefore be minimized by maximizing *R _{F}* and minimizing . Note that

The input capacitance, *C _{in}*, arising from

where NF(0) is given by (5.128) and *f*_{0} = 1/(*πR _{S}C_{in}*).

Figure 5.49 depicts an implementation of the circuit [6]. Here, *M*_{2} and *M*_{3} serve as a CS amplifier, providing a voltage gain of *g _{m}*

The principal advantage of the above noise cancellation technique is that it affords the broadband characteristics of feedback or CG stages but with a lower noise figure. It is therefore suited to systems operating in different frequency bands or across a wide frequency range, e.g., 900 MHz to 5 GHz.

It is possible to devise an LNA topology that inherently cancels the effect of its own input capacitance. Illustrated in Fig. 5.51(a) [7], the idea is to exploit the inductive input impedance of a negative-feedback amplifier so as to cancel the input capacitance, *C _{in}*. If the open-loop transfer function of the core amplifier is modeled by a one-pole response,

At frequencies well below *ω*_{0}, 1/*Re*{*Y*_{1}} reduces to *R _{F}*/(1 +

The input matching afforded by the above technique holds for frequencies up to about *ω*_{0}, dictating that the open-loop bandwidth of the core amplifier reach the maximum frequency of interest. The intrinsic speed of deep-submicron devices provides the gain and bandwidth required here.

The reader may wonder if our modeling of the core amplifier by a one-pole response applies to multistage implementations as well. We return to this point below.

Figure 5.52 shows a circuit realization of the amplifier concept for the frequency range of 50 MHz to 10 GHz [7]. Three common-source stages provide gain and allow negative feedback. Cascodes and source followers are avoided to save voltage headroom. The input transistor, *M*_{1}, has a large width commensurate with flicker noise requirements at 50 MHz, thus operating with a *V _{GS}* of about 200 mV. If this voltage also appears at node

With three gain stages, the LNA can potentially suffer from a small phase margin and exhibit substantial peaking in its frequency response. In this design, the open-loop poles at nodes *A*, *B*, *X*, and *Y* lie at 10 GHz, 24.5 GHz, 22 GHz, and 75 GHz, respectively, creating a great deal of phase shift. Nonetheless, due to the small feedback factor, *R _{S}*/(

The multi-pole LNA of Fig. 5.52 contains an inductive component in its input impedance but with a behavior more complex than the above analysis suggests. Fortunately, behavioral simulations confirm that, if the poles at *B*, *X*, and *Y* are “lumped” (i.e., their time constants are added), then the one-pole approximation still predicts the input admittance accurately. The pole frequencies mentioned above collapse to an equivalent value of *ω*_{0} = 2*π* (9.9 GHz), suggesting that the real and imaginary parts of *Y*_{1} retain the desired behavior up to the edge of the cognitive radio band.

The LNA output is sensed between nodes *X* and *Y*. Even though these nodes provide somewhat unequal swings and a phase difference slightly greater than 180°, the pseudo-differential sensing still raises both the gain and the *IP*_{2}, the latter because second-order distortion at *X* also appears at *Y* and is thus partially cancelled in *V _{Y}* −

The dynamic range of the signal sensed by a receiver may approach 100 dB. For example, a cell phone may receive a signal level as high as −10 dBm if it is close to a base station or as low as −110 dBm if it is in an underground garage. While designed for the highest sensitivity, the receiver chain must still detect the signal correctly as the input level continues to increase. This requires that the gain of each stage be reduced so that the subsequent stages remain sufficiently linear with the large input signal. Of course, as the gain of the receiver is reduced, its noise figure rises. The gain must therefore be lowered such that the degradation in the sensitivity is less than the increase in the received signal level, i.e., the SNR does not fall. Figure 5.53 shows a typical scenario.

Gain switching in an LNA must deal with several issues: (1) it must negligibly affect the input matching; (2) it must provide sufficiently small “gain steps”; (3) the additional devices performing the gain switching must not degrade the speed of the original LNA; (4) for high input signal levels, gain switching must also make the LNA *more linear* so that this stage does not limit the receiver linearity. As seen below, some LNA topologies lend themselves more easily to gain switching than others do.

Let us first consider a common-gate stage. Can we reduce the transconductance of the input transistor to reduce the gain? To switch the gain while maintaining input matching, we can insert a physical resistance in parallel with the input as *g _{m}* is lowered. Figure 5.54 shows an example [8], where the input transistor is decomposed into two,

In the above calculation, we have neglected the effect of channel-length modulation. If the upper bound expressed by Eq. (5.67) restricts the design, then the cascode CG stage of Fig. 5.24 can be used.

Another approach to switching the gain of a CG stage is illustrated in Fig. 5.55, where the on-resistance of *M*_{2} appears in parallel with *R*_{1}. With input matching and in the absence of channel-length modulation, the gain is given by

For multiple gain steps, a number of PMOS switches can be placed in parallel with *R*_{1}. The following example elaborates on this point.

The principal difficulty with switching the load resistance in a CG stage is that it alters the input resistance, as expressed by *R _{in}* = (

The advantage of the above technique over the previous two is that the gain step depends only on *W*_{3}/*W*_{2} (if *M*_{2} and *M*_{3} have equal lengths) and not the absolute value of the on-resistance of a MOS switch. The bias and signal currents produced by *M*_{1} split between *M*_{3} and *M*_{2} in proportion to *W*_{3}/*W*_{2}, yielding a gain change by a factor of 1 + *W*_{3}/*W*_{2}. As a result, gain steps in the circuit of Fig. 5.57 are more accurate than those in Figs. 5.54 and 5.55. However, the capacitance introduced by *M*_{3} at node *Y* degrades the performance at high frequencies. For a single gain step of 6 dB, we have *W*_{3} = *W*_{2}, nearly doubling the capacitance at this node. For a gain reduction by a factor of *N*, *W*_{3} = (*N* − 1)*W*_{2}, possibly degrading the performance considerably.

In order to reduce the capacitance contributed by the gain switching transistor, we can *turn off* part of the main cascode transistor so as to create a greater imbalance between the two. Shown in Fig. 5.58 (on page 310) is an example where *M*_{2} is decomposed into two devices so that, when *M*_{3} is turned on, *M*_{2}* _{a}* is turned off. Consequently, the gain drops by a factor of 1 +

We now turn our attention to gain switching in an inductively-degenerated cascode LNA. Can we switch part of the input transistor to switch the gain (Fig. 5.59)? Turning *M*_{1}* _{b}* off does not alter

As with the CG LNA of Fig. 5.55, the gain can be reduced by placing one or more PMOS switches in parallel with the load [Fig. 5.60(a)]. Alternatively, the cascode switching scheme of Fig. 5.57 can be applied here as well [Fig. 5.60(b)]. The latter follows the calculations outlined in Example 5.24, providing well-defined gain steps with a moderate additional capacitance at node *Y*. It is important to bear in mind that cascode switching is attractive because it reduces the current flowing through the load by a well-defined ratio *and* it negligibly alters the input impedance of the LNA.

For the two variants of the CG stage studied in Section 5.3.3, gain switching can be realized by cascode devices as illustrated in Fig. 5.57. The use of feedback or feedforward in these topologies makes it difficult to change the gain through the input transistor without affecting the input match.

Lastly, let us consider gain switching in the noise-cancelling LNA of Fig. 5.48(b). Since *V _{Y}*/

Which one of the foregoing gain reduction techniques also makes the LNA *more linear*? None, except for the last one! Since the CG and CS stages retain the gate-source voltage swing (equal to half of the input voltage swing), their linearity improves negligibly. In the feedback LNA of Fig. 5.48(b), on the other hand, a lower *R _{F}* strengthens the negative feedback, raising the linearity to some extent.

Receiver designs in which the LNA nonlinearity becomes problematic at high input levels can “bypass” the LNA in very-low-gain modes. Illustrated conceptually in Fig. 5.61, the idea is to omit the LNA from the signal path so that the mixer (presumably more linear) directly senses the received signal. The implementation is not straightforward if input matching must be maintained. Figure 5.62 depicts a common-gate example, where *M*_{1} is turned off, *M*_{2} is turned on to produce a 50-Ω resistance, and *M*_{3} is turned on to route the signal to the mixer.

As mentioned in Section 5.1, LNAs that must operate across a wide bandwidth or in different bands can incorporate band switching. Figure 5.63(a) repeats the structure of Fig. 5.7(a), with the switch realized by a MOS transistor. Since the bias voltage at the output node is near *V _{DD}*, the switch must be a PMOS device, thus contributing a larger capacitance for a given on-resistance than an NMOS transistor. This capacitance lowers the tank resonance frequency when

The choice of the width of *S*_{1} in Fig. 5.63(b) proves critical. For a very narrow transistor, the on-resistance, *R _{on}*

The foregoing observation implies that *R _{on}*

An alternative method of band switching incorporates two or more tanks as shown in Fig. 5.64 [8]. To select one band, the corresponding cascode transistor is turned on while the other remains off. This scheme requires that each tank drive a copy of the following stage, e.g., a mixer. Thus, when *M*_{1} and band 1 are activated, so is mixer *MX*_{1}. The principal drawback of this approach is the capacitance contributed by the additional cascode device(s) to node *Y*. Also, the spiral inductors have large footprints, making the layout and routing more difficult.

As explained in Chapter 4, even-order distortion can significantly degrade the performance of direct-conversion receivers. Since the circuits following the downconversion mixers are typically realized in differential form,^{18} they exhibit a high IP_{2}, leaving the LNA and the mixers as the IP_{2} bottleneck of the receivers. In this section, we study techniques of raising the IP_{2} of LNAs, and in Chapter 6, we do the same for mixers.

Differential LNAs can achieve high IP_{2}’s because, as explained in Chapter 2, symmetric circuits produce no even-order distortion. Of course, some (random) asymmetry plagues actual circuits, resulting in a finite, but still high, IP_{2}.

In principle, any of the single-ended LNAs studied thus far can be converted to differential form. Figure 5.65 depicts two examples. Not shown here, the bias network for the input transistors is similar to those described in Sections 5.3.3 and 5.3.4.

But what happens to the noise figure of the circuit if it is converted to differential form? Before answering this question, we must determine the source impedance driving the LNA. Since the antenna and the preselect filter are typically single-ended, a transformer must precede the LNA to perform single-ended to differential conversion. Illustrated in Fig. 5.66(a), such a cascade processes the signal differentially from the input port of the LNA to the end of the baseband section. The transformer is called a “balun,” an acronym for “balanced-to-unbalanced” conversion because it can also perform differential to single-ended conversion if its two ports are swapped.

If the source impedance provided by the antenna and the band-pass filter in Fig. 5.66(a) is *R _{S}*

Note that the differential input impedance of the LNA, *R _{in}*, must be equal to

We now calculate the noise figure of the differential CG LNA of Fig. 5.65(a), assuming it is designed such that the impedance seen between each input node and ground is equal to *R _{S}*

Since each half circuit provides matching at the input, the CG results of Section 5.3.3 apply here as well with the substitution *R _{S}* =

From Eq. (5.148), the total output noise power is twice this amount. Noting that the total voltage gain *A _{v}* = (

Interestingly, this value is lower than that of the single-ended counterpart [Eq. (5.58)]. But why? Since in Fig. 5.67(c), *V _{Y}*/

In summary, a single-ended CG LNA can be converted to differential form according to one of three scenarios: (1) simply copy the circuit, in which case the differential input resistance reaches 100Ω, failing to provide matching with a 1-to-1 balun; (2) copy the circuit but double the transconductance of the input transistors, in which case the input is matched but the overall voltage gain is doubled; (3) follow the second scenario but halve the load resistance to retain the same voltage gain. The second choice is generally preferable. Note that, for a given noise figure, a differential CG LNA consumes *four* times the power of a single-ended stage.^{19}

Our NF calculations have assumed an ideal balun. In reality, even external baluns have a loss as high as 0.5 dB, raising the NF by the same amount.

The differential CS LNA of Fig. 5.65(b) behaves differently from its CG counterpart. From Section 5.3.4, we recall that the input resistance of each half circuit is equal to *L*_{1}*ω _{T}* and must now be halved. This is accomplished by halving

To compute the noise figure, let us first determine the output noise of the half circuit depicted in Fig. 5.70(b). Neglecting the contribution of the cascode device, we note from Section 5.3.4 that, if the input is matched, half of the noise current of the input transistor flows from the output node. Thus,

Multiplying this power by two, dividing it by and 4*kTR _{S}*

How does this compare with the noise figure of the original single-ended LNA [Eq. (5.101)]? We observe that both the transistor contribution and the load contribution are halved. The transistor contribution is halved because *g _{m}*

The reduction of the input transistor noise contribution in Eq. (5.157) is a remarkable property of differential operation, reinforcing the NF advantage of the degenerated CS stage over the CG LNA. However, this result holds only if the design can employ *two* degeneration inductors, each having *half* the value of that in the single-ended counterpart. This is difficult with bond wires as their physical length cannot be shortened arbitrarily. Alternatively, the design can incorporate on-chip degeneration inductors while converting the effect of the (inevitable) bond wire to a common-mode inductance. Figure 5.72 shows such a topology. With perfect symmetry, the bond wire inductance has no effect on the differential impedance seen between the gates. Nonetheless, as explained in Chapter 7, on-chip inductors suffer from a low quality factor (e.g., a high series resistance), possibly degrading the noise figure. We compare the power consumptions of the single-ended and differential implementations in Problem 5.22.

The NF advantage implied by Eq. (5.157) may not materialize in reality because the loss of the balun is not negligible.

Is it possible to use a differential pair to convert the single-ended antenna signal to differential form? As shown in Fig. 5.73(a), the signal is applied to one input while the other is tied to a bias voltage. At low to moderate frequencies, *V _{X}* and

The capacitance at *P* can be nulled through the use of a parallel inductor [Fig. 5.73(b)] [9], but the *C _{GD}*

The topology of Fig. 5.73(b) still does not provide input matching. We must therefore insert (on-chip) inductances in series with the sources of *M*_{1} and *M*_{2} (Fig. 5.75). Here, *L _{P}*

The foregoing development of differential LNAs has assumed ideal 1-to-1 baluns. Indeed, external baluns with a low loss (e.g., 0.5 dB) in the gigahertz range are available from manufacturers, but they consume board space and raise the cost. Integrated baluns, on the other hand, suffer from a relatively high loss and large capacitances. Shown in Fig. 5.76 is an example, where two spiral inductors *L _{AC}* and

The reader may wonder if an *N*-to-1 (rather than 1-to-*N*) balun proves beneficial in the above example as it would multiply the first two terms of Eq. (5.160) by 1/*N*^{2} rather than *N*^{2}. Indeed, off-chip baluns may provide a lower noise figure if *L*_{1} (a bond wire) can be reduced by a factor of *N*^{2}. On the other hand, on-chip baluns with a non-unity turns ratio are difficult to design and suffer from a higher loss and a lower coupling factor. Figure 5.78(a) shows an example [5], where one spiral forms the primary (secondary) of the balun and the series combination of two spirals constitutes the secondary (primary). Alternatively, as shown in Fig. 5.78(b), spirals having different numbers of turns can be embedded [10].

The difficulty with the use of off-chip or on-chip baluns at the input of differential LNAs makes single-ended topologies still an attractive choice. A possible approach to raising the IP_{2} entails simply filtering the low-frequency second-order intermodulation product, called the beat component in Chapter 4. Illustrated in Fig. 5.79, the idea is to remove the beat by a simple high-pass filter (HPF) following the LNA. For example, suppose two interferers are located at the edges of the 2.4-GHz band, *f*_{1} = 2.4 GHz and *f*_{2} = 2.480 GHz. The beat therefore lies at 80 MHz and is attenuated by approximately a factor of 2400/80 = 30 for a first-order HPF. With this substantial suppression, the IP_{2} of the LNA is unlikely to limit the RX performance, calling for techniques that improve the IP_{2} of *mixers* (Chapter 6).

The filtration of the IM_{2} product becomes less effective for wider communication bands. For example, if a receiver must accommodate frequencies from 1 GHz to 10 GHz, then two interferers can produce a beat *within* the band, prohibiting the use of filters to remove the beat. In this case, the LNA may become the receiver’s IP_{2} bottleneck.

The general behavior of nonlinear systems was formulated in Chapter 2. In this section, we develop a methodology for computing the nonlinear characteristics of some circuits.

Recall from Chapter 2 that systems with weak static nonlinearity can be approximated by a polynomial such as *y* = *α*_{1}*x* + *α*_{2}*x*^{2} + *α*_{3}*x*^{3}. Let us devise a method for computing *α*_{1}-*α*_{3} for a given circuit. In many circuits, it is difficult to derive *y* as an explicit function of *x*. However, we recognize that

These expressions prove useful because we can obtain the derivatives by implicit differentiation. It is important to note that in most cases, *x* = 0 in fact corresponds to the *bias* point of the circuit with no input perturbation. In other words, the total *y* may not be zero for *x* = 0. For example, in the common-source stage of Fig. 5.80, *M*_{1} is biased at a gate-source voltage of *V _{GS}*

As an example, let us study the resistively-degenerated common-source stage shown in Fig. 5.81, assuming the drain current is the output of interest. We wish to compute the IP_{3} of the circuit. For a simple square-law device

where *K* = (1/2)*μ _{n}C_{ox}*(

and hence

We also note that

where *V _{in}*

an expected result.

We now compute the second derivative from Eq. (5.166):

With no signals, (5.168) and (5.169) can be substituted in (5.170) to produce

Lastly, we determine the third derivative from (5.170):

which, from (5.169) and (5.171) reduces to

While lengthy, the foregoing calculations lead to interesting results. Equation (5.173) reveals that *α*_{3} = 0 if *R _{S}* = 0, an expected outcome owing to the square-law behavior assumed for the transistor. Additionally,

To compute the IP_{3} of the stage, we write from Chapter 2,

The 1-dB compression point follows the same expression but lowered by a factor of 3.03 (9.6 dB).

The reader may wonder if the above analysis of nonlinearity confuses large-signal and small-signal operations by expression *α*_{1}-*α*_{3} in terms of the device transconductance. It is helpful to bear in mind that *g _{m}* in the above expressions is merely a short-hand notation for a

Consider the CS stage shown in Fig. 5.80. Submicron transistors substantially depart from square-law characteristics. The effect of mobility degradation due to both vertical and lateral fields in the channel can be approximated as

where *μ*_{0} denotes the zero-field mobility, *v _{sat}* the saturation velocity of the carriers, and

The input signal, *V _{in}*, is superimposed on a bias voltage,

where *K* = (1/2)*μ*_{0}*C _{ox}*(

We note that the IP_{3} rises with the bias overdrive voltage, reaching a maximum of

at *V _{GS}*

In RF systems, differential signals can be processed using the differential pair shown in Fig. 5.85(a) or the “quasi-differential” pair depicted in Fig. 5.85(b). The two topologies exhibit distinctly different nonlinear characteristics. We know from our above analysis that the dependence of the mobility upon vertical and lateral fields in the channel results in third-order nonlinearity in the quasi-differential pair and an IP_{3} given by Eq. (5.189). To study the nonlinearity of the standard differential pair, we recall from basic analog circuits that

where *V _{in}* denotes the input differential voltage. If |

That is,

and hence

where (*V _{GS}*

Interestingly, the standard differential pair suffers from third-order nonlinearity even in the absence of field-dependent mobility (i.e., with square-law devices). For this reason, the quasi-differential pair of Fig. 5.85(b) is preferred in cases where linearity is important. In fact, it is for this reason that the differential CS LNA of Fig. 5.65(b) does not employ a tail current source. The quasi-differential pair also saves the voltage headroom associated with the tail current source, proving more attractive as the supply voltage is scaled down.

Consider the degenerated pair shown in Fig. 5.86, where *I _{D}*

where *V _{in}* =

At *V _{in}* = 0,

where *g _{m}* = 2

Note that for *V _{in}* = 0, we have because

It follows that . We now have that

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[2] D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier,” *IEEE J. Solid-State Circuits,* vol. 32, pp. 745–759, May 1997.

[3] P. Rossi et al., “A Variable-Gain RF Front End Based on a Voltage-Voltage Feedback LNA for Multistandard Applications,” *IEEE J. Solid-State Circuits,* vol. 40, pp. 690–697, March 2005.

[4] X. Li, S. Shekar, and D. J. Allstot, “*G _{m}*-Boosted Common-Gate LNA and Differential Colpitts VCO/QVCO in 0.18-um CMOS,”

[5] A. Zolfaghari, A. Y. Chan, and B. Razavi, “Stacked Inductors and 1-to-2 Transformers in CMOS Technology,” *IEEE Journal of Solid-State Circuits,* vol. 36, pp. 620–628, April 2001.

[6] F. Bruccoleri, E. A. M. Klumperink, and B. Nauta, “Wideband CMOS Low-Noise Amplifier Exploiting Thermal Noise Canceling,” *IEEE J. Solid-State Circuits,* vol. 39, pp. 275–281, Feb. 2004.

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5.1. Assuming *Z _{in}* =

5.2. If *R _{p}* =

5.3. Repeat Example 5.5 by solving the specific network shown in Fig. 5.10(a).

5.4. Determine the noise figure of the stages shown in Fig. 5.87 with respect to a source impedance of *R _{S}*. Neglect channel-length modulation and body effect.

5.5. For the inductively-loaded CS stage of Fig. 5.11(b), determine *V _{out}*/

5.6. For the CS stage of Fig. 5.13(a), determine the closed-loop gain and noise figure if channel-length modulation is not neglected. Assume matching at the input.

5.7. For the complementary stage shown in Fig. 5.15, determine the closed-loop gain and noise figure if channel-length modulation is not neglected. Assume matching at the input.

5.8. For the CG stage of Fig. 5.16(a), compute the noise figure at the output resonance frequency if *g _{m}* ≠ 1/

5.9. A circuit exhibits a noise figure of 3 dB. What percentage of the output noise power is due to the source resistance, *R _{S}*? Repeat the problem for NF = 1 dB.

5.10. Determine the noise figure of the CG circuits shown in Fig. 5.17.

5.11. In Example 5.10, we concluded that the noise of *M*_{2} reaches the output unattenuated if *ω* is greater than (*R*_{1}*C _{X}*)

5.12. If *L _{G}* in Fig. 5.34 suffers from a series resistance of

5.13. The LNA shown in Fig. 5.88 is designed to operate with low supply voltages. Each inductor is chosen to resonate with the total capacitance at its corresponding node at the frequency of interest. Neglect channel-length modulation and body effect and the noise due to the loss in *L*_{2}. Determine the noise figure of the LNA with respect to a source resistance *R _{S}* assuming that

5.14. Determine *S*_{11} for both topologies in Fig. 5.40 and compute the maximum deviation of the center frequency for which *S*_{11} remains lower than −10 dB.

5.15. Repeat the analysis of the CG stage in Fig. 5.43 while including channel-length modulation.

5.16. Repeat the NF analysis of the CG stage in Fig. 5.43 while including the noise of the feedback network as a voltage, , in series with its input.

5.17. Prove that the input-referred noise of the feedforward amplifier in Fig. 5.45(a) manifests itself as the fourth term in Eq. (5.124).

5.18. Repeat the analysis of the CG stage of Fig. 5.45(a) while including channel-length modulation.

5.19. Is the noise of *R _{F}* in Fig. 5.48(b) cancelled? Explain.

5.20. For the circuit shown in Fig. 5.89, we express the input-output characteristic as

where *I*_{0} and *V*_{0} denote the bias values, i.e., the values in the absence of signals. We note that *∂I _{out}*/

(a) Write a KVL around the input network in terms of *V _{in}* and

(b) Differentiate the equation obtained in part (a) with respect to *V _{in}* once more and compute

(c) Determine the *IP*_{2} of the circuit.

5.21. Determine the noise figure in Example 5.21 if the gain is reduced by 3 dB.

5.22. Compare the power consumptions of the single-ended and differential CS stages discussed in Section 5.6.1. Consider two cases: (a) the differential stage is derived by only halving *L*_{1} (and hence has a lower noise figure), or (b) the differential stage is designed for the same NF as the single-ended circuit.

5.23. Repeat the analysis of the differential CG stage NF if a 1-to-2 balun is used. Such a balun provides a voltage gain of 2.

5.24. Consider a MOS transistor configured as a CS stage and operating in saturation. Determine the *IP*_{3} and *P*_{1dB} if the device (a) follows the square-law behavior, *I _{D}* ∝ (

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