In Chapter 10, Sensing and Displaying Real-World Data, we connected to devices using a bus protocol called I²C. Raspberry Pi also supports another chip-to-chip protocol called Serial Peripheral Interface (SPI). The SPI bus differs from I²C because it uses two single direction data lines (where I²C uses one bidirectional data line).

Although SPI requires more wires (I²C uses two bus signals, SDA and SCL), it supports the simultaneous sending and receiving of data and much higher clock speeds than I²C:

The SPI bus consists of the following four signals:

• SCLK: This allows the clock edges to read/write data on the input/output lines; it is driven by the master device. As the clock signal changes from one state to another, the SPI device will check the state of the MOSI signal to read a single bit. Similarly, if the SPI device is sending data, it will use the clock signal edges to synchronize when it sets the state of the MISO signal.
• CE: This refers to Chip Enable (typically, a separate Chip Enable is used for each slave device on the bus). The master device will set the Chip Enable signal to low for the device that it wants to communicate with. When the Chip Enable signal is set to high, it ignores any other signals on the bus. This signal is sometimes called Chip Select (CS) or Slave Select (SS).
• Master Output, Slave Input (MOSI): It connects to Data Out of the master device and Data In of the slave device.
• Master Input, Slave Output (MISO): It provides a response from the slave.

The following diagram shows each of the signals:

The previous scope trace shows two bytes being sent over SPI. Each byte is clocked into the SPI device using the SCLK (1) signal. A byte is signified by a burst of eight clock cycles (a low and then high period on the SCLK (1) signal), where the value of a specific bit is read when the clock state changes. The exact sample point is determined by the clock mode; in the following diagram, it is when the clock goes from low to high:

The first byte sent is 0x01 (all the bits are low, except Bit 0) and the second sent is 0x03 (only Bit 1 and Bit 0 are high). At the same time, the MOSI (4) signal returns data from the SPI device-in this case, 0x08 (Bit 3 is high) and 0x00 (all the bits are low). The SCLK (1) signal is used to sync everything, even the data being sent from the SPI device.

The CE (2) signal is held low while the data is being sent to instruct that particular SPI device to listen to the MOSI (4) signal. When the CE (2) signal is set to high again, it indicates to the SPI device that the transfer has been completed.

The following is an image of an 8 x 8 LED matrix that is controlled via the SPI Bus: