Compression and limiting play an increasingly important role in the resources of a modern sound studio. The conventional function of signal level control is to avoid overload, but it can be used in the realm of special effects. To date, however, relatively few designs for high-fidelity compressor/limiters have been published.

The main design problem is the voltage-controlled attenuator, v.c.a., which increases attenuation of the input signal in response to a voltage from a control loop as shown in Figure 1. In limiting, this circuit block continuously monitors the peak output level from the v.c.a. and acts to maintain an almost constant level if it exceeds a threshold value, or, in compression, allows it to increase more slowly than the v.c.a. input signal. This is illustrated in Figure 2, which shows the input-amplitude/output-amplitude characteristic for both compression and limiting. Note that limiting makes use of a much tighter slope to ensure that the output voltage cannot exceed the chosen limit, and that the threshold (point of onset of attenuation) takes place at a higher level than for compression.

Traditionally, studio-quality compressor/limiters (as the two functions are so similar it is logical to produce a system that can be used for either compression or limiting) used one of two types of v.c.a. Either the audio signal was chopped at an ultrasonic frequency by a variable mark/space square wave – which requires complex circuitry and careful filtering of the audio output to avoid beats with tape-recorder bias frequencies – or it was attenuated by an electronic potential divider one arm of which was a photoresistor, the control signal being applied via a small filament bulb. The last-mentioned has disadvantages because photoresistors are non-linear devices, therefore noticeable distortion is introduced into the audio signal, and the thermal inertia of the bulb filament limits the speed of attenuation onset.

Most modern compression systems use field-effect transistor operated below pinch-off as a voltage-variable resistance in a potential divider. This technique has many advantages; it is a simple, cheap, and fast-acting configuration that can provide an attenuation variable between 0 and 45 dB. The only problem is that an FET is a square-law device, and tends to generate a level of second-harmonic distortion that increases rapidly with signal amplitude. A typical arrangement is shown in Figure 3 – R₂, R₃ and C₂ allow the source of the FET to be set at a d.c. level above ground, so that a control-voltage that moves positive with respect to ground can be used, to avoid level-shifting problems in the control loop. This d.c. level is isolated from the input and output by C₁.

The distortion introduced by this circuit is at its worst for the 6 dB attenuation condition, because at this point the drain-source resistance equals R₁, and the maximum power level exists in the FET. Table 1 shows the level of second-harmonic distortion introduced into a sine-wave signal of 100 mV r.m.s. amplitude, under the 6 dB attenuation condition for three different FET types. Measurements were made with a Marconi TF2330 wave analyser, higher-orders of harmonic distortion proved to be negligible amplitude in all cases. These measurements were made on one sample of each type of FET and, because production spreads are large, the results should be treated with some caution. However, it is clear that these levels of distortion are unacceptable for high-quality applications.

Fortunately, a technique exists for reducing FET distortion to manageable levels, if the control-voltage is applied to the FET gate and summed with a signal consisting of one-half the voltage from drain to source, then the distortion level is dramatically lowered. The configuration in Figure 4 shows a simple way of realising this; the signal fraction fed back is not critical and 10% resistors can be used for R₄ and R₅. Surprisingly, this distortion cancellation procedure leaves the attenuation/control-voltage characteristic almost unchanged. Table 1 shows the new maximum distortion values for 100 mV r.m.s. input. (Note that the maximum no longer occurs at 6 dB attenuation, but at a point that varies with the FET type, where cancellation is least effective.) From these results the 2 N5457 and 2 N5459 are superior, the 2 N5459 was used in the final version of the v.c.a.

To determine appropriate signal levels in the v.c.a., measurements were made of maximum distortion generated, i.e. the v.c.a. was set to 2 dB attenuation, against r.m.s. input voltage; results are shown in Table 2. The question now arises as to whether this distortion performance is adequate for a high-quality compressor/limiter. There is no general agreement as to the amount of second harmonic distortion that can be introduced into a program signal before it becomes aurally detectable, but 0.1% is a figure that is quoted. This means that the permissible input voltage to the v.c.a. would be restricted to below 100 mV r.m.s. In practice, however, the attenuation level will be constantly changing, and because distortion level peaks fairly sharply with attenuation change, this level of distortion will only be present for a very small percentage of the time. In any case, second harmonic distortion alone has a relatively low ‘objectionability factor’. The proof of the pudding is in listening to the compressor output signal; inputs of music around 200 mV r.m.s. produced no trace of audible distortion. (Good class A power amplifiers and headphones were used for monitoring).

The control loop consists of an amplifier which senses the v.c.a. output level. A full-wave rectification system is normal practice because program waveforms have positive and negative peaks that can vary by as much as 8 dB, and an 8 dB uncertainty in the output level is usually unacceptable. A time-constant arrangement is used with the rectification circuit to control the attack and decay rates.

The output sensing amplifier in the system is a non-inverting op-amp which allows a high input impedance because the output impedance of the v.c.a. stage reaches a maximum of about 39 kΩ at zero attenuation. The fullwave rectification system consists of a transistor phase-splitter driving two op-amp precision-rectifier stages in antiphase. The principle of a precision rectifier is illustrated in Figure 5. The rectifying element is placed in the feedback loop of an op-amp, so that the effect of the forward voltage drop on the output voltage is divided by the open-loop gain. During positive half-cycles, if the input voltage exceeds the d.c. level stored on the capacitor C, the op-amp output swings positive and C is charged through diode D until its stored voltage is equal to the input voltage. Thus C takes up a voltage across it equal to that of the positive peak of the input signal. During negative half-cycles, and while the input is less than the voltage on C during positive half-cycles, the op-amp saturates negatively and D remains firmly reverse-biased. Obviously this is only a half-wave rectification circuit, the full-wave version uses two of these driven in antiphase, and charging a common capacitor. A resistance through which the charging currents flow determines the attack time, and another in parallel with C defines the decay time-constant.

The complete circuit is shown in Figure 6. The v.c.a. is essentially as described above and the attenuation threshold is set by the variable resistance R₂. As the resistance is increased the level of control voltage required for attenuation to begin is reduced, and the system’s input/output characteristic moves smoothly from A to B on Figure 2. The threshold decreases and the compression slope becomes less flat as the system turns slowly from a limiter into a compressor by the manipulation of a single control. The output sensing amplifer consists of IC₁ and has a gain of 19 over the audio band. This is rolled off to unity at d.c. by C₅. Transistor Tr₂ and its associated components form a conventional phase-splitter driving IC₂ and IC₃ the precision rectifiers. The rectifier circuitry is more complex than implied above, three modifications have been made to improve the performance. Firstly, IC₂ and IC₃ charge C₉ via current amplifier stages Tr₅ and Tr₆ otherwise the current-limited 741 outputs would be unable to provide enough current for the faster attack times (less than 1 mS). Secondly, the feedback loop from C₉ to the inverting unputs of IC₂ and IC₃ is completed via a FET source-follower. Without this, C₉ would be loaded by the two 741 inputs, and this would severely limit the maximum decay times available. Incorporating the source-follower allows decay times of several minutes by using large resistance values for R₂₇. The conventional source-follower has a large negative offset voltage and is unusable in this application because due to their the rectifying action IC₂ and IC₃ are unable to provide a voltage on C₉ that is negative of ground. This would be required to allow the source-follower output to be at ground when there is no input to the rectifers. However, if a modified source-follower is used, with a constant-current source and resistance combination in the source circuit, the offset voltage can be varied on either side of zero by manipulation of R₂₄ which varies the driving current. The offset voltage is arranged to be plus 0.3 V, to allow a large safety margin for thermal variations, component ageing, etc. This means that under no-signal conditions C₉ takes up a standing quiescent voltage of plus 0.3 V. The effect of this is taken up in the calibration of R₂.

The third modification is the addition of R₂₁,D₃, and R₂₂,D₄. These two networks prevent IC₂ and IC₃ from saturating negatively, during negative half-cycles of their input voltage, by allowing local negative feedback through D₃ and D₄. This limits the negative excursion of the IC outputs to about 2 V. The prevention of saturation is necessary because the recovery time of the 741 s causes the frequency response of the precision rectifier circuit to drop off at about 1 kHz. The addition of the anti-saturation networks provides a frequency response that starts to fall off significantly above about 12 kHz which is ample for our purposes as program signals have very little energy content above this frequency.

The final part of the circuit defines the attenuation time constants. Resistor R₂₆ sets the attack time constant and R₂₇ the decay time constant; these can range between 0 and 1 MΩ (220 μs and 10 s) for R₂₆, and 1 kΩ and ∞ (10 mS and 20 min) for R₂₇. They can be either switched or variable resistances, depending on the range of variation required.

The circuit in Figure 6 shows the compressor output being taken directly from the v.c.a. This is only suitable if the minimum load to the output is greater than 100 kΩ, otherwise the v.c.a. attenuation characteristic will be distorted by excessive loading. If lower resistance loads are to be driven a buffer amplifier stage must be interposed. The IC₁ amplifier stage is suitable for most applications, and its gain is (R₇ + R₈)/R₈. For the unity gain case R₈ & C₅ can be eliminated and R₇ replaced by a direct connexion.

The compressor should be driven from a reasonably low impedance output (less than 5 kΩ).

Construction is straightforward; the layout is not critical and the prototype was assembled on 0.1 in matrix Veroboard. To set up the circuit R₂₄ is adjusted so that the voltage across C₉ is about + 0.3 V with no signal input. The value required will vary due to production spreads in the f.e.ts. To calibrate R₂ it is necessary to relate the level of input signal at which attenuation commences, with the voltage across C₂. This can be done with an oscilloscope, or preferably an a.f. millivoltmeter. As a guide the calibration data for the prototype is shown in Table 3, along with the values of the compression ratio (number of dBs the input must increase by to increase the output by 1 dB). This data must be regarded as only a guide. It is worth noting that as the controlling factor setting the compression/limiting function is the voltage across C₂ R₂ could be replaced by a 1kΩ resistor connected to a remote voltage source.

The compressor/limiter is quite straightforward in use, provided a few points are kept in mind. Firstly, if it is being used in the limiting mode to prevent overload of a subsequent device, the fastest possible attack time should be used, to catch fast transients, and a fast decay time (say 100 ms; R₂₇ = 10 kΩ), to allow the system to recover rapidly when the transient has passed. Secondly, if a noisy programme signal is being compressed a long decay time should be employed, otherwise the noisy background will be faded up during quiet passages, and the familiar compressor ‘breathing noises’ will be heard. Finally, signals with a large v.l.f. content should be avoided or filtered, otherwise v.l.f. modulation of the signal will result, if a fast decay time is in use.

If a stereo compressor/limiter is constructed from two of the systems described above it is necessary to gang together R₂, R₂₆, and R₂₇ between the two channels. A direct connection between the non-grounded sides of the two C₉s is also needed. It might be necessary to select matched f.e.ts to avoid stereo image shift during compression, due to differing attenuation characteristics in the two v.c.as. A well-smoothed p.s.u. providing ± 15 V should be used to power the compressor/limiter.