Copyright © 2011 NVIDIA Corporation and Wen-mei W. Hwu. All rights reserved.
Introduction
The State of GPU Computing in Electronic Design Automation
The success of very large-scale integrated (VLSI) design hinges heavily on design automation techniques to speed up the design process. Electronic design automation (EDA) software utilizes several key underlying algorithms, and an efficient implementation of these algorithms holds the key to our ability to design highly integrated, complex integrated circuits (ICs) of the future. Over the last few years, GPUs have received close attention by EDA practitioners, and significant speedups have been obtained by implementations of several key algorithms on the GPU. Some of these algorithms include logic simulation, Boolean satisfiability, fault simulation, and state space exploration.
In the future, it is expected that GPU computing will hold a key role in EDA advances. As more EDA algorithms are sped up using GPUs, it is conceivable that users of EDA tools will have the ability to quickly perform what-if analyses when different optimization options are invoked. Such an ability is not available today owing to the large runtimes associated with several steps of the EDA flow. More flexible GPU architectures will hold the key to making this possible.
In This Section
In this section, we present two chapters that utilize GPUs to accelerate specific EDA algorithms.
Chapter 23 addresses logic simulation at the gate level, using GPU-based algorithms. Logic simulation is a key step in the design automation process, allowing the designer to verify whether their design meets specifications. The approach employs gate levelization and then maps the independent computations of each level on a GPU, thereby leveraging the parallelism available. This is combined with a technique that performs event-driven simulation at a higher level of circuit granularity.
Chapter 24 addresses performance and power optimization (by simultaneous gate sizing and theshold voltage adjustment). This is a key step in automatic circuit optimization after technology mapping. The approach employs clever task scheduling in order to maximize the speedup available from a GPU-based algorithm.
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