Index

  • 3M and 5M, § V1-1.2

A

  • abacus, § V1-1.1
  • ABC, § V1-1.2 and computer model
  • ABI, cf. interface
  • access, § V3-2.4.2
    • multiple, § V3-2.1.1.4
    • read, § V3-2.4.2
    • read-modify-write, § V3-2.4.2
    • write, § V3-2.4.2
  • accumulator, cf. register
  • adding machine, § V1-1.1
    • Model K, § V1-1.2
  • addition, cf. arithmetic operation
  • address
    • effective (EA), § V3-3.1.6, V3-3.4.4, V4-1.2, V4-2.2.2 and V4-3.2.1
    • format, § V4-1.2.1 and V4-1.2.3
    • physical (PA), § V4-1.2 and V5-1.2.1
    • translation, § V4-3.2.2
    • virtual (VA), § V1-1.4, V3-2.1.1.1, V4-2.5.4, V4-3.2.2, V4-5.7 and V5-1.2.1
  • addressing, § V4-1.2
    • bit-reversed, § V4-1.2.4.5.2
    • circular, § V4-1.2.4.5.1
    • geographical, § V2-1.5
    • linear, § V4-1.2.4.5.3
    • memory to memory, § V1-3.3.3, V4-1.1 and V4-1.2.4.1
    • MMR, § V3-3.1.1 and V4-1.2.4.4
    • mode, § V4-1.2
    • random, § V1-2.1
    • space (AS), § V3-2.1.1.1
  • alignment, § V1-2.2.2
  • Arithmetic and Logic Unit (ALU), cf. unit/integer processing
  • Antikythera mechanism, § V1-1.3
  • API, cf. interface
  • Apple II, cf. microcomputer
  • arbitration, cf. bus
  • architecture, § V1-3.1.4
    • according to storage location, § V1-3.5.1
      • accumulator, § V1-3.4.1
      • memory-to-memory, § V1-3.5.1
      • stack, § V1-3.5.1
      • register-memory, § V1-3.5.1
      • register-register (load–store), § V1–3.5.1
    • CISC, § V3-1.2, V4-1.1, V4-2.1, V4-2.4 and V4-2.8.1
      • fault, § V4-1.2.5
    • classification of computers (definition), § V1-3.1.4
    • CRISC, § V1-3.4.3
    • EPIC, § V1-3.4.3 and V3-4.7
    • exo/endoarchitecture, § V1-3.1.4
    • General-Purpose Register (GPR), § V1-3.5.1
    • Harvard, § V1-3.3.2, V1-3.3.4, V1-3.4.2, V3-2.1.1.1, V3-5.2 and V3-5.3
    • microarchitecture, § V1-3.1.4, V1-3.3.1.2, V4-3.4.2, V4-3.4.5 and V4-5.2.4
    • MISC, § V1-3.4.3.1
      • OISC/SISC/URISC, § V1-3.4.3.1
      • ZISC, § V1-3.4.3.1
    • no or several addresses, § V1-3.5.1
    • one or several buses, § V1-3.4.1
    • RISC, § V1-1.2, V1-2.2.1, V1-3.4.3.1, V1-3.5, V3-1.2, V3-3.1.2, V3-3.1.11.3, V3-3.1.12.6, V3-4.6, V3-5.3, V4-1.1, V4-1.2, V4-2.1, V4-2.4, V4-2.7.1 and V5-1.1.4
    • superscalar, § V1-3.3, V1-3.4.3.1, V1-3.4.3, V3-4.6, V4-1.1, V4-2.4.2 and V5-1.3
    • TTA, § V1-3.4.3.1
    • very long instruction word (VLIW), § V1-3.4.3, V1-3.5.3, V3-4.6, V3-4.7, V3-5.2, V4-2.4.2, V4-2.8.5 and V5-1.3
    • von Neumann, § V1-3.2.2, V1-3.3, V3-5.3 and V4-1.2.4.8
    • x86, § V1-3.3.2, V1-3.4.2, V1-3.5.1, V1-3.5.4, V3-3.1.9, V4-2.1, V4-3.1, V4-3.2.2, V4-3.3, V4-4.1, V4-5.2.1, V4-5.4, V4-5.7 and V5-2.2.5
  • arithmetic operation, § V1-3.3.1.2.1, V3-3.3 and V4-2.3.1
    • addition, § V1-1.1, V1-1.2, V1-3.2.2, V1-3.3.1.2.1, V1-3.4.2, V1-3.5.3.1, V3-3.1.5.1 and V4-2.3.1
    • complementation, § V1-1.1
    • divide-by-zero, § V4-5.4, V4-5.6 to V4-5.9, V4-5.11 and V5-2.3
    • division, § V1-2.1, V1-3.3.1.2.1, V3-5.4, V4-2.3.1 and V4-2.7.1
    • multiplication, § V3-3.1.1, V3-3.1.2, V3-4.3, V3-5.2, V3-5.4, V4-1.2.2.2, V4-2.7.1 and V4-2.7.2
    • subtraction, § V1-1.1, V1-3.5.1, V3-3.1.5.1, V4-2.4.1, V4-2.7.2 and exercises V1-E1.1, V1-E3.2, V4-E2.2 and V4-E2.3
  • arithmetic
    • integer, § V1-1.1, V3-1.2, V3-3.1.1, V3-3.3, V4-2.3.1 and V4-2.7.2
    • floating-point, § V1-1.2, V1-3.3 and V4-2.8.4.2
    • modular, § V3-5.2, V4-1.2.4.5.1 and V4-2.3.1
    • saturation, § V3-5.2
  • ASIC, § V1-1.2 and V5-3.3.1
  • assembler, § V5-1.2.1 also cf. development tool
  • asynchronism, § V2-1.3 and V3-2.4.3
  • ATB, cf. bus/address

B

  • Babbage, § V1-1.1, V4-5.1 also cf. mechanical computing machines
  • bandwidth, § V1-2.1, V1-3.1.4, V2-1.2, V2-1.6, V2-4.1, V2-4.2.2, V2-4.2.6, V2-4.2.9, V3-5.2 and V4-3.4
  • BCD, cf. representation/integer
  • BCS, cf. file format
  • benchmark, cf. performance
  • Beowulf, cf. cluster
  • BINAC, cf. computer model
  • binding, § V5-1.2.2.
  • BIOS, cf. firmware
  • binary format, § V1-2.1 and V4-1.1
    • byte, § V1-2.1
    • nibble, § V1-2.1
    • superword, § V4-2.3.2.1
    • word, § V1-2.1
  • binary pattern, § V2-1.4, V3-5.3, V3-5.4, V4-5.9, V5-2.2.2 and V5-3.5.3
  • bit rate, § V1-2.1 and V2-1.2
  • black box, § V1-3.1.4 and figures V3-E3.2 and V3-E3.4
  • BNF, § V5-1.2.1
  • Boolean logic, § V1-1.1, V1-3.1.4, V4-2.4.1 and V4-2.6.1
  • bottleneck, § V1-3.2.2.2, V1-3.3.4, V1-3.4.2, V1-3.5.1 and V2-1.2
  • branching, § V1-3.1.2, V3-3.1.5, V3-5.2, V4-1.1, V4-2.3.2.2, V4-2.4 and V5-1.3
    • conditional, § V4-1.2.4.3 and V4-2.4.1
    • test-and-branching, § V4-2.6.1
    • unconditional, § V1-3.3.4 and V4-2.4.1
  • break, § V4-2.5.2
  • bus
    • concepts, § V1-1.1 and V2-1.1
      • alignment, § V2-1.2 also cf. memory (concepts)
      • arbitration (local/distributed), § V2-1.5, V2-1.6, V2-2.1, V2-3.1, V2-3.2 and V2-4.2.9
      • bandwidth, § V2-1.2 and V2-4.2.9
      • characteristics, § V2-1.2
      • derivation, § V2-1.2 and V2-3.3.1
      • multi- § V2-4.1.3
      • MUX-based or multiplexed, § V2-4.2.9
      • parallel, § V2-1.2
      • passive, § V2-1.2
      • serial, § V2-1.2
      • specialized (i.e. dedicated), § V2-1.2
      • starvation, § V2-1.6 and V4-5.3
    • computer, cf. computer bus
    • fieldbus, § V2-4.2.8
    • microprocessor, § V3-2.1
      • address, § V3-2.1
      • data, § V3-2.1
      • control, § V3-2.1
      • interface, § V3-3.5 and V2-3.1
    • power, § V2-4.2.10
    • products, § V2-4.2
      • AGP, § V2-4.1.4, V2-4.2.4 and V5-3.3.1
      • BSB, § V2-4.2.1 and V5-3.3.1
      • DIB, § V2-4.2.1 and V5-3.3.1
      • DMI, § V2-4.2.3 and V5-3.3.1
      • FSB, § V2-4.2.1, V3-2.4.1 and V5-3.3.1
      • EISA, § V2-2.2.3, V2-4.2.4 and V5-3.3.1
      • HyperTransport (HT/LDT), § V2-4.2.3 and V5-3.3.1
      • ISA, § V2-2.2.1, V2-4.1.4, V2-4.2.4, V5-3.2.1, V5-3.2.3 and V5-3.3.1
      • MCA, § V2-4.2.4
      • NuBus, § V2-4.2.7
      • PCI, § V2-1.1, V2-1.6, V2-2.2.3, V2-3.2, V2-4.1.4, V2-4.2.4, V3-2.1.1.1 and V5-3.3.1
      • PCI express (PCIe), § V2-1.2, V2-4.2.4 and V2-4.2.7
      • PCI-X, § V2-4.2.4
      • QPI, § V2-4.2.3
      • Unibus™, § V2-1.3, V2-1.6 and V2-4.3
      • VMEbus™, § V2-1.5, V2-1.6, V2-3.2, V2-4.2.7 and V2-4.3
    • products for Multibus, § V2-1.3, V2-3.2, V2-4.1, V2-4.2.5, V2-4.2.7 and V2-4.3
      • iLBX, § V2-4.1
      • iPSB, § V2-4.1
      • iSBX, § V2-4.1 and V2-4.5
      • iSSB, § V2-4.1
    • SoC bus, § V2-4.2.9
  • butterfly (circuit), § V4-2.3.2.5

C

  • cache, cf. memory/cache
  • capacity, cf. memory/characteristics
  • carry, § V4-2.3.1, exercise V4-E2.1 also cf. code/condition
  • CDC, cf. computer model
  • CFSD, § V1-1.2
  • CGMT, cf. parallelism/ multithreading
  • circuit logic, cf. integrated circuit logic
  • checksum, § V3-5.3 and V5-3.5.3
  • chip set, § V5-3.3
    • CCAT, NEAT, POACH and SCAT, § V5-3.3
    • definition, § V5-3.3.1
    • hub, § V2-4.2.1, V2-4.2.3 and V5-3.3.1
    • northbridge (GMCH), § V2-4.2.1
    • southbridge (ICH), § V2-4.2.1
  • CISC, cf. architecture
  • clock, § V3-2.4.1 and V3-3.4.2
    • circuit, § V3-1.2, V3-2.1, V3-2.4.1 and V3-4.3
    • cycle, § V5-2.2.4.3
    • domain crossing (CDC), § V2-1.3, V2-3.1 and V3-6.1.3
    • energy saving, § V3-6.1.4
    • frequency/period, § V1-1.2, V1-1.5, V1-2.1, V1-3.4.3.2, V1-3.4.3.3, V2-1.2, V3-1.2, V3-6.1, V4-3.4.1 and V4-3.4.5
    • signal, § V2-1.2, V2-1.3, V2-3.2, V2-3.6, V3-3.4.2, V3-3.4.3.3, V4-3.4.1 and V5-2.2.5
  • cloud, cf. cloud computing
  • cluster, § V1-1.2
    • definition, § V1-1.2
    • workstations (COW), § V1-1.2
  • CMOS, cf. electronic technology
  • CMP, cf. multicore
  • CMT, § V1-3.4.3.2 and V3-4.7
  • code
    • 8b/10b, § V2-1.2
    • compression, § V4-1.1.1
    • condition, § V3-3.1.5, V3-3.1.12.1, V4-2.4 cf. also register/status
    • Dual-Rail (DR), § V2-1.4 and exercise V2-E1.1
    • instruction/operation, § V4-1.1
    • machine, cf. language/machine
    • Multi-Rail (MRn), § V2-1.4
    • pure, § V4-3.1.4
    • re-entrant, § V4-3.1.4, V4-4.2.1 and V4-5.3
    • relocatable, § V4-3.1.4
  • COFF, cf. format
  • commands, § V5-1.2.2
  • communication, § V2-1.1
    • broadcast, § V2-1.1, V2-2.2, V2-3.3.6 and V4-5.7
    • cycle
      • bus, § V2-3.6 and V2-4.2.2
    • duplex, § V2-1.1
      • full, § V2-3.3.4, V2-3.3.6, V2-4.2.3 and V2-4.2.4
      • half-duplex, § V2-1.1
      • simplex, § V2-3.3.6
    • general points, § V2-1.1
    • protocol, § V2-1.5
    • splitting the transaction, § V2-2.1.1
    • through bundles, § V2-4.2.2
    • transaction pipeline, § V2-2.1.1
  • comparison, cf. logical operation
  • compatibility, § V4-3.3
    • backward and forward, § V4-3.2.3
    • electromagnetic (EMC), § V2-3.3.2
    • hardware, § V4-3.2.1
    • software, § V4-3.2.2
  • Commercial Off-The-Shelf (COTS), § V1-1.2 and V2-1.2
  • compiler, cf. development tool
  • computer
    • analog, § V1-1.3
    • classes, § V1-1.2
      • electromechanical, § V1-1.2
      • electronic, § V1-1.2
    • Mr Perret’s letter, § V1-1 (footnote)
    • stored program, § V1-3.2.3
  • computer bus
    • access arbitration, § V2-1.6
    • asynchronous/synchronous, § V2-1.3
    • backplane, § V1-1.2 and V2-4.2.7
    • bridge, § V2-4.1.4
    • centerplane, § V2-4.2.7
    • extension, § V2-4.2.4
    • hierarchical, § V2-4.1.2
    • I/O, § V2-4.2.6
    • local, § V2-4.2.1
    • mastering, § V2-2.2.3
    • memory (channel), § V2-1.2, V2-3.3.1, V2-3-6 and V2-4.2.2
    • multiple, § V2-4.1.3
    • packet switching, § V2-3.6
    • protocol, § V2-1.5 and V3-2.4.2
    • standard, § V2-1.2
    • segmented, § V2-4.1.1
    • switch, § V2-3.3.6, V2-4.2.7 and V2-4.2.9
  • computer categories, § V1-1.2
    • macrocomputer, cf. computer/mainframe
    • microcomputer, § V1-1.2 also cf. microcomputer
    • minicomputer, § V1-1.2
    • supercomputer, § V1-1.2
  • computer model
    • ABC, § V1-1.2
    • BINAC, § V1-1.2
    • Burroughs B5000, § V1-1.2
    • Colossus, § V1-1.2
    • Control Data Corporation (CDC), § V1-1.4
    • CDC 6600, § V1-1.2 and V1-3.5.1
    • Cyber 205, § V1-1.4
    • Cray, § V1-1.2 and V4-2.4.1
      • Cray-1, § V4-2.4.1
      • Cray MPP, § V1-1.4
      • Cray X-MP, § V1-1.4
      • Cray Y-MP, § V4-3.2.2
    • DEC, § V1-3.5
    • EDSAC, § V1-1.2 and V5-1.1
    • EDVAC, § V1-1.2
    • ENIAC, § V1-1.2
    • Harvard Mark I, § V1-1.2
    • IAS Princeton, § V1-1.2
    • IBM, § V1-1.2
      • IBM 650, § V1-1.4 and V1-3.5.1
      • IBM 701, § V1-1.4, V1-3.2.2.3, V1-3.5.3 and V3-2.1.1.1
      • IBM 3090, § V1-1.4
      • IBM stretch, cf. § V1-3.1.4 (footnote)
      • IBM System/360, § V1-1.2 and V4-2.4.1
      • IBM System/370, § V4-1.1, V4-1.2.3.1, V4-2.4.1 and V4-3.2.4
    • Illiac IV, § V1-1.2, V3-2.4.3 and V3-3.3
    • Manchester, § V1-1.2
      • Manchester Baby, § V1-1.2
      • Manchester Mark I, § V3-3.1.6
    • PDP, § V1-1.2
      • PDP-11, § V1-2.2.1, V2-1.6 and V3-3.1.3
    • SEAC, § V1-3.5.1
    • VAX, § V1-1.2, V1-2.1 and V1-2.2.1
      • VAX-11, § § V1-1.2 and V1-3.5.1
      • VAX-9000, § V1-1.4
    • UNIVAC I, § V1-1.2
    • Whilwind, § V1-1.2
    • Zuse Z1, Z2, Z3 and Z4, § V1-1.2
  • computation model, § V1-3.1.3
    • concurrent, § V1-3.1.3
    • control flow, § V1-3.1.3
    • declarative, § V1-3.1.3
    • object oriented, § V1-3.1.3
    • Turing, § V1-3.1.3
    • von Neumann, § V1-3.2.1
  • computing
    • cloud, § V1-1.2
      • IaaS, PaaS and SaaS, § V1-1.2
    • ubiquitous, § V1-1.2
  • control mechanism, § V1-3.1.2
    • control-driven (CO), § V1-3.1.2
    • data-driven (DA), § V1-3.1.2
    • demand-driven (DE), § V1-3.1.2
    • pattern-driven (PA), § V1-3.1.2
  • control structure, § V1-3.1.1, V1-3.3.4, V3-3.1.5.7, V4-1.2.3.2, V4-1.2.5, V4-2.4, V4-2.4.1, V4-2.4.3 and V4-3.1.5
    • loop, § V1-3.1.1
    • if_then_else, § V1-3.1.1
  • co-processor, § V3-5.4
    • graphics, § V3-5.4
    • I/O, § V3-5.4
    • mathematical, § V3-5.4
  • core, cf. multicore
  • costs
    • bus, § V2-1.1, V2-1.2, V2-3.3.5 and V2-4.2.7
    • computer, § V1-1.1
    • memory, § V1-2.1 and V1-2.1
  • counting stick, § V1-1.1
  • CPI, cf. performance/unit of measurement
  • Cray-1, cf. computer model
  • crossbar, cf. grid/crossbar matrix
  • cryptography, § V4-2.7.3
  • cycle
    • access, § V3-2.1.2
    • clock, cf. clock
    • CPU/processor, § V1-3.4.3
    • execution, § V1-3.2.2.4, V1-3.3.1.2.2, V1-3.3.2 and V3-3.1.3
      • decoding, § V1-3.2.2, V1-3.3.1.2, V3-3.4.3.2, V4-1.1 and V4-1.2.3.2
      • fetch, § V3-3.1.4, V3-3.4.3.1
      • phase, § V3-3.4.3
    • life, § V1-1.2
    • machine, § V3-2.4
    • number, § V2-1.5 and V3-2.4.1
    • read, § V2-1.5
    • special, § V2-2.2
    • time, § V1-2.1 and V2-3.2.1
    • write, § V2-1.5

D

  • data mechanism, § V1-3.1.2
    • passing messages (ME), § V1-3.1.2
    • shared data (SH), § V1-3.1.2
  • datasheet, § V3-6
  • DDR, cf. semiconductor-based memory (component)
  • debug monitor, cf. firmware
  • debugging hardware interface
  • decoding
    • address, § V2-2.1.1, V2-3.1, V3-2.1.1.1, V3-2.1.1.2, V3-2.3 and V5-3.3.1
      • incomplete, § V2-3.1
    • instruction, cf. execution cycle
  • decrement/increment, § V4-1.2.3.3, V4-1.2.3.5 and V4-1.2.4.5
    • automatic, § V3-3.1.6
    • pre- and post-, § V4-1.2.3.3
  • debugging, § V5-2.2
  • delay
    • time, § V2-1.2, V2-1.3, V3-2.4.1 and V3-2.4.3
  • descriptor table, § V1-3.5.6
    • GDT, § V3-3.1.9
    • IDT, § V4-5.10
    • LDT, § V3-3.1.9
  • development/design stage, § V5-1.1.2
  • development/design chain/tools, cf. development tool
  • Dhrystone. cf. performance/benchmark/synthetic suite
  • diagram in Y, § V1-3.1.4
  • Direct Memory Access (DMA), § V1-3.3
  • disassembler, cf. development tool
  • division, cf. arithmetic operation
  • DSP, cf. processor
  • DTL, cf. electronic technology

E

  • EDSAC, cf. computer model
  • EDVAC, cf. computer model
  • EFI, cf. firmware
  • electrical overshooting, § V2-3.3.2
  • electromechanical relay, § V1-1.2
  • electronic board, § V1-1.2, V2-1.2 and V5-2.1.1
    • dummy board (CRIMM), § V2-1.6
    • start, evaluation, development board, § V5-2.1.1
    • motherboard, § V1-1.2, V2-1.2 and V5-3.1
  • electronic logic
    • buffer, § V1-3.4, V2-3.3.4, V2-4.1.4, V3-2.4.1, V4-3.1, V4-3.2.1 and V4-3.3.1
      • driver, § V2-3.3.4
    • three-state, § V1-3.4, V2-1.3, V2-1.6, V2-3.3.4 and V3-2.1
    • transceiver, § V2-3.3.4
  • electronic technology, § V1-1.2
    • BiCMOS, § V1-2.4, V2-3.3.7
    • CMOS, § V1-1.5, V1-2.4, V2-1.3, V2-3.3.7, V3-1.1, V3-1.2, V3-2, V3-4 and V3-6
    • DTL, § V1-1.2
    • ECL, § V2-3.3.7 and V3-5.1
    • (C)HMOS, § V3-4.3, V3-4.5, V3-4.6, V3-5.3 and V4-3.3.1
    • GTL/GTLP, § V2-3.3.7
    • LVDS, § V2-3.3.7, V2-4.2.3 and V4-3.3.1
    • MOS, § V3-1.2, V3-4.6 and V4-3.4.1
    • NMOS, § V3-1.2, V3-4.3 and V3-6.1.1
    • PMOS, § V3-1.1, V3-1.2, V3-4.2, V3-4.3, V3-4.5, V3-5.3, V3-5.4 and V3-6.1.1
    • SLT, § V1-1.2
    • TTL, § V2-3.3.7, V3-4.3, V3-5.1, V3-5.4, V5-3.1 and V5-3.2.1
  • electronic tube, cf. grid
  • element
    • communication, § V2-4.2.9
    • processing (PE), § V2-4.2.9
    • router (RE), § V2-4.2.9
    • storage, § V1-3.3.1.2.1
  • ELF, cf. format
  • ELSI, cf. integration technology
  • emulator, cf. development tool
  • endian/endianness, cf. memory/order of storage
  • energy savings, § V3-6.1.4
  • ENIAC, cf. computer model
  • error, § V1-2.1, V2-2.2.4, V2-3.2, V2-4.1.4, V2-4.2.3 and V3-5.2
    • ASCII/BCD, § V4-2.3.1 and exercises V4-E2.1 and E2.2
    • checking (ECC), § V2-4.1.4
    • CRC, § V2-3.2 and V4-2.7.1
    • detection (EDC), § V4-2.7.1 and V5-3.2.1
  • evolution
    • of concepts, § V1-1.4
    • of integration, cf. law/Moore’s
    • of roles, § V1-1.4
  • exception, cf. interruption
  • execution
    • conditional, § V4-2.4.2
    • context, § V3-3.1.12.2 and V4-4.2.2
    • mode, § V1-3.5.5, V3-3.1.12.4, V4-3.2.2, V4-5.9 and V4-5.10
      • real/protected, § V3-3.1.5.6, V3-3.1.12.4, V3-4.5, V3-4.6, V4-2.5.3, V4-3.2.2, V4-5.7, V4-5.10 and V4-5.11
      • supervisor, § V1-3.5.5, V3-1.2, V3-3.1.8, V4-3.2.2, V5-2.2.2 and V5-2.2.4.1
      • user, § V1-3.5.5
    • sequential, § V4-1.2.5
    • stop, § V3-4.3, V3-6.1.4, V4-2.5.2, V4-2.5.2, V4-5.2.2, V4-5.6, V4-5.8, V4-5.11 and V5-2.2.7
    • time, § V4-3.2.1, V4-3.4.3, V4-5.11 and V5-1.1.2

F

  • famine, cf. bus/concepts
  • faults
    • hardware/software, § V4-3.1.2, V4-3.2.4, V4-5.1, V4-5.4, V4-5.7 to V4-5.9 and V4-5.11
    • tolerance, § V1-1.2, V2-1.6 and V2-3.3.6
  • FFT (Fast Fourier Transform), cf. Fourier transform/fast
    • flow graph, § V4-1.2.4.5.2
  • FGMT, cf. parallelism/ multithreading
  • field, § V4-1.1, V5-1.2.1 and V5-1.3.3
    • address, § V4-1.2.3.1
    • comment, § V5-1.3.3
    • condition, § V4-2.4.2
    • function, § V4-1.1
    • identification, § V4-1.1
    • instruction, § V5-1.3.3
    • label, § V5-1.3.3
    • operand, § V4-1.1, V4-1.2.2.1 and V5-1.3.3
    • sub-field, § V4-1.1
  • file format
  • filtering/filter, § V2-3.3.4 and V3-5.2
    • Finite Impulse Response (FIR), § V3-5.2
    • Infinite Impulse Response (IIR), § V2-V3-5.2
    • digital, § V4-1.2.4.5.1, V4-1.2.4.5.2, V4-2.8.4.2 and V4-3.4.2
  • firmware, § V1-1.4, V2-3.1, V4-5.7 and V5-3.5
  • flag, cf. code/condition
  • flip-flop, § V1-1.2, V1-2.3, V1-3.1.4, V1-3.3.1.2.1, V1-3.3.1.2.2, V2-1.3, V2-3.1, V3-2.4.1, V3-3.1.1, V4-5.2.3, V4-5.3 and V5-2.2.5
  • flow, § V1-3.1.2 and V1-3.1.3, V2-1.5, V3-3.1.5.1 and V4-5.2
    • control, § V1-3.1.2
      • exceptional (ECF), § V1-3.1.2
      • graph (CFG), § V1-3.1.2
    • data flow, § V1-3.1.2
  • form factor, § V1-1.2, V5-3.4.1 and V5-3.4.2
    • AT, ATX, BTX, ITX, NLX, PC, WTX and XT, V5-3.4.1
  • format
    • binary, cf. binary format
    • file, cf. file format
    • instruction, cf. instruction format
  • Fourier transform, § V3-5.2
    • discrete, § V4-1.2.4.5.2
    • fast, cf. § V3-5.2, V4-1.2.4.5.2 and V4-3.4.4
  • FPGA, § V1-3.5.3, V2-4.2.10, V4-5.7 and V5-2.2.3
  • frame, cf. memory
  • FSM, cf. state/state machine
  • function, cf. subprogram

G

  • gate, cf. transistor/gate
  • glue logic, § V3-2.1.1.1, V3-2.3, V5-3.1 to V5-3.3 and V5-3.4.2
  • grid
    • crossbar matrix, § V2-3.3.6, V2-4.2.7 and V2-4.2.9
    • electronic tube, § V1-1.2
  • GSI, cf. integration technology

H

I

  • I/O
    • isolated (IIO) or separated, § V3-2.1.1.1
    • memory-mapped interface (MMIO), § V3-4.3 and V3-5.4
  • IAS Princeton, cf. computer model
  • IBI, § V5-3.5.3
  • iCOMP, cf. performance/benchmark
  • Illiac IV, cf. computer model
  • ILP, cf. parallelism/instructions
  • incrementation, cf. decrement
  • insertion-withdrawal under tension, § V2-3.4
  • instruction format, cf. instruction
  • Instruction Set Architecture (ISA), § V1-3.5
    • extension, § V4-2.4.2
    • IA-32 (Intel), § V3-3.1.1
    • instruction set, § V1-3.5.3
    • properties
      • execution modes, § V1-3.5.5
      • memory model, § V1-3.5.4
    • storage elements, § V1-3.5
  • integrated circuit logic
    • combinational, § V1-1.2, V1-3.1.4, V1-3.3.1.2.1, V3-3.3 and V4-4.1
      • family, § V1-1.2
      • sequential, § V1-3.3.1.2.1, V3-3.1 and V3-3.3
  • integrated circuit package
    • DIP, § V1-1.2, V3-1.1, V3-4.1, V4-5.2.2, V5-3.1 and V5-3.2.2
    • LGA, § V3-6.3
    • PGA, § V3-4.5 and V3-6.3
  • instruction
    • advanced bit manipulation instructions, § V4-2.3.2.4 and V4-2.3.2.5
    • alignment, § V4-2.3.2.4 and V4-3.1.2
    • arithmetic, § V3-3.1.5.1, V3-3.1.5.7, V4-2.3.1, V4-2.8.4, V4-2.4.1, V4-2.7.1 and V4-2.7.2 cf. also arithmetic operation
    • atomic, § V4-2.1, V4-2.3.2, V4-2.6.1 and V4-2.6.2
    • branching, § V3-5.2 and V4-2.4.1 to V4-2.4.3
    • break, § V4-2.5.2
    • bundle - VLIW, § V3-2.1.2
    • character manipulation (chains), § V4-2.8.1
    • class, § V4-2.1
      • control transfer, § V4-2.4
      • data processing, § V4-2.3
      • environmental, § V4-2.5
      • parallelism, § V4-2.6
      • transfer, § V4-2.2
    • code (op-code), § V4-1.1
    • coding, § V4-1.1 and appendix V4-1
    • control transfer, § V4-2.4
    • decoding, § V3-3.4.2 and appendix V4-1
    • dyadic, § V1-3.4.1 and V4-1.1
    • environmental, § V4-2.5
    • extension to the set, § V4-2.7
      • cryptography, § V4-2.7.3
      • format, § V4-1.1 and V4-1.2
      • multimedia, § V4-2.3.2.4 and V4-2.7.1
      • randomization management, § V4-2.7.4
      • signal processing, § V4-2.7.2
      • variable, § V3-3.4.3.2
    • high-level, § V4-2.8.3
    • illegal, § V4-3.1.1
    • Input/Output (I/O), § V4-2.8.2
    • invalid, § V4-3.1.1
    • macro-instruction, § V4-2.4.3, V4-4.2, V4-4.2.2, V5-1.1.2, V5-1.2.1, V5-1.3.3 and V5-1.3.4
    • micro-, § V1-3.1.4, V3-3.4.1, V3-3.4.3.2, V4-5.2.4 and V5-1.1.1
    • mnemonic, § V4-2.1, V4-3.1.5, V4-3.5 and V5-1.1
    • monadic, § V4-1.1
    • number per cycle/IPC, § V2-3.4.2
    • parallelism, § V4-2.6
    • per cycle (IPC), cf. performance/ unit of measurement
    • prefix, § V4-1.1
    • pseudo-instruction, § V5-1.3.3 and V5-1.3.4
    • set (IS), § V1-3.5.3 and V4-2.1
      • properties, § V1-3.5.3.1
        • orthogonality/symmetry, § V4-2.4.1
    • SIMD, § V4-2.3.2.4 and V4-2.7.1
      • micro, § V4-2.3.2.1
    • specific to digital representation, § V4-2.8.4
  • integration technology, § V1-1.2, V1-1.4, V1-1.5 and V1-3.1.4
  • interruption, § V4-5
    • cause
      • external, § V4-5.2
      • internal, § V4-5.4
    • controller, § V4-5.2.5
    • debugging, § V4-5.5
    • definition, § V4-5.1
    • hardware, § V4-5.2
    • instruction, § V4-3.2.2 and V4-5.4
    • mask and maskable/non-maskable INT, § V3-2.1.3, V3-3.1.5.4, V3-3.1.5.6, V3-3.1.5.7, V3-6.2, V4-5.2, V4-5.3, V4-5.6, V4-5.7, V4-5.9 and V4-5.11
    • nested, § V4-5.3 and V4-5.8
    • orthogonal, § V4-5.7
    • software, § V4-5.4
    • vectorization, § V4-5.7
  • IP (Intellectual Property), § V3-1.2
    • register x86, cf. register
  • ISA, cf. instruction set architecture or bus (products)
  • ISC, § V5-2.1.2
  • Ishango (incised bones of), § V1-1.1
  • ISP
    • bus, § V2-2.2.3
    • processor, § V1-3.1.4 and V4-2.1
    • programming, § V5-2.1.2
  • ITRS, § V1-1.4 and V1-1.5

J

  • JTAG, cf. test/interface

L

  • language
    • concepts, § V1-1.4
    • high-level (HLL), § V1-3.1.5, V4-1.2.3.3, V4-2.4.3, V5-1.1.1, V5-1.1.4, V5-1.3 and V5-1.3.4
    • layer of, § V5-1.1
    • level, § V5-1.1.1
    • machine, § V1-1.4, V1-3.3.4, V4-3.1.5, V5-1.1, V5-1.1.1 and V5-1.3
    • programming, cf. programming language
    • register transfer (RTL), cf. § V1-3.1.4, V1-3.3.1.2.1 and V3-3.1.3
  • LAPACK, cf. performance/core
  • latch, § V1-3.3.1.2.1
  • launcher cf. development tool
  • law
    • iron, § V4-3.4.3
    • Moore’s, § V1-1.2, V1-1.5 and V3-1.2
  • library (development), § V4-3.1.5 and V5-1.2.2
  • LINPACK, cf. performance/core
  • loading, cf. development tool
  • logic gate, § V1-1.2, V1-3.1.4, V2-3.3.4 and V2-4.1
  • logical operation, § V1-3.3.1.2.1, V4-2.3.2.2 and V4-2.7.1
    • comparison, § V4-2.4.1
    • complementation, § V4-2.4.1, V4-2.6.1 and § V3-2.1.3 (footnote)
    • NOT AND (NAND), § V1-1.2
    • permutation, § V2-1.2 and V2-4.1.4
  • look up memory, § V3-3.4.3.2 and V4-2.8.4.2
  • loom, § V1-1.1
  • loop
    • current, § V2-3.3.2
    • hardware, § V3-3.1.9 and V3-5.2
    • phased-locked (PLL), § V3-2.4.1
    • software, § V1-3.1.1, V1-3.3.2, V4-1.2.3.2 and V4-2.4.3
  • LSI, cf. integration technology
  • LVDS, cf. electronic technology

M

  • MAC, § V3-5.2 and V4-2.8.4.2
  • MACS, § V4-3.4.2
  • MBR
  • mask
    • binary/logical, § V3-3.3, V4-2.3.2.2, V4-2.3.2.4 and exercise V4-E2-5
    • interruption, cf. interruption
    • window, § V3-3.1.11.3
  • mass storage, § V1-1.2, V1-2.1, V1-2.3, V1-2.4 and V1-3.2.2.1
    • interface, § V2-1.2 and V2-4.2.6
    • library of cartridges, § V1-2.3
  • mechanical computing machines, § V1-1.1
    • analytical engine (Babbage), § V1-1.1
    • difference engine (Babbage), § V1-1.1
    • Pascaline, cf. exercise V1-E1.1
    • statistics machine, § V1-1.1
  • mechanism, § V1-3.1.2
    • control, cf. control mechanism
    • data, cf. data mechanism
  • memory
    • alignment, § V1-2.2.2, V1-3.5.4, V2-1.2; V3-2.1.1.4 and V3-3.4.3.2
    • boundary, § V4-3.1.2
    • buffer
      • queue (FIFO), § V1-2.1, V2-1.6, V2-3.1, V2-4.1.4, V4-1.2.4.5.1 and V5-2.3
      • stack (LIFO), § V1-3.5.1 and V4-4.1
    • byte access, § V2-3.2 and V3-2.1.1.4
    • cache, § V1-2.3, V1-2.4, V2-2.2, V2-2.2.5, V2-4.2.1, V3-3.1.9, V4-2.5.4, V4-2.5.5, V4-3.4, V4-5.7, V5-2.3 and V5-3.3.4
    • capacity/size, § V1-2.1
    • characteristics, § V1-2.1
    • classification, § V1-2.4
    • cycle communication, § V1-2.4
    • extension, § V3-2.1.1.3
    • hierarchy, § V1-2.3
    • interleaving, § V1-3.3.4 and V2-4.2.2
    • internal, § V3-3.2
    • look up, cf. look up memory
    • memory map, § V5-1.1.4
    • method or policy of access, § V1-2.1
    • model, § V2-3.5.4
    • modeling, § V1-2.3
    • multiport, § V3-3.1.11.1
    • order of storage (little/big endian, bi-endian), § V1-2.2.1, V2-1.1 and V2-1.2
    • organization, § V1-2.1 and V1-3.1.5
    • punched card, § V1-1.1 and V1-1.4
    • random access, cf. random access memory (RAM)
    • read-only, cf. read-only memory (ROM)
    • semiconductor-based, § V1-2
    • technology, § V1-2.3 and V1-2.4
    • UMB, § V5-3.2.3
    • unified, § V1-3.3.1.2.2, V1-3.2.2.1, V1-3.3.4, V1-3.4.2, V3-5.4, V5-3.3.1 and exercise V1-E3.1
  • MEMS, § V1-1.2
  • microcontroller (MCU), § V3-1.1 and V3-5.3
  • microcomputer, § V1-1.2 and V5-3
    • Apple II, § V5-3.1
    • IBM Personal Computer (PC)
    • Micral N, § V1-1.2 and V3-1.2
  • microprocessor (MPU)
    • commercial, § V3-1.2
    • definition, § V3-1.1
    • digital signal processor (DSP), § V3-5.2
    • family, § V3-4
    • generations, § V3-1.1 and V3-4
    • history, § V3-1.2
    • initialization, § V3-6.2 and V4-5.2.2
    • interfacing, § V3-2
    • single-bit, § V3-4.1
  • microprogramming, cf. logical unit/control unit
  • MIPS, cf. performance/unit of measurement
  • mixed language programming, § V5-1.1.3
  • MMX, cf. instruction/extension to the set
  • MOS, cf. electronic technology
  • MPP, cf. parallelism/processor
  • multiplication, cf. arithmetic operation
  • MSI, cf. integration technology
  • multicore, § V1-1.4, V1-3.3, V1-3.4.3.3, V3-1.1, V4-3.4.1 and V3-4.7
  • multiprocessor, § V1-3.6, V2-2.2.5, V2-4.2.9, V3-1.1, V4-3.2.2 and V4-3.6.2

N

  • NMOS, cf. electronic technology
  • NoC (Network-on-Chip), § V2-4.2.9
  • node
    • processing, § V1-1.2 and V1-3.6
    • technology, § V1-1.5
  • norms, cf. standard

O

  • object module, § V5-1.1.2, V5-1.1.3, V5-1.2.1, V5-1.2.2, V5-1.2.4 and V5-1.3.4
  • Operating System (OS), § V1-1.2, V1-1.4 and V3-1.2
    • calls, § V2-2.2.1
    • debugging, § V5-2.2.2
    • flag, § V3-3.1.5.6
    • MS-DOS, § V5-3.2.1 and V5-3.2.3
    • protection, cf. execution/mode
  • organization
    • of a memory, cf. memory
    • of computers, § V1-3.1.4
  • overflow, § V3-5.2
    • buffer, § V4-1.2.4.5.1
    • capacity, § V4-2.3.1 and V4-2.3.2.2
      • overflow (positive/negative), § V3-3.1.5.1, V3-3.1.5.3, V3-3.1.5.4, V3-5.3, V4-5.1, V4-5.4, V4-5.7, V4-5.11 and exercise V3-E3.4
      • underflow, § V3-3.1.5.4 and V4-5.4
    • format (unsigned), § V3-3.1.5.1, V4-2.3.1, V4-2.3.2.2 and exercise V3-E3.2
    • register window, § V3-3.1.11.3
    • segment, § V4-5.4
    • stack, § V4-4.1, V4-4.2.1 and V4-5.1

P

  • parallelism, § V1-1.4 and V1-3.4.3
    • instruction-level (ILP), § V1-3.4.3.1
    • multicores, § V1-3.4.3.3
    • multithreading, § V1-3.4.3.2
    • processor, § V3-5.5
    • thread level, § V1-3.4.3
  • parameters
    • calling convention, § V4-4.2.3
    • passage, § V3-3.1.12.3 and V4-4.2.3
  • path
    • control (CP), § V1-3.1.4 and V1-3.3.1.2.2
    • data (DP), § V1-2.3, V1-3.1.4, V1-3.2.2.1, V1-3.3.1.2.1, V1-3.3.3 and V5-3.3.1
    • definition, § V1-3.2.2.1
    • execution, § V1-3.1.2, V3-3.4.3, V4-2.4.1 and V4-2.4.2
    • instruction (IP), § V1-3.2.2.1
    • scan/exam/access, § V5-2.2.5 and V5-2.3
  • PC, cf. register/program counter
  • PCMark, cf. benchmark
  • PCMC, § V5-3.3.1
  • performance, § V4-3.4
    • core
      • LAPACK and LINPACK, § V4-3.4.4
    • measurement, § V4-3.4
    • program performance, § V4-3.4.4
    • unit of measurement (metric), § V4-3.4.4
      • Dhrystone, § V4-3.4.4
      • IPC, § V4-3.4.3.1
  • permutation, cf. logical operation/permutation
  • Personal Computer (PC), cf. microcomputer
  • PIC, cf. interruption/controller
  • pin, § V1-2.1, V2-1.2, V2-3.3.1, V2-3.6, V3-6.3, V4-5.2.2, V4-5.7 and V3-4.1
  • pipeline, § V1-3.3.2, V1-3.4.3.2, V3-1.2, V4-3.4.5, V4-5.11 also cf. communication/transaction pipeline
    • stall cycle, § V2-2.1.1 and V4-2.4.1
  • PLL, cf. loop/phase locked
  • PMOS, cf. electronic technology
  • PMS, § V1-3.1.4
  • poison bit, § V4-5.11
  • portability, § V4-3.2.3
  • POST, § V5-3.5.3
  • post-fixed notation, Reverse Polish Notation (RPN), § V1-3.5.1
  • power, § V3-6.1.2
    • dissipation, § V2-4.2.10
    • domain, § V3-6.1.3
    • dynamic, § V3-6.1.2
    • static, § V3-6.1.2
    • supply
      • consumption, § V3-6.1.2
      • profile, § V3-6.1.3
      • voltage, § V3-6.1.1
  • pre-decoding, § V3-3.4.3.2
  • predication, § V2-2.4.2
  • processor
    • bit slice, § V3-5.1
    • graphics, § V3-5.4
    • I/O, § V3-5.4
    • signal processing (DSP), cf. microprocessor
  • program, § V1-3.1.1
    • definition, § V1-3.1.1
    • stored, cf. computer (concepts)
  • program counter (CO/PC/IP), cf. register
  • programmer, § V5-2.1.2 and V5-3.5.3
  • programming language, § V1-3.1.4
    • assembly, § V1-1.4, V1-3.5.3, V4-1.2, V4-2.1, V4-2.4.2, V4-2.4.3, V4-3.1.3
    • to V4-3.1.5, V5-1.1 and V5-1.3
    • BASIC, § V5-3.1, V5-3.2.1, V5-3.5.2 and V5-3.5.2.2
    • COBOL, § V1-1.4, V1-3.1.3, V4-2.8.4.1 and V5-1.3
    • FORTRAN, § V1-1.4, V1-3.1.1, V1-3.1.3 and V4-3.4.4
    • LISP, § V1-3.1.3 and V1-3.1.4
  • punched card, cf. memory

Q

  • quipu, § V1-1.1

R

  • Random-Access Memory (RAM)
  • randomization management, § V4-2.7.4 and V5-3.3.1
  • Read-Only Memory (ROM), § V1-2.3, V1-2.4, V1-3.3.1.1 and V3-5.3
  • register, § V3-3.1 and V3-3.1.1
    • accumulator § V1-3.2.2.1 to V1-3.2.2.3, V1-3.4.1, V1-3.5.1, V3-3.1.2, V4-1.2.2.2, V4-1.2.4.2 and V4-2.2.1
    • address (MAR), § V1-3.2.2.2 to V1-3.2.2.4, V1-3.3.1.2.2, V1-3.4, V3-3.1.1 to V3-3.5
    • bank, § V3-3.1.11.2
    • category, § V3-3.1
    • cause, cf. register/surprise
    • data (MBR/MDR), § V1-3.2.2.2, V1-3.2.2.4, V1-3.3.1.2.2, V1-3.4, V3-3.1.1 and V3-3.5
    • definition, § V3-3.1.1
    • encoding, § V3-3.1.12.6
    • file, § V3-3.1.11.1
    • floating point number, § V3-3.1.2 and V3-3.1.5.4
    • format, § V3-3.1.1
    • general-purpose (GPR), § V1-3.5.1, V3-3.1.3, V3-3.1.8, V4-2.4.1 and V4-4.1
    • index, § V3-3.1.1, V3-3.1.6, V4-1.2.2.2, V4-1.2.3.4 and V4-1.2.3.5
    • indirection, § V2-.1.7, V4-1.2.3 and V4-4.1
    • instruction, § V3-3.1.1 and V3-3.4.3.1
    • Multiplier-Quotient (MQ), § V3-3.1.1
    • number, § V3-3.1.12.6 and V4-1.1
    • parallelism, § V3-3.1.12.5
    • Program Counter (PC), § V1-3.2.2.1 to V1-3.2.2.3, V1-3.3.1.2, V1-3.3.2, V3-2.1.1.1, V3-3.1.3, V4-1.1, V4-1.2, V4-1.2.3.2, V4-1.2.3.5, V4-2.4, V4-2.4.1, V4-2.4.3, V4-4.2, V4-4.2.2, V4-5.2.1, V4-5.7, V5-2.2.1, V5-2.2.3 and V5-2.2.4.3
    • projected in memory, § V3-5.4, V3-3.1.1, V4-1.2.4.4 and § V3-3.1 (footnote)
    • Shift Register (SR), cf. shift/register and shifter
    • stack pointer (SP), § V3-3.1.1, V3-3.1.8, V3-4.3, V4-1.2.4.2, V4-4.1 and V4-4.2
    • status (CCR)/of flags, § V1-3.3.1.2, V1-3.3.1.2.2, V1-3.3.2, V1-3.5.1, V3-3.1.5, V3-3.1.5.1, V3-3.1.5.4, V3-3.1.5.7, V3-3.1.8, V3-3.3, V3-3.4, V3-3.4.1, V3-3.4.3.3, V4-2.2.1, V4-4.2.3, V4-5.2.1, V4-2.2.4.3 and V5-2.2.5
    • surprise, § V4-5.7
    • test, § V3-3.1.9
    • windowing, § V3-3.1.11.3
  • relocatable, cf. code
  • representation of information
    • adjustment, § V4-2.3.1
    • ASCII, § V3-5.4 and V4-2.8.1
    • decimal number:
      • fixed-point, § V1-3.2.2.2, V1-3.6, V3-3.1.5.3 and V4-9.4
      • floating-point, § V3-3.1.5.4 and V4-9.4
    • integer
      • 2n’s complement (signed), § V1-3.6, V3-3.1.5.1, V3-3.3, V4-1.2.3.2, V4-2.3.1 and exercise V1-E1-1
      • BCD, § V1-3.3, V1-3.5.2, V1-3.6, V4-2.3.1, V3-3.1.5.1, V3-3.1.5.2 and V3-5.4
    • Unicode, § V4-2.8.1
  • reverse, § V4-1.2.4.5.2
  • RISC, cf. architecture
  • RNG, cf. random generator
  • rotation, § V3-3.3, V4-2.3.2 and V4-2.3.2.4
  • routine, cf. subprogram
  • RTC, § V3-6.1.4 and V4-3.3.1
  • RTL, § V1-3.1.4

S

  • SBC, § V1-1.2
  • scalability, § V2-1.2 and V2-4.2.9
  • SDR, cf. semiconductor-based (component)
  • (de)serialization, § V2-1.1
  • semantic gap, § V1-3.1.5
  • server, § V1-1.2
    • blade, § V1-1.2
  • SFF, § V1-2
  • shift, § V1-3.2.2.2, V1-3.3.1.2.1, V3-3.1.1, V3-3.3, V4-1.1, V4-1.2.4.5.1, V4-2.3.2 and V4-4.1
    • arithmetic, § V4-2.3.2.3
    • logical, § V4-2.3.2.3 and V4-2.3.2.4
    • register (SR), § V1-2.1, V1-3.2.2.2, V3-3.4.2, V3-5.4, V4-4.1 and V5-2.2.5
  • shifter
    • barrel, cf. exercises V3-E3.5 and V3-E3.6
    • circular, § V3-3.3
    • funnel, § V3-3.3
  • side effect, § V3-3.1.12.1 and V4-2.4.1
  • signal
    • integrity of the, § V2-3.3.2
    • noise, § V2-1.2, V2-1.3, V2-1.6, V2-3.3.4, V2-3.3.5, V2-4.1.1, V2-4.2.8, V2-4.2.10, V3-2.4.3, V3-5.2 and V3-6.3
  • simulator, cf. software debugging
  • SLSI, cf. integration technology
  • SLT, cf. electronic technology
  • (S)CMP, cf. multicore
  • SMP, cf. multicore
  • SMT
    • component, § V5-3.1 and V5-3.4.2
    • processor, § V1-3.4.3.2 and V3-4.7
  • SoC, § V1-1.2
  • software development tool, § V5-1.2
  • software interface
    • ABI (Application Binary Interface), § V4-4.1 and V5-1.1.4
    • API (Application Programming Interface), § V5-1.1.4 and V5-3.5.3
    • POSIX, § V5-1.1.4
  • software library, § V4-2.8.4.2
  • SPEC cf. performance/ benchmark/application suite
  • SSE, cf. instruction/extension to the instruction set
  • SSI, cf. integration technology
  • standard
    • BCS, cf. file format
    • CAN, cf. bus/fieldbus
    • component, § V1-1.2, V1-1.3, V2-1.2, V2-3.3.5 and V2-3.3.7
    • IEEE Standard
      • IEEE Std 694-1985, § V4-1.3.2, V4-1.3.3, V4-2.1 and V4-2.3.2.2
      • IEEE Std 754, § V4-2.8.4
      • IEEE Std 1003.1, § V4-1.1.4
      • IEEE Std 1149.1, § V2-3.5, V4-2.1.2 and V4-2.2.5
      • IEEE Std 1275, § V4-3.5.4
      • IEEE Std 1532, § V4-2.1.2
      • IEEE-ISTO Std 5001, § V4-2.2.2
    • ISA, cf. bus/extension
    • multibus, cf. bus/expansion
    • SEAC, cf. computer/SEAC
    • VESA, cf. bus/local
  • state
    • diagram, § V2-1.3, V3-3.4.1 and V5-2.1.2
    • information, § V3-3.3.1.1, V3-3.4 and V4-5.11
    • machine, § V1-3.3.1.2.2, V2-1.6, V2-3.1, V3-1.1, V3-2.4.1, V3-3.4.2, V3-3.4.3.2, V5-2.1.2 and V5-2.2.5
      • Turing, § V1-3.1.2 and V1-3.1.3
  • static and dynamic link library, cf. development tool
  • subprogram § V1-3.3.1.2.1 and V4-4
    • call/return, § V3-3.1.1, V3-3.1.5.7, V3-3.1.8 and V4-2.4.3
    • definition, § V4-4.2
    • instruction, § V4-2.4.3
    • nested, § V4-4.2.1
    • open, § V5-1.3.4
    • passing parameters, § V3-3.1.12.3
    • sheet, § V4-4.2
    • standard passing parameters, § V4-4.2.3
  • subtraction, cf. arithmetic operation
  • switching
    • circuit-, § V2-3.3.6 and V2-4.2.9
    • packet-, § V2-1.5, V2-2.2, V2-2.2.4, V2-4.1.4 and V2-4.2.9
  • synchronism, § V2-1.3
  • system
    • embedded, § V1-1.2
    • logical, cf. unit

T

  • technology
    • electronic, cf. electronic technology
    • integration, cf. integration technology
  • test, § V5-2.3
    • BIST, § V5-2.2.5
    • bus, § V2-3.5
    • instruction, cf. instruction/atomic, instruction/branching
    • interface, cf. debugging hardware interface
    • register, cf. register/test
    • self-test, § V3-5.3
    • test program, cf. performance/program and firmware/POST
  • time, § V1-1.4
    • access, § V1-1.2, V1-1.4, V1-2.1, V2-1.2, V2-1.5, V3-2.4.2, V3-3.1.11.1 and V3-3.2
    • bus settling, § V2-1.2, V2-1.3, V2-1.5 and V2-3.1
    • execution, cf. execution/time
    • cycle, § V1-1.4, V1-2.1, V1-2.3, V1-2.4, V3-1.2, V3-2.4.1 and V3-3.4.3.2
    • hold, § V2-1.5 and V2-3.1
    • reaction, § V4-5.3
    • starvation, § V4-5.3
    • switching, § V4-3.4.5
    • transfer, § V2-1.1 and V2-1.3
  • time (linked to software development)
  • TLP (Thread-Level Parallelism), § V1-3.4.3.2 and V3-4.7
  • transistor, § V1-1.2, V1-1.4 to V1-1.6, V1-3.1.4, V2-2.2.1 and V2-3.3.4
    • bipolar junction (BJT), § V1-1.2
    • density, § V1-1.2
    • field effect (FET), § V1-1.2
    • gate, cf. § V1-1.5 and V4-3.4.5
  • TTL, cf. electronic technology

U

  • UEFI, cf. firmware
  • ULSI, cf. integration technology
  • UMA, cf. memory (concepts)/unified
  • UMB, cf. memory (concepts)
  • unit
    • central, cf. § V1-1.2 and V3-1.1
    • logical
      • AGU, § V3-3.4.4 and V4-1.2.4.5.2
      • control unit, § V1-3.2.2.1, V1-3.3.1.2, V1-3.3.1.2.2 and V3-3.4
        • hardwired, § V1-3.2.3
        • microprogrammed, § V3-3.4, V3-3.4.3.2 and V4-1.1 (footnote)
      • DPU, § V5-3.3.1
      • FMAC, § V3-5.2
      • functional, § V3-1.2
      • Integer Processing (IPU), § V1-1.2, V1-3.3.1.2, V1-3.3.1.2.1, V3-3.3, V3-5.1 and V3-5.2
      • MAC, § V4-2.8.4.2 and V3-5.2
      • vector-based, § V1-1.2, V4-2.3.2 and V4-2.7.1
    • of measurement, § V1-1.2, V1-2.1 and V4-3.4
    • processing, cf. element/processing unit
  • UNIVAC, cf. computer model

V

  • verification
    • cycle, § V3-5.3
    • exchange, § V2-1.3
    • machine, § V2-2.5.7
    • memory, § V5-2.2.4.3 and V5-2.2.5
    • result, § V2-2.4.1
  • virtualization
    • debugging, § V5-2.2.6
    • MPU, § V3-3.1.5.6 and V4-3.2.4
    • server, § V1-1.2
    • virtual machine, § V1-1.4
  • VLIW, cf. architecture
  • VLSI, cf. integration technology
  • von Neumann machine, § V1-3.2 and V1-3.3
    • advantages and disadvantages, § V1-3.3.4

W

  • wall, § V1-1.5 and V3-1.2
    • fineness of etching, § V1-1.5
    • power, § V1-1.5, V3-1.1 and V3-6.1.2
    • red brick, § V1-1.5
    • speed, § V1-1.5
  • Whetstone, cf. performance/benchmark/synthetic suite
  • Whilwind, cf. computer model
  • word (broken down) into packets, § V4-2.3.2.1
  • workstations, cf. cluster/workstations
  1. This index covers all 5 volumes in this series of books.
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