Index
As this ebook edition doesn't have fixed pagination, the page numbers below are hyperlinked for reference only, based on the printed edition of this book.
Symbols
8-bit microcontrollers 5
32-bit cores
characteristics 17
A
Access Control Register (ACR) 121
ACK 177
address frame 177
Ad-hoc, On-demand, Distance Vector (AODV) 231
Advanced Encryption Standard (AES) 16
Advanced Peripheral Bus (APB) bus 131
analog-to-digital signal converter (ADC) 145
Application 82
application binary interface (ABI) 73
application protocols 237
distributed systems 239
message protocols 238
REST architectural pattern 238
ARM Cortex-M
asymmetric cryptography 61
B
Better Approach to Mobile Ad Hoc Networking (B.A.T.M.A.N.) 231
bitwise operations 118
examples 118
block-based SRAM protection 301, 302
Block Started by Symbol (BSS) 22
Bluetooth technology 216
boot code
application, running 80
building 77
running 77
image, building 83
multi-stage system, debugging 84, 85
remote firmware updates 87
secure boot 87
bug report 55
C
C compiler 20
commit 54
communication
authentication 233
confidentiality 233
integrity 233
Configurable Fault Status Register (CFSR) 74
configuration-management tools 53, 54
activities, tracking 55
code reviews 56
context switching 244, 247-249
Continuous Integration (CI) 62
Controller Area Network (CAN) bus 6
Core-Coupled Memory (CCM) 92
Cortex-M 38
Cortex Microcontroller Software Interface Standard (CMSIS) 58
Cortex-M instruction
Cortex-M microprocessor 17, 18
cross compilation 21
cross compiler 21
cross compiler, GCC toolchain 29-31
crosstool-NG 31
cryptography algorithms 61
D
DAC controllers 11
DASH7 218
data memory barrier (DMB) 94
data synchronization barrier (DSB) 94
debugger 25
Destination Sequence Distance Vector (DSDV) 231
Device Firmware Upgrade (DFU) 40
Digital Rights Management (DRM) 292
Direct Memory Access (DMA) 156
distributed embedded systems
challenges 15
Doxygen 66
dynamic IP routing
proactive dynamic-routing protocols 230
reactive dynamic-routing protocols 230
E
earliest-deadline-first scheduling (EDF) scheduling 265
efficiency 44
embedded Linux systems 4
embedded operating systems 282, 283
embedded project, life cycle 62, 63
documentation 66
project steps, defining 63, 64
refactoring 65
8-bit microcontrollers 5
multithreading 9
embedded TCP/IP stack implementations 264
emulators 48
enable wake-up pin (EWUP) 194
end of conversion (EOC) 148
Ethernet 214
Ethernet MAC controller 214
event mask register (EMR) 144
Executable and Linkable Format (ELF) 21
execute in place (XIP) 10, 121
execution program status register (xPSR) 250
EXTI 143
F
falling trigger select register (FTSR) 144
flash power down in deep sleep (FPDS) mode 194
heap memory management 285
G
binary format conversion 37
general-purpose input/output (GPIO) 11, 133
ADC controllers 11
DAC controllers 11
digital input 142
pin configuration 133
Pulse Width Modulation (PWM) 12, 137-141
timers 12
Generic Attribute Profile (GATT) 216
registers 130
Gerrit 56
Git 54
Global TrustZone Controller (GTZC) 300
GNRC 287
GNU Compiler Collection (GCC) 20
GNU GCC manual
reference link 31
GPIOx_SECCFG register 303
H
hash algorithms (SHA) 61
heap memory management
approaches 288
I
Implementation-Defined Attribution Unit (IDAU) 297
In-Application Programming (IAP) 10
input data register (IDR) 142
input/output (I/O) device 256
Input/Output (I/O) interface 234
instruction synchronization barrier (ISB) 94
integrated environments
versus text editors 28
inter-domain transitions 307-310
interfaces 12
Inter-integrated circuit (I2C) bus 13, 175, 176
controller, programming 180-183
interrupt handling 184
multiple masters 180
URL 176
International Electrotechnical Commission (IEC) 215
International Society of Automation (ISA) 215
Internet of Things (IoT) 14
Internet Protocol (IP) 14
interrupt controller 118
peripherals’ interrupt configuration 119, 120
interrupt mask register (IMR) 144
interrupt service routines (ISRs) 70
interrupt vector table (IVT) 69, 70, 91
stack, allocating 73
IPs 220
connectionless protocols 229
custom implementations 220
network device drivers 221-223
standard protocols 220
isolation mechanisms 15
Issue tracking systems (ITSs) 54
using 55
J
Jenkins 56
L
libopencm3 58
lightweight IP stack (lwIP) 221
linker script 32
linking process 32
link register (LR) 250
Linux kernel 4
Load Memory Address (LMA) 75
Load Register Exclusive (LDREX) 270
local 4444 TCP port 38
LoRa/LoRaWAN 217
low-power deep sleep (LPDS) mode 194
low-power embedded applications
busy loops, replacing with sleep mode 205, 206
clock speed, selecting 207
deep sleep mode, during longer inactivity periods 206
designing 205
power state transitions 207, 208
low-power operating modes 192
deep-sleep configuration 193-195
normal operation mode 192
wait for event (WFE) instruction 193
wait for interrupt (WFI) instruction 193
wake-up time intervals 203
Low-Speed External (LSE) 200
Low-Speed Internal (LSI) 200
industrial link-layer extensions 215
M
reference link 25
Master Stack Pointer (MSP) 274
Media Access Control (MAC) 212, 213
Bluetooth 216
ethernet 214
Low-Power Wide Area Networks (LPWANs) 217
Low-Rate Wireless Personal Area Networks (LR-WPANs) 214, 215
LR-WPAN industrial link-layer extensions 215
mobile networks 217
Wi-Fi 214
memory-array allocator 288
memory management unit (MMU) 4, 8
memory mapping 90
code region 91
order of memory transactions 93, 94
peripheral-access regions 93
RAM regions 92
system region 93
memory protection unit (MPU) 17, 109
configuration registers 109
merge operation 55
Message-Queuing Telemetry Transport (MQTT) protocol 238
microcontrollers 7
components 5
development boards 204
low-power operating modes 192
power, measuring 204
microcontroller unit (MCU) 5, 143
Micro IP (uIP) 221
Mobile Ad Hoc Networks (MANETs) 230
Most Significant Bit (MSB) 178
move special from register (msr) 82
MPU Control Register 109
MPU Region Attribute and Size Register 109
MPU Region Number Register 109
MPU Type Register 109
multi-stage system
mutexes 269
mutex (mutual exclusion) 273
N
Nested Vector Interrupt Controller (NVIC) 17, 118
network interfaces 212
Non-Secure Callable (NSC) 296
Non-Secure (NS) execution domain 295
Non-secure applications
O
one-time static allocation 288
on-the-go (OTG) mode 14
OpenOCD target
Open On-Chip Debugger (OpenOCD) 38
Optimized Link-State Routing (OLSR) 231
P
pending interrupt register (PR) 144
PendSV 247
peripherals 12
peripherals’ interrupt configuration 119, 120
phase-locked loop (PLL) 120
Physical Layer Transceiver (PHY) 212
POSIX tool 22
power
measuring 204
power down in deep sleep (PDDS) mode 194
preemption 244
preemptive scheduler 255
priority inheritance 274
priority inversion 273
Process Stack Pointer (PSP) 274
program counter (PC) 250
pulse-wave modulation (PWM) 12
Pulse Width Modulation (PWM) 137
registers 139
Q
R
R0-R3 250
Raw Interrupt Status (RIS) register 125
real-time clocks (RTCs) 191
real-time operating systems (RTOSs) 128
real-time processing 4
real-time systems 4
reduced instruction set computer (RISC) 16
refactoring 63
reference board 204
reference platform 16
characteristics 16
Cortex-M microprocessor 17, 18
Regulator Voltage-Scaling Output Selection (VOS) 194
Reload Value Register (RVR) 127
URL 48
repository control platforms 56
Reset and Clock Control (RCC) register 121
REST
architectural pattern 238, 239
REST-based communication 237
revision control system 54
rings 292
rising trigger select register (RTSR) 144
S
Secure access
configuring, to peripherals 302, 303
Secure application entry point 304, 305
SAU_CTRL 298
SAU_RBAR 298
SAU_RLAR 298
SAU_RNR 298
scheduler implementation 252
concurrency and timeslices 255, 256
cooperative scheduler 254, 255
I/O events, waiting from specific resources 262-264
securable peripherals 302
Secure Encrypted Virtualization (SEV) 293
Secure Gateway (SG) 305
Secure (S) execution domain 295
Secure Socket Layer (SSL) 15, 234
Security Attribution Unit (SAU) 297
regions 299
security considerations
hardware cryptography 62
software cryptography 61
untrusted code, running 62
vulnerability management 60, 61
sem_trywait function 270
events sequence 270
sequence registers (SQRs) 148
serial clock (SCL) 13
serial communication 154
clock and symbol synchronization 155
peripherals, programming 156
serial data (SDA) 13
Serial Peripheral Interface (SPI) bus 13, 167
interrupt-based SPI transfers 175
transceiver, programming 168-171
Serial Peripheral Interface (SPI) controller 119
serial ports 12
Sigfox 218
Slave Select Output Enable (SSOE) 169
slave select (SS) signal 13
Software Guard Extensions (SGX) 292
software interrupt enable register (SWIER) 144
source code organization 57
stack frame 248
stack pointer limit (SPLIM) register 296
START condition 177
static priority-driven preemptive scheduling 265
STM32F746-Discovery target 38
STOP condition 177
Store Register Exclusive (STREX) 270
SVCall 247
Secure watermarks 300
Secure-world elf file 309
symmetric cryptography 61
synchronization 269
mutex 273
priority inversion 273
system configuration 188
hardware design 188
voltage control 192
System Control Block (SCB) 17
System Control Register (SCR) 193
flag fields 193
System-on-Chip (SoC) 5
system resource separation 274
memory segmentation strategies, integrating in scheduler 276-279
privilege levels, implementing 274-276
system call interface, implementing 279-282
system resources separation, TrustZone-M 296
block-based SRAM protection 301, 302
flash memory 300
secure access, configuring to peripherals 302, 303
secure watermarks 300
system time 120
clock distribution 126
flash wait states, adjusting 121
SysTick
bit 0 128
bit 1 128
bit 2 128
T
tags 55
task management 244
TCP/IP 14
test-driven development (TDD) 43
text editors
versus integrated environments 28
timekeeping 120
toolchain 20
Transport Layer Security (TLS) 15, 59, 212, 232, 233
socket communication, securing 234-237
True Random Number Generators (TRNGs) 62
Trusted Execution Environment (TEE) 16, 291, 292
TrustZone 293
TrustZone-A 293
TrustZone-aware peripherals 302
enabling 304
example, building 303
example, running 303
non-secure execution domain 295, 296
reference platform 294
secure execution domain 295, 296
TrustZone S Controller (TZSC) 302
two-level segregate fit (TLSF) allocator 288
U
UART-based asynchronous serial bus 157
controller, programming 158-161
data, receiving 164
interrupt-based input/output 165-167
UART Bit Rate Register (BRR) 159
UART Configuration Registers (CRxs) 159
UART_Data Register (DR) 159
UART Status Register (SR) 159
unicore-mx 58
Universal Asynchronous Receiver-Transmitter (UART) 12
Universal Serial Bus (USB) 13, 14
V
validation 43
functional tests 43
hardware tools 44
Vector Table Offset Register (VTOR) 82
version control system (VCS) 54
Virtual Memory Address (VMA) 75
W
wait for event (WFE) instruction 193
wait for interrupt (WFI) instruction 193
wake-up flag (WUF) 194
wake-up time intervals 203
key register 149
prescale register 150
reload register 150
status register 150
Weightless 218
WFI(wait for interrupt) assembly instruction 129
wolfBoot 87
wolfMQTT 238
wolfSSL 233
workflow
overview 20