IBM Z Functional Matrix
This IBM® Redpaper™ publication provides a list of features and functions that are supported on IBM Z, including the IBM z15TM (z15) - Machine types 8561 and 8562, IBM z14TM (z14) - Machine types 3906 and 3907, IBM z13® (z13), IBM z13s®(z13s).
|
IBM Z® Naming: The IBM Z server generations described in this paper are available as the following machine types and models:
•Machine Type 8561 (M/T 8561) Model T01, further identified as IBM z15 Model T01.
•Machine Type 8562 (M/T 8562) Model T02, further identified as IBM z15 Model T02.
In the remainder of this document, IBM z15™ (z15) refers to both machine types (8561 and 8562), unless otherwise specified.
•Machine Type 3906 (M/T 3906), Models M01, M02, M03, M04, and M05, which are further identified as IBM z14 Model M0x, or z14 M0x.
•Machine Type 3907 (M/T 3907), Model ZR1, which are further identified as IBM z14 Model ZR1, or z14 ZR1.
In the remainder of this document, IBM z14™ (z14) refers to both machine types (3906 and 3907), unless otherwise specified.
•Machine Type 2964 (M/T 2964), further identified as IBM z13®
•Machine Type 2965 (M/T 2965), further identified as IBM z13s
|
On June 30, 2019 the IBM z13 and z13s were withdrawn form marketing (WDMF) - see ther following Announcement letter:
This means orderings are not possible for:
•All new build models for z13 and z13s
•All hardware MES changes for z13 and z13s
•All upgrades to the IBM z13 from the IBM zEnterprise® 196 (z196) or IBM zEnterprise EC12 (zEC12)
•All upgrades to the IBM z13s from the IBM zEnterprise 114 (z114) or IBM zEnterprise BC12 (zBC12)
Field installed features and all associated conversions that are delivered solely through a modification to the machine's Licensed Internal Code (LIC) are still possible until June 30, 2020:
This publication is divided into the following topics:
|
Note: This publication is not intended to include services, requests for price quotation (RPQs), or specific quantities or measurements that are related to performance, memory size, bandwidth, and so on. The intention of this publication is to compare the standard and optional features for the various IBM Z configurations. For more information about the features and functions that are listed in the tables, see the system-specific reference guide documentation.
|
This IBM Redpaper publication helps readers understand the connectivity alternatives that are available when planning and designing their IBM Z infrastructures.
The following key is used in the tables in this IBM Redpaper publication:
•S: Standard
•O: Optional
•n: Not supported
•na: not applicable
•CF: Carry forward only
|
Statements of Direction (SoD): IBM’s statements regarding its plans, directions, and intent are subject to change or withdrawal without notice at IBM’s sole discretion. Information regarding potential future products is intended to outline our general product direction and it should not be relied on in making a purchasing decision. The information regarding potential future products is not a commitment, promise, or legal obligation to deliver any material, code, or functionality. Information about potential future products may not be incorporated into any contract. The development, release, and timing of any future features or functionality described for our products remain at our sole discretion.
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Application programming interfaces
IBM Z allows independent system management software vendors and customers to develop system management applications that provide integrated hardware and software system management solutions by using the console programming interfaces. Detailed information that includes console application programming interfaces (API) objectives, architecture, data structures, usage, and console-managed object definitions and identifications is provided. An API is a set of routines, protocols, and tools that are used for building software applications.
The API interfaces provide the capability to use object-based, industry-standard programming interfaces instead of building home-grown, release-specific programs for collecting the hardware information that is needed to provide an integrated hardware and software system management solution. The firmware support for APIs is listed in Table 1.
Table 1 Firmware support for APIs
|
Application programming interface (API)
|
z15
|
z14
|
z13
|
z13s
|
|
Hardware Management Console Web Services (Web Services)1
|
S
|
S
|
S
|
S
|
|
Simple Network Management Protocol (SNMP)
|
S
|
S
|
S
|
S
|
|
Secure Service Container (SSC)
|
S
|
S
|
S2
|
S
|
|
Base Control Program internal interface (BCPii)
|
S
|
S
|
S
|
S
|
|
Ability to use APIs to access Unified Resource Manager function
|
n
|
S
|
S
|
S
|
|
Hardware Management Console Common Information Model (CIM)
|
n
|
n
|
S
|
S
|
1 Web Services are disabled by default for security reasons.
2 For more information about feature support, see the latest z13 HMC driver-level information.
Cryptographic features
The hardware cryptographic services that are provided in IBM Z are intended to cover the full range of cryptographic operations that are needed for modern world applications from the functional and performance standpoints.
The Trusted Key Entry (TKE) workstation is another optional feature that consists of an IBM-specific workstation that provides a highly secure environment for the centralized management of the Crypto Express features (in one or more systems) to which the TKE workstation has TCP/IP connectivity.
For more information about TKE hardware support, see Table 3 on page 8.
For more information about TKE hardware support, see Table 3 on page 8.
The following types of hardware cryptographic features are available to be installed in IBM Z:
•The CP Assist for Cryptographic Functions (CPACF): This feature is implemented as a functional extension to IBM Z.
•The Crypto Express feature: This optional feature is plugged into the system’s I/O extensions.
The cryptographic features, functions, and attributes are listed in Table 2.
Table 2 Cryptography
|
Cryptographic features, functions, or attributes
|
z15 T01
|
z15 T02
|
z14 M0x
|
z14 ZR1
|
z13
|
z13s
|
|
Secure Hash Standard SHA1
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Secure Hash Standard SHA2
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Secure Hash Standard SHA3
|
S
|
S
|
S
|
S
|
n
|
n
|
|
SHAKE support for 128-, and 256 bit
|
S
|
S
|
S
|
S
|
n
|
n
|
|
CP Assist Cryptographic Function (CPACF)1
|
||||||
|
CPACF feature enablement
|
O
|
O
|
O
|
O
|
O
|
O
|
|
Advanced Encryption Standard (AES)
AES-128; AES-192, 256; |
S
|
S
|
S
|
S
|
S
|
S
|
|
Data Encryption Standard (DES); TDES
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Message authentication code (MAC)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
True Random Number Generation (TRNG)
|
S
|
S
|
S
|
S
|
n
|
n
|
|
Deterministic Random Number Generation (DRNG)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Pseudo Random Number Generator (PRNG)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Cipher Message with CFB (KMF)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Cipher Message with Counter (KMCTR)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Cipher Message with OFB (KMO)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Crypto Express features
|
||||||
|
Common Crypto-Express features functionality (CPACF must be enabled)
|
||||||
|
Common Cryptographic Architecture (CCA)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Concurrent internal code changes on segment 3 to add/update a CCA application
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Compute Intermediate Message Digest (CIMD)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Elliptic Curve Cryptography (ECC)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Enable/Disable the encrypt DEA key or encrypt AES key function using the Support Element (SE)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Europay MasterCard Visa (EMV)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Protected key CPACF for high-performance data encryption
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Remote key loading for ATM/POS
|
S
|
S
|
S
|
S
|
S
|
S
|
|
RSA – Optimal Asymmetric Encryption Padding (OAEP) method with SHA-256
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Secure Keyed-Hash Message Authentication Code (HMAC)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
TR-31 wrapping method for secure key exchange
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Crypto Express7 featuresa
|
||||||
|
Crypto Express7 feature
|
O
|
O
|
n
|
n
|
n
|
n
|
|
AES GMAC, AES GCM, AES XTS, CMAC
|
S
|
S
|
na
|
na
|
na
|
na
|
|
ECDSA, ECDH
|
S
|
S
|
na
|
na
|
na
|
na
|
|
Enterprise Public Key Cryptography Standards #11 (EP11)
|
S
|
S
|
na
|
na
|
na
|
na
|
|
Max, domains
|
85
|
40
|
na
|
na
|
na
|
na
|
|
Max. operational key part registers
|
512
|
512
|
na
|
na
|
na
|
na
|
|
Payment Card Industry (PCI) Hardware Security Module (HSM) PCI-HSM
|
S
|
S
|
na
|
na
|
na
|
na
|
|
Prime Number Generator (PNG)
|
S
|
S
|
na
|
na
|
na
|
na
|
|
Secure AES Galois Counter Mode (GCM) encryption mode
|
S
|
S
|
na
|
na
|
na
|
na
|
|
True Random Number Generation (TRNG)
|
S
|
S
|
na
|
na
|
na
|
na
|
|
Visa Data Secure Platform P2PE
|
S
|
S
|
na
|
na
|
na
|
na
|
|
Visa Format Preserving Encryption
|
S
|
S
|
na
|
na
|
na
|
na
|
|
Crypto Express6 featuresa
|
||||||
|
Crypto Express6 feature
|
CF
|
CF
|
O
|
O
|
n
|
n
|
|
AES GMAC, AES GCM, AES XTS, CMAC
|
S
|
S
|
S
|
S
|
na
|
na
|
|
ECDSA, ECDH
|
S
|
S
|
S
|
S
|
na
|
na
|
|
Enterprise Public Key Cryptography Standards #11 (EP11)
|
S
|
S
|
S
|
S
|
na
|
na
|
|
Max, domains
|
85
|
40
|
85
|
40
|
na
|
na
|
|
Max. operational key part registers
|
512
|
512
|
512
|
512
|
na
|
na
|
|
Payment Card Industry (PCI) Hardware Security Module (HSM) PCI-HSM
|
S
|
S
|
S
|
S
|
na
|
na
|
|
Prime Number Generator (PNG)
|
S
|
S
|
S
|
S
|
na
|
na
|
|
Secure AES Galois Counter Mode (GCM) encryption mode
|
S
|
S
|
S
|
S
|
na
|
na
|
|
True Random Number Generation (TRNG)
|
S
|
S
|
S
|
S
|
na
|
na
|
|
Visa Data Secure Platform P2PE
|
S
|
S
|
S
|
S
|
na
|
na
|
|
Visa Format Preserving Encryption
|
S
|
S
|
S
|
S
|
na
|
na
|
|
Crypto Express5 featuresa
|
||||||
|
Crypto Express5 feature
|
CF
|
CF
|
CF
|
CF
|
O
|
O
|
|
AES GMAC, AES GCM, AES XTS, CMAC
|
S
|
S
|
S
|
S
|
S
|
S
|
|
ECDSA, ECDH
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Enterprise Public Key Cryptography Standards #11 (EP11)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Max, domains
|
85
|
40
|
85
|
40
|
85
|
40
|
|
Max. operational key part registers
|
512
|
512
|
512
|
512
|
512
|
512
|
|
Prime Number Generator (PNG)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Secure AES Galois Counter Mode (GCM) encryption mode
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Visa Data Secure Platform P2PE
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Visa Format Preserving Encryption
|
S
|
S
|
S
|
S
|
S
|
S
|
|
TKEa
|
||||||
|
TKE additional smart cards
|
O
|
O
|
O
|
O
|
O
|
O
|
|
TKE Smart Card Reader
|
O
|
O
|
O
|
O
|
O
|
O
|
|
TKE Tower or TKE workstation
|
O
|
O
|
O
|
O
|
O
|
O
|
|
TKE Rack Mounted
|
O
|
O
|
O
|
O
|
n
|
n
|
|
TKE 9.2 Licensed Internal Code
|
S
|
S
|
S
|
S
|
n
|
n
|
|
PCI-compliant with CCA 6.3
|
S
|
S
|
S
|
S
|
na
|
na
|
|
TKE 9.1 Licensed Internal Code or
TKE 9.0 LIC (superseded by TKE 9.1 LIC)
|
CF
|
CF
|
CF
|
CF
|
S
|
S
|
|
CF
|
CF
|
CF
|
CF
|
CF
|
CF
|
|
|
Key material copy to alternative zone
|
S
|
S
|
S
|
S
|
n
|
n
|
|
Save TKE data directory structure with files to USB
|
S
|
S
|
S
|
S
|
n
|
n
|
|
Create key parts without opening a host
|
S
|
S
|
S
|
S
|
n
|
n
|
|
Heartbeat audit record
|
S
|
S
|
S
|
S
|
n
|
n
|
|
Audit Log for Privileged Mode Access ID
|
S
|
S
|
S
|
S
|
n
|
n
|
|
Secure key entry on EP11
|
S
|
S
|
S
|
S
|
n
|
n
|
|
X.509 certificates manager for domains
|
S
|
S
|
S
|
S
|
n
|
n
|
|
Domain mode management
|
S
|
S
|
S
|
S
|
n
|
n
|
|
Set clock
|
S
|
S
|
S
|
S
|
n
|
n
|
|
Domain-specific Host Crypto Module Audit Log management
|
S
|
S
|
S
|
S
|
n
|
n
|
|
Domain-specific roles and authorities
|
S
|
S
|
S
|
S
|
n
|
n
|
|
TKE 8.1 Licensed Internal Code or
TKE 8.0 LIC (superseded by TKE 8.1 LIC)
|
CF
|
CF
|
CF
|
CF
|
S
|
S
|
|
CF
|
CF
|
CF
|
CF
|
CF
|
CF
|
|
|
Domain Cloning
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Certificate Authority Wizards
(smart card wizards creating for TKE zone and for configuration migrations)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Coordinated Master Key roll from TKE
|
S
|
S
|
S
|
S
|
S
|
S
|
|
TKE 7.3 Licensed Internal Code
|
CF
|
CF
|
CF
|
CF
|
CF
|
CF
|
1 This feature is optional. If it is present, the related functionality is characterized hereafter.
Table 3 shows the supported feature codes of the TKE related to the License Internal Code (LIC) release and the different Crypto Express features.
For some functionality, requirements must be considered; for example, the characterization of a Crypto Express adapter in EP 11 mode always requires the use of a TKE.
The TKE is unaware of the CPC type where the host crypto module is installed. That is, the TKE does not consider whether a Crypto Express is running on z15, 14, or z13, or z13s system. Therefore, the LIC can support any CPC where the coprocessor is supported, but the TKE LIC must support the specific crypto module.
Table 3 TKE Compatibility Matrix
|
TKE workstation
|
TKE Release LIC
|
7.31
|
8.0a
|
8.1a
|
9.0
|
9.1
|
9.2
|
|
HW Feature Code
|
0842
|
0847
|
0847 or
0097
|
0085 or
0086
|
0085 or
0086
|
0087 or
0088
|
|
|
LICC
|
0872
|
0877
|
0878
|
0879
|
0880
|
0881
|
|
|
Smart Card Reader
|
0885
|
0891
|
0891
|
0895
|
0895
|
0895
|
|
|
Smart Card
|
0884
|
0892
|
0892
|
0892
|
0892
|
0892
|
|
|
Manage Host Crypto Module
|
CEX7C (CCA)
|
no
|
no
|
no
|
no
|
no
|
Yes
|
|
|
CEX7P (EP11)
|
no
|
no
|
no
|
no
|
no
|
Yes
|
|
|
CEX6C (CCA)
|
no
|
no
|
no
|
Yes
|
Yes
|
Yes
|
|
|
CEX6P (EP11)
|
no
|
no
|
no
|
Yes
|
Yes
|
Yes
|
|
|
CEX5C (CCA)
|
Yes
|
Yes
|
Yes
|
Yes
|
Yes
|
Yes
|
|
|
CEX5P (EP11)
|
Yes
|
Yes
|
Yes
|
Yes
|
Yes
|
Yes
|
1 The TKE workstation FC 0842 or 0847 that is running LIC 7.3, or 8.x can be upgraded to TKE LIC V9.2 by adding a 4786 cryptographic adapter.
I/O characteristics
The system input/output (I/O) operations for IBM Z are handled by the channel subsystem (CSS). The role of the CSS is to control communication between internal or external channels and control units and devices.
From a central processor standpoint, the CSS is independent of the processors of the mainframe host. Therefore, I/O within a mainframe host can be done asynchronously. This requirement is critical in a system that is designed to handle massive numbers of concurrent transactions.
The current mainframe technology of IBM provides large servers with the ability to handle a high volume of transactions and I/O operations in parallel. Because of this ability, IBM Z configurations can serve many network nodes that are geographically dispersed across the world while handling a high volume of input and output operations to disk storage, printers, and other attached computers. The I/O characteristics are listed in Table 4.
Table 4 I/O characteristics
|
I/O features, functions, or attributes
|
z15 T01
|
z15 T02
|
z14 M0x
|
z14 ZR1
|
z13
|
z13s
|
|
Cancel Subchannel (XSCH)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Dynamic I/O configuration
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Dynamic I/O configuration for standalone CF1
|
S
|
S
|
S
|
S
|
n
|
n
|
|
Dynamic reconnect
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Fiber Quick Connect (FQC)
|
O
|
O
|
O
|
O
|
O
|
O
|
|
I/O drawers2
|
n
|
n
|
n
|
n
|
O
|
O
|
|
Nondisruptive I/O removal
|
S
|
S
|
S
|
S
|
S
|
S
|
|
PCIe I/O drawersb
|
n
|
n
|
O
|
n
|
O
|
O
|
|
PCIe+ I/O drawerb
|
O
|
O
|
n
|
O
|
n
|
n
|
|
System-initiated CHPID reconfiguration
|
S
|
S
|
S
|
S
|
S
|
S
|
|
IBM z/OS® discovery and autoconfig (zDAC)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Hardware Management Console
|
||||||
|
Physical HMC appliance (tower or rack mounted)
|
O, CF
|
O, CF
|
O
|
O
|
O
|
O
|
|
Hardware Management Appliance (FC 0100)
|
O3
|
Oc
|
na
|
na
|
na
|
na
|
|
Integrated Console functions at HMC
|
||||||
|
Integrated 3270 console
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Integrated ASCII console
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Java Applets based implementations
|
n
|
n
|
n
|
n
|
S
|
S
|
|
Secure 3270
|
S
|
S
|
S
|
S
|
n
|
n
|
|
Logical Channel Subsystems (LCSS): up to 256 CHPIDs per LCSS
|
||||||
|
Multiple image facility (MIF)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Support of LCSS (max. supported)
|
S(6)
|
S(3)
|
S(6)
|
S(3)
|
S(6)
|
S(3)
|
|
Subchannel sets per LCSS (max. supported)
|
S(4)
|
S(3)
|
S(4)
|
S(3)
|
S(4)
|
S(3)
|
|
CHPID Type HYL
|
||||||
|
zHyperLink read support
|
S
|
S
|
S
|
S
|
n
|
n
|
|
zHyperLink write support
|
S
|
S
|
S
|
S
|
n
|
n
|
|
zHyperLink Express
|
||||||
|
zHyperLink Express 1.1 (FC 0451)
|
O
|
O
|
n
|
n
|
n
|
n
|
|
zHyperLink Express (FC 0431)
|
CF
|
CF
|
O
|
O
|
n
|
n
|
|
IBM FICON® functionality5
|
||||||
|
CHPID Type FC
|
||||||
|
FICON multihop cascaded directors (max 4)
|
S
|
S
|
S
|
S
|
S6
|
S
|
|
FICON CTC
|
S
|
S
|
S
|
S
|
S
|
S
|
|
FICON Dynamic Routing (FIDR)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
FICON purge path extended
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Forward Error Correction (FEC) for
FICON Express16S and newer
|
S
|
S
|
S
|
S
|
S
|
S
|
|
High-Performance FICON for IBM z Systems (zHPF)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
High FICON (zHPF)
Extended Distance II
|
S
|
S
|
S
|
S
|
S
|
S
|
|
MIDAW facility
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Number of devices per FICON channel
|
32 K
|
32 K
|
32 K
|
32k
|
32 K
|
32 K
|
|
IBM Fibre Channel Endpoint Security (FC 1146)7
|
O8
|
n
|
na
|
na
|
na
|
na
|
|
CHPID Type FCP
|
||||||
|
FCP channels – T10-DIF support
|
S
|
S
|
S
|
S
|
S
|
S
|
|
FCP full-fabric connectivity to SCSI storage devices
|
S
|
S
|
S
|
S
|
S
|
S
|
|
FCP program directed restart
|
S
|
S
|
S
|
S
|
S
|
S
|
|
FCP SCSI IPL
|
S
|
S
|
S
|
S
|
S
|
S
|
|
FCP support for IBM z/VM®, IBM z/VSE® and Linux on IBM Z (attach to SCSI devices)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
N_Port ID Virtualization (NPIV) for FCP
|
S
|
S
|
S
|
S
|
S
|
S
|
|
WWPN prediction tool for virtual ports
|
S
|
S
|
S
|
S
|
S
|
S
|
|
WWPN prediction tool for physical ports
|
S
|
S
|
S
|
S
|
S
|
S
|
|
IBM Fibre Channel Endpoint Security (FC 1146)g
|
Oh
|
n
|
na
|
na
|
na
|
na
|
|
FICON Express16SA9 (8, 16 Gbps)
|
||||||
|
10 KM LX (2 ports) FC 0436
|
O
|
n
|
n
|
n
|
n
|
n
|
|
SX (2 ports) FC 0437
|
O
|
n
|
n
|
n
|
n
|
n
|
|
FICON Express16S+i (4, 8, 16 Gbps)
|
||||||
|
10 KM LX (2 ports) FC 0427
|
CF
|
O, CF
|
O
|
O
|
n
|
n
|
|
SX (2 ports) FC 0428
|
CF
|
O, CF
|
O
|
O
|
n
|
n
|
|
FICON Express16S (4, 8, 16 Gbps)
|
||||||
|
10 KM LX (2 ports) FC 0418
|
CF
|
CF
|
CF
|
CF
|
O
|
O
|
|
SX (2 ports) FC 0419
|
CF
|
CF
|
CF
|
CF
|
O
|
O
|
|
FICON Express8S (2, 4, 8 Gbps)
|
||||||
|
10 KM LX (2 ports) FC 0409
|
CF
|
CF
|
CF
|
CF
|
O
|
O
|
|
SX (2 ports) FC 0410
|
CF
|
CF
|
CF
|
CF
|
O
|
O
|
|
FICON Express8 (2, 4, 8 Gbps)
|
||||||
|
10 KM LX (4 ports) FC 3325
|
n
|
n
|
n
|
n
|
CF
|
CF
|
|
SX (4 ports) FC 3326
|
n
|
n
|
n
|
n
|
CF
|
CF
|
|
Open Systems Adapter functionalitye
|
||||||
|
640 TCP/IP address
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Checksum offload
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Display OSAINFO for z/OS
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Inbound workload queuing for z/OS
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Large send
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Link aggregation for z/VM
|
S
|
S
|
S
|
S
|
S
|
S
|
|
OSA dynamic LAN idle
|
S
|
S
|
S
|
S
|
S
|
S
|
|
OSA-Express Network Traffic Analyzer
|
S
|
S
|
S
|
S
|
S
|
S
|
|
PCI-IN (PCIe Interconnect®)
|
O
|
O
|
O
|
O
|
O
|
O
|
|
Virtual MAC address support
|
S
|
S
|
S
|
S
|
S
|
S
|
|
VLAN mgmt - GVRP support
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Supported CHPID types
|
||||||
|
CHPID type OSC for integrated console controller (ICC) at all 1000BASE-T Ethernet features
|
S
|
S
|
S
|
S
|
S
|
S
|
|
CHPID type OSC for integrated console controller (ICC) for OSA-Express7S GbE features
|
S
|
n
|
na
|
na
|
na
|
na
|
|
OSA-ICC support for Secure Sockets Layer
|
S
|
S
|
S
|
S
|
S
|
S
|
|
CHPID type OSD (for QDIO) supported on all OSA-Express features
|
S
|
S
|
S
|
S
|
S
|
S
|
|
QDIO data connection isolation
|
S
|
S
|
S
|
S
|
S
|
S
|
|
QDIO Diagnostic Synchronization facility
|
S
|
S
|
S
|
S
|
S
|
S
|
|
QDIO Optimized latency mode for the z/OS environment
|
S
|
S
|
S
|
S
|
S
|
S
|
|
QDIO Layer 2/Layer 3
|
S
|
S
|
S
|
S
|
S
|
S
|
|
CHPID type OSE for non QDIO at all 1000BASE-T Ethernet features
|
S
|
S
|
S
|
S
|
S
|
S
|
|
CHPID type OSM for intranode management network (INMN) at all 1000BASE-T Ethernet features
|
n10
|
nj
|
S
|
S
|
S
|
S
|
|
CHPID type OSN for network control program (NCP) at all OSA-Express 1000BASE-T Ethernet and OSA-Express3 GbE features
|
n
|
n
|
n
|
n
|
S
|
S
|
|
CHPID type OSX for all 10 GbE features
|
n
|
n
|
S
|
S
|
S
|
S
|
|
CHPID type OSX for 25 GbE11 features
|
n
|
n
|
S
|
S
|
n
|
n
|
|
Open Systems Adapter-Express7S (OSA-Express7S)
|
||||||
|
25 Gigabit Ethernet SR1.1 (1 port) FC 044912
|
O
|
n
|
O
|
O
|
n
|
n
|
|
25 Gigabit Ethernet SR (1 port) FC 0429l
|
CF
|
O
|
O
|
O
|
n
|
n
|
|
10 Gigabit Ethernet LR (1 port) FC 0444
|
O
|
n
|
n
|
n
|
n
|
n
|
|
10 Gigabit Ethernet SR (1 port) FC 0445
|
O
|
n
|
n
|
n
|
n
|
n
|
|
1000BASE-T Ethernet (2 ports /1 CHPID) FC 0446
|
O
|
n
|
n
|
n
|
n
|
n
|
|
Gigabit Ethernet LX (2 ports/1 CHPID) FC 0442
|
O
|
n
|
n
|
O
|
n
|
n
|
|
Gigabit Ethernet SX (2 ports/1 CHPID) FC 0443
|
O
|
n
|
n
|
n
|
n
|
n
|
|
Open Systems Adapter-Express6S (OSA-Express6S)
|
||||||
|
10 Gigabit Ethernet LR (1 port) FC 0424
|
CF
|
O, CF
|
O
|
O
|
n
|
n
|
|
10 Gigabit Ethernet SR (1 port) FC 0425
|
CF
|
O, CF
|
O
|
O
|
n
|
n
|
|
1000BASE-T Ethernet (2 ports /1 CHPID) FC 0426
|
CF
|
O, CF
|
O
|
O
|
n
|
n
|
|
Gigabit Ethernet LX (2 ports/1 CHPID) FC 0422
|
CF
|
O, CF
|
O
|
O
|
n
|
n
|
|
Gigabit Ethernet SX (2 ports/1 CHPID) FC 0423
|
CF
|
O, CF
|
O
|
O
|
n
|
n
|
|
Open Systems Adapter-Express5S (OSA-Express5S)
|
||||||
|
10 Gigabit Ethernet LR (1 port) FC 0415
|
CF
|
CF
|
CF
|
CF
|
O
|
O
|
|
10 Gigabit Ethernet SR (1 port) FC 0416
|
CF
|
CF
|
CF
|
CF
|
O
|
O
|
|
1000BASE-T Ethernet (2 ports /1 CHPID) FC 0417
|
CF
|
CF
|
CF
|
CF
|
O
|
O
|
|
Gigabit Ethernet LX (2 ports/1 CHPID) FC 0413
|
CF
|
CF
|
CF
|
CF
|
O
|
O
|
|
Gigabit Ethernet SX (2 ports/1 CHPID) FC 0414
|
CF
|
CF
|
CF
|
CF
|
O
|
O
|
|
Open Systems Adapter-Express4S (OSA-Express4S)
|
||||||
|
10 Gigabit Ethernet LR (1 port) FC 0406
|
n
|
n
|
n
|
CF
|
CF
|
CF
|
|
10 Gigabit Ethernet SR (1 port) FC 0407
|
n
|
n
|
n
|
CF
|
CF
|
CF
|
|
1000BASE-T Ethernet (2 ports/1 CHPID) FC 0408
|
n
|
n
|
CF
|
n
|
CF
|
CF
|
|
Gigabit Ethernet LX (2 ports/1 CHPID) FC 0404
|
n
|
n
|
n
|
CF
|
CF
|
CF
|
|
Gigabit Ethernet SX (2 ports/1 CHPID) FC 0405
|
n
|
n
|
n
|
CF
|
CF
|
CF
|
|
IBM HiperSockets™
|
||||||
|
32 HiperSockets
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Completion queue function
|
S
|
S
|
S
|
S
|
S
|
S
|
|
IPv6 support
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Integration with intraensemble data network (IEDN)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Layer 2 support
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Multiple Write facility
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Network Traffic Analyzer
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Flash Express
|
||||||
|
Flash Express FC 040313
|
n
|
n
|
n
|
n
|
O
|
O
|
|
Shared Memory Communications
|
||||||
|
25 GbE RoCE Express2.1 FC 0450
|
O
|
O
|
n
|
n
|
n
|
n
|
|
10 GbE RoCE Express2.1 FC 0432
|
O
|
O
|
n
|
n
|
n
|
n
|
|
25 GbE RoCE Express2 FC 0430k
|
CF
|
CF
|
O
|
O
|
n
|
n
|
|
10 GbE RoCE Express2 FC 0412
|
CF
|
CF
|
O
|
O
|
n
|
n
|
|
10 GbE RoCE Express FC 0411
|
CF
|
|
CF
|
CF
|
O
|
O
|
|
Shared Memory Communications-Remote Direct Memory Access (SMC-R)14.
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Shared Memory Communications-Direct Memory Access (SMC-D)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
zEnterprise Data Compression Express (zEDC)
|
||||||
|
zEnterprise Data Compression Express FC 0420
|
n15
|
n
|
O
|
O
|
O
|
O
|
1 With z14 Driver Level 36 or z15 Driver Level 41, Dynamic I/O for standalone CF CPCs is available and HCD PTFs.
2 At least one PCIe I/O drawer, I/O drawer, or I/O cage is required, depending on the system (except certain configurations which are used as standalone Coupling Facility).
3 New orders ONLY. Cannot be added as an MES. Supports N-2 generations.
4 Support for zHyperLink Writes requires compatible levels of DS8880/F hardware and firmware R8.5.1, as well as Db2® 12 with PTFs.
5 This feature is optional. If it is present, the related functionality is characterized hereafter.
6 Check the latest z13 HMC driver level information for feature support.
7 Requires FC 3863 (CPACF enablement); subject to export regulations.
8 FICON Express16SA - Encryption of Data in Flight and Endpoint Authentication; FICON Express 16S+ - only Endpoint Authentication
9 Both ports on this FCION Express feature must be defined as the same CHPID type (FC or FCP)
10 CHPID type OSM is not available for definitions in user configurations. This CPID type is used in DPM mode for internal management only.
11 Requires z14 Driver Level 36.
12 Requires 25GbE switch. Does not negotiate to 10Gbps.
13 Virtual Flash Memory replaces FC0403 on z14 and later platforms. For more information, see IBM z14 Technical Guide, SG24-8451.
14 One OSA Express fearure defined for TCP communications must be present.
15 For z15 server generation (M/T 8561, 8562) the FC 0420 PCIe feature has been replaced by the on-chip IBM Integrated Accelerator for zEnterprise Data Compression.
On-demand functions
Capacity Upgrade on Demand (CUoD) is an inherent capability of the current IBM Z architecture. It allows you to concurrently add capacity and features to the IBM Z hardware. Concurrence depends on the hardware.
Customer Initiated Upgrade (CIU) is a tool that supports clients ordering permanent and temporary upgrades for their IBM Z hardware. It helps to provide CUoD. CUoD upgrades can be ordered through CIU or by using the standard IBM Sales/MES order process.
Athough all CIU upgrades support CUoD, not all CUoD capabilities are available through CIU. For example, a new drawer for IBM Z hardware can be ordered and installed concurrently. This capability is part of the CUoD capabilities of IBM Z. However, it cannot be ordered by using CIU. For more information, see the CIU column in Table 5.
Capacity for Planned Event (CPE), Capacity Backup (CBU), and On/Off Capacity on Demand (OOCoD) are temporary upgrade capabilities that allow clients to add capacity to their processor. These upgrades are all part of CUoD. Only one CUoD upgrade capability is available through CIU, which is On/Off CoD.
The available on-demand functions are listed in Table 5.
Table 5 On-demand functions
|
On-Demand function
|
CIU
|
z15 T01
|
z15 T02
|
z14 M0x
|
z14 ZR1
|
z13
|
z13s
|
|
Capacity Upgrade on Demand (CUoD)
|
|||||||
|
API for capacity provisioning management (CPM)
|
n/a
|
O
|
O
|
S
|
S
|
S
|
S
|
|
Capacity Backup (CBU)
|
O
|
O
|
O
|
O
|
O
|
O
|
O
|
|
Capacity for Planned Event (CPE)
|
O
|
O
|
O
|
O
|
O
|
O
|
O
|
|
CIU-Express with extended staging
|
O
|
O
|
O
|
O
|
O
|
O
|
O
|
|
Concurrent memory upgrades
|
O
|
O
|
O
|
O
|
O1
|
O
|
O
|
|
Concurrent permanent processor upgrade
|
O
|
O
|
O
|
O
|
O2
|
O
|
n
|
|
Concurrent processor CPC drawer add
|
n
|
O
|
O
|
O
|
n
|
O
|
n
|
|
Concurrent upgrades while temporary capacity is active
|
O
|
O
|
O
|
O
|
O
|
O
|
O
|
|
Flexible memory
|
n
|
O
|
O
|
O
|
n
|
O
|
n
|
|
High Water Mark (HWM)
Increase total model capacity and IFLs without changing the active model capacity and IFLs
|
O
|
O
|
O
|
O
|
O
|
O
|
O
|
|
On/Off Capacity on Demand (OOCoD)
|
S
|
O
|
O
|
O
|
O
|
O
|
O
|
|
Plan ahead memory
|
n
|
n
|
n
|
O
|
O
|
O
|
O
|
|
Up to 8 installed or active (On/Off CoD, CBU, CPE) records at any specific time
|
O
|
S
|
S
|
S
|
S
|
S
|
S
|
|
|
|||||||
|
Capacity Backup (CBU): Temporary upgrade
|
|||||||
|
Ability to replenish an ordered record to extend the expiration date, add processing resources, order tests, and restore real activation
|
S
|
S
|
S
|
S
|
S
|
S
|
|
|
Ability to select the contract length 1 - 5 years
|
S
|
S
|
S
|
S
|
S
|
S
|
|
|
Automatic deactivation at expiration date
|
S
|
S
|
S
|
S
|
S
|
S
|
|
|
CPs, IFLs, ICFs, zIIPs, and SAPs
|
O
|
O
|
O
|
O
|
O
|
O
|
|
|
Manufacturing installation of up to four CPE and CBU records, when ordered
|
S
|
S
|
S
|
S
|
S
|
S
|
|
|
Maximum of 15 test activations (free and purchased) per CBU record
|
S
|
S
|
S
|
S
|
S
|
S
|
|
|
Number of free test activations equates to the number of years purchased with the CBU record
|
S
|
S
|
S
|
S
|
S
|
S
|
|
|
Replenishment/Reuse record
|
S
|
S
|
S
|
S
|
S
|
S
|
|
|
Subcapacity CBU processors
|
O
|
O
|
O
|
S
|
O
|
O
|
|
|
Uninstalled LICCC records can be staged on the Support Element
|
O
|
O
|
O
|
S
|
O
|
O
|
|
|
Capacity for Planned Event (CPE): Temporary upgrade
|
|||||||
|
CPs, IFLs, ICFs, zIIPs, and SAPs
|
O
|
O
|
O
|
O
|
O
|
O
|
|
|
Manufacturing installation of up to four CPE and CBU records when ordered
|
S
|
S
|
S
|
S
|
S
|
S
|
|
|
Nondisruptive hardware CP capacity setting changes
|
S
|
S
|
S
|
S
|
S
|
S
|
|
|
Select model capacity and type/quantity of engines based on business needs
|
S
|
S
|
S
|
S
|
S
|
S
|
|
|
On/Off Capacity on Demand (On/Off CoD): Temporary upgrade
|
|||||||
|
Ability to replenish an ordered record
|
S
|
S
|
S
|
S
|
S
|
S
|
|
|
Administrative On/Off CoD testing
|
S
|
S
|
S
|
S
|
S
|
S
|
|
|
API for On/Off CoD activation
|
S
|
S
|
S
|
S
|
S
|
S
|
|
|
Automatic deactivation at expiration date
|
S
|
S
|
S
|
S
|
S
|
S
|
|
|
Automatic renewal to extend expiration date
|
O
|
O
|
O
|
O
|
O
|
O
|
|
|
CPs, IFLs, ICFs, zIIPs, and SAPs
|
O
|
O
|
O
|
O
|
O
|
O
|
|
|
On/Off CoD test
|
S
|
S
|
S
|
S
|
S
|
S
|
|
|
On/Off CoD with extended staging
|
O
|
O
|
O
|
O
|
O
|
O
|
|
|
Post-paid upgrades with spending limits controlled by tokens
|
O3
|
Oc
|
O
|
O
|
O
|
O
|
|
|
Prepaid upgrades controlled by tokens
|
Oc
|
Oc
|
O
|
O
|
O
|
O
|
|
|
Replenishment/Reuse record
|
S
|
S
|
S
|
S
|
S
|
S
|
|
|
Subcapacity engine support
|
S
|
S
|
S
|
S
|
S
|
S
|
|
|
Uninstalled LICCC records can be staged on the Support Element
|
O
|
O
|
O
|
O
|
O
|
O
|
|
|
System Recovery Boost Upgrade (temporary records, pre-paid)
|
|||||||
|
System Recovery Boost Upgrade - zIIP records for temporary capacity boost
|
O
|
n
|
n
|
n
|
n
|
n
|
|
|
Tailor Fit Pricing for IBM Z Hardware
|
|||||||
|
Tailor Fit Pricing for IBM Z - HW Consumption solution4
|
O
|
O
|
n
|
n
|
n
|
n
|
|
1 Memory upgrades are concurrent only if there is enough physical memory installed (LICCC upgrades only). Max. physical memory installed depends on the CPC drawer feature.
2 Concurrent processor upgrades are possible only if there are installed but not active processors available (LICCC upgrades only). Max. number of processors installed depends on the CPC drawer feature.
3 SOD: Beginning with z15, new prepaid OOCoD tokens purchased will not carry forward to future systems.
4 Pre- or post-paid; Requires contract. CP only.
IBM Parallel Sysplex
IBM Parallel Sysplex® was introduced with the coupling facility (CF) and coupling links for high-speed communication, with IBM MVS™ V5.1 operating system support with the mainframe models in 1994. With the IBM Parallel Sysplex technology, you can harness the power of up to 32 z/OS systems, yet make these systems behave as a single, logical computing facility. Also, the underlying structure of the Parallel Sysplex remains virtually transparent to users, networks, applications, and even operations.
To realize these benefits, the z/OS Parallel Sysplex combines two critical capabilities: Parallel processing and enabling read/write data sharing across multiple systems with full data integrity.
This combination makes the z/OS Parallel Sysplex unique from every other system, solution, and architecture that is available today. The Parallel Sysplex matrix is listed in Table 6.
Table 6 Parallel Sysplex
|
Parallel Sysplex
|
z15 T01
|
z15 T02
|
z14 M0x
|
z14 ZR1
|
z13
|
z13s
|
|
BCPii interface
|
S
|
S
|
S
|
S
|
S
|
S
|
|
CFLevel=24
|
S
|
S
|
n
|
n
|
n
|
n
|
|
CFCC Fair Latch Manager
|
S
|
S
|
n
|
n
|
n
|
n
|
|
CFCC Message Path Resilience Enhancement
|
S
|
S
|
n
|
n
|
n
|
n
|
|
CF Monopolization Avoidance
|
S
|
S
|
n
|
n
|
n
|
n
|
|
CFLevel=23
|
n
|
n
|
S1
|
S
|
n
|
n
|
|
CFLevel=22
|
n
|
n
|
S
|
S
|
n
|
n
|
|
CFLevel=21
|
n
|
n
|
n
|
n
|
S
|
S
|
|
CFLevel=20
|
n
|
n
|
n
|
n
|
S
|
n
|
|
Coupling facility dynamic dispatch ON/OFF
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Coupling Facility Thin Interrupt
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Coupling facility shared processors
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Integrated Coupling Facility (ICF)
|
O
|
O
|
O
|
O
|
O
|
O
|
|
128-bit TOD clock
|
S
|
S
|
S
|
S
|
S
|
S
|
|
z/VM guest coupling
|
S
|
S
|
S
|
S
|
S
|
S
|
|
z/OS recovery process boost2
|
S
|
S
|
n
|
n
|
n
|
n
|
|
Coupling Links features for Parallel Sysplex clustering
|
||||||
|
Integrated Coupling Adapter (ICA SR1.1)
(2 port/8 CHPIDs) FC 0176
|
O
|
O
|
n
|
n
|
n
|
n
|
|
Integrated Coupling Adapter (ICA SR)
(2 ports/8 CHPIDs) FC 0172
|
CF
|
CF
|
O
|
O
|
O
|
O
|
|
Coupling Express Long Reach (2 ports/8 CHPIDs) FC 0433
|
O, CF
|
O, CF
|
O, CF
|
O, CF
|
O3
|
O
|
|
Internal Coupling link (IC)4
|
S
|
S
|
S
|
S
|
S
|
S
|
|
HCA3-O LR fanout for 1xIFB (4 ports/16 CHPIDs) FC 0170
|
n
|
n
|
O
|
n
|
O
|
O
|
|
HCA3-O fanout for 12x IFB (2 ports/8 CHPIDs) FC 0171
|
n
|
n
|
O
|
n
|
O
|
O
|
|
Server Time Protocol (STP)5
|
||||||
|
Graphical setup and configuration at the HMC
|
S6
|
Sf
|
S
|
S
|
n
|
n
|
|
CTN Dynamic Split or Merge7
|
S
|
S
|
S
|
S
|
n
|
n
|
|
Additional stratum level (4)
|
S
|
S
|
S
|
S
|
n
|
n
|
|
Continuous availability of NTP servers
|
S
|
S
|
S
|
S
|
S
|
S
|
|
HMC used as an NTP server8
|
S
|
S
|
S
|
S
|
S
|
S
|
|
NTP server with pulse per second (PPS)9
|
S
|
S
|
S
|
S
|
S
|
S
|
|
NTP client
|
S
|
S
|
S
|
S
|
S
|
S
|
|
IEEE 1588 Precision Time Protocol (PTP) support as External Time Source
|
S10
|
Sj
|
n
|
n
|
n
|
n
|
|
PTP server with pulse per second (PPS)
|
Sj
|
Sj
|
n
|
n
|
n
|
n
|
|
Improved STP recovery and availability when an Internal Battery Feature (IBF) is installed on one or more servers in the CTN
|
S
|
S11
|
S
|
Sk
|
S
|
S
|
|
Going away signal to improve recovery12
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Enhanced Console Assisted Recovery
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Save STP configuration and time information across power-on resets (POR) or power outages for a single or dual server STP-only CTN
|
S
|
S
|
S
|
S
|
S
|
S
|
|
z/OS messaging when events occur related to accessing an ETS
|
S
|
S
|
S
|
S
|
S
|
S
|
1 CFCC Level 23 is delivered with z14 Driver Level 36.
2 Short duration boost for speeding up sysplex recovery; based on System Recovery Boost functionality. Requires OS opt-in.
3 For more information about feature support, see the latest z13 HMC driver level information.
4 64 per CPC for z15, up from 32 per CPC for previous generations
5 This feature is optional. If it is present, the related functions are characterized hereafter.
6 Setting up STP for a z15 requires HMC 2.15.0. Support element (Driver 41) Syspex Timer task has been discontinued.
7 Requires HMC 2.14.1 or newer.
8 The HMC must be at level 2.10.1 for an STP-only CTN to obtain its external time source from an NTP server defined on the HMC.
9 Not available when the HMC is used as NTP server.
10 Requires PTP capable infrastructure (including networking support). Requires PPS for highest CTN accuracy.
11 IBF feature is not available for this CPC
12 Available on HCA-3O and ICA SR Coupling.
Performance
The IBM Mainframe was the computing workhorse for large organizations for many years. These organizations realized that they can reduce their total cost of ownership (TCO) by tuning the workloads that are running on the mainframe. TCO also can be significantly reduced by implementing various performance and other enhancements that are provided by new releases of IBM mainframe.
Workload capacity performance is sensitive to three major factors: Instruction path length, instruction complexity, and memory hierarchy.
The IBM Z configurations are designed to deliver the highest levels of performance and capacity for large-scale consolidation and growth. Attributes and design points of the IBM Z systems that contribute to overall performance and throughput are listed in Table 7.
Table 7 Performance
|
Performance
|
z15 T01
|
z15 T02
|
z14 M0x
|
z14 ZR1
|
z13
|
z13s
|
|
16 floating point registers
|
S
|
S
|
S
|
S
|
S
|
S
|
|
64-bit addressing
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Branch and set authority facility
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Compare and move extended facility
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Data software compression
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Data hardware compression (CMPSC)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
IBM Integrated Accelerator for zEDC
|
S
|
S
|
n
|
n
|
n
|
n
|
|
IBM Integrated Accelerator for Z SORT
|
S
|
S
|
n
|
n
|
n
|
n
|
|
IBM Db2® Sort facility
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Dedicated move page engine
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Dynamic CF dispatching
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Dynamic Address Translation (DAT)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Enhanced Move Page/VM
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Extended translation facility
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Extensions for virtual machine (VM)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Flexible memory configurations1
|
O
|
n
|
O
|
n
|
O
|
n
|
|
Floating point instruction2
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Hardware decimal floating point facility
|
S
|
S
|
S
|
S
|
S
|
S
|
|
HFP square root instructionb
|
S
|
S
|
S
|
S
|
S
|
S
|
|
HiperDispatch function
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Immediate and relative instructionb
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Large Page Support
|
S
|
S
|
S
|
S
|
S
|
S
|
|
1 MB large page support (pageable)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
2 GB large page support
|
O
|
O
|
O
|
O
|
O
|
O
|
|
Level 1 cache size (Instruction/Data in kB)
|
128/128
|
128/128
|
128/128
|
128/128
|
96/128
|
96/128
|
|
Level 2 cache size (Instruction/Data in MB)
|
4/4
|
4/4
|
2/4
|
2/4
|
2/2
|
2/2
|
|
Level 3 cache size (in MB)
|
256
|
256
|
128
|
128
|
64
|
64
|
|
Level 4 cache size (in MB)
|
960
|
960
|
672
|
672
|
430
|
430
|
|
Logical string assist
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Long displacement facility
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Number of cores per processor unit3
|
12
|
124
|
10
|
10
|
8
|
8
|
|
Move page
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Runtime Instrumentation
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Out of Order Instruction Execution
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Perform locked operation facility
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Plan ahead memory
|
n
|
n
|
O
|
O
|
O
|
O
|
|
Processor frequency (Ghz)
|
5.2
|
4.5
|
5.2
|
4.5
|
5.0
|
4.3
|
|
Server/Application State Protocol (SASP) support for load balancing across virtual servers
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Start Interpretive Execution (SIE)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Superscalar
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Suppression on protection facility
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Simultaneous Multi Threading (SMT) on zIIPs, IFLs, and SAPs
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Single Instruction Multiple Data (SIMD)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
System Recovery Boost5
|
S
|
S
|
n
|
n
|
n
|
n
|
|
System Recovery Boost Upgrade (FC 6802)
|
O
|
n
|
n
|
n
|
n
|
n
|
|
IBM z Integrated Information Processors (zIIPs)
|
O
|
O
|
O
|
O
|
O
|
O
|
|
Transactional Memory
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Trimodel addressing
|
S
|
S
|
S
|
S
|
S
|
S
|
|
zHyperLink support
|
S
|
S
|
S
|
S
|
n
|
n
|
|
Maximum supported memory (in TB)6
|
40
|
16
|
32
|
8
|
10
|
4
|
1 Flexible Memory is an option for multi-drawer systems to alleviate memory requirements when a CPC drawer is replaced (concurrently).
2 For more information, see Principles of Operation, SA22-7832.
3 By chip design. The maximum number of cores is not available on all PUs SCMs (Single Chip Module).
4 12 cores by design; 7-11 active cores
5 Requires Operating System opt-in
6 The maximum amount of memory depends on the number of CPC drawers. The values in this row pertain to the maximum number of CPC drawers.
Processor Resource/Systems Manager
IBM introduced Processor Resource/Systems Manager™ (PR/SM™) in 1988 with the IBM 3090 processors. It consists of hardware electronics and microcode that is built into IBM mainframes that support logical partitions (LPARs). LPARs allow you to run multiple system images on a single processor complex. Each image includes a full complement of CPUs (dedicated or shared), main storage, expanded storage, and channels. Channels can be shared across images by using the multiple image facility (MIF) feature.
The PR/SM functionality ensures the highest level of optimized resources usage and an unparalleled utilization in the IT world of the IBM Z near to 100%. The main characteristics of PR/SM for the z15, z14 M0x, z14 ZR1, z13, and z13s are listed in Table 8 on page 23.
Table 8 PR/SM
|
PR/SM
|
z15 T01
|
z15 T02
|
z14 M0x
|
z14 ZR1
|
z13
|
z13s
|
|
128-bit TOD clock
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Absolute capping support of PUs (all types)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Absolute capping support of an LPAR Group
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Add/delete logical partition name
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Automatic Reconfiguration Facility (ARF)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Defined capacity I/O
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Dynamic Memory Management
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Dynamic storage reconfiguration
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Dynamic PU reassignment
|
S
|
S
|
S
|
S
|
S
|
S
|
|
EAL5 certification1
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Dynamic Partition Manager (DPM)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
HSA size (in GB)
|
256
|
160
|
192
|
64
|
96
|
40
|
|
Hypervisor support for virtualization: z/VM
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Hypervisor support for virtualization: KVM
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Individual management of PU types
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Logical partition time offset
|
S
|
S
|
S
|
S
|
S
|
S
|
|
LPAR group capacity limit
|
S
|
S
|
S
|
S
|
S
|
S
|
|
LPAR management time report
|
S
|
S
|
S
|
S
|
S
|
S
|
|
LPAR preferred path
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Max number of configurable processors
|
190
|
65
|
170
|
30
|
141
|
20
|
|
Max number of CPs
|
190
|
6
|
170
|
6
|
141
|
6
|
|
Max number of supported LPARs
|
85
|
40
|
85
|
40
|
85
|
40
|
|
Max number of supported LCSS
|
6
|
3
|
6
|
3
|
6
|
3
|
|
Max number of subchannel sets per LCSS
|
4
|
3
|
4
|
3
|
4
|
3
|
|
Simultaneous multithreading (SMT) for IFLs, zIIPs, and SAPs
|
S
|
S
|
S
|
S
|
S2
|
Sb
|
|
Single Instruction Multiple Data (SIMD)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Single storage pool
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Secure Service Container (SSC)
|
S
|
S
|
S
|
S
|
S3
|
S
|
|
Secure Execution for Linux4
|
O
|
O
|
n
|
n
|
n
|
n
|
|
Intelligent Resource Directory (IRD)
|
||||||
|
Channel subsystem priority queuing
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Dynamic Channel Path Management (DCM)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
LPAR CPU management
|
S
|
S
|
S
|
S
|
S
|
S
|
1 Common Criteria EAL5 certification for the security of the LPARs that run under the control of PR/SM is in process.
2 SMT not enabled for SAPs (IFLs and zIIPs only).
3 Check the latest z13 HMC driver level information for support.
4 Secure Execution for Linux for second level Linux guests (FC 0115)
Reliability, availability, and serviceability
The IBM Z design is focused on providing higher availability by reducing planned and unplanned outages, which is commonly known as Reliability, availability, and serviceability (RAS). RAS can be accomplished by using improved concurrent replace, repair, and upgrade functions for processors, memory, drawers, and I/O. RAS also extends to the nondisruptive capability for installing Licensed Internal Code (LIC) updates.
As an extension to the RAS capabilities, environmental controls are implemented in the system to help reduce power consumption and meet cooling requirements. Continuous improvements in RAS are associated with new features and functions to ensure that IBM Z machines deliver exceptional value.
The main RAS features of the z15, z14 M0x, z14 ZR1, z13, and z13s are listed in Table 9.
Table 9 RAS functionality
|
RAS
|
z15 T01
|
z15 T02
|
z14 M0x
|
z14 ZR1
|
z13
|
z13s
|
|
50/60 Hz power
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Three-phase AC power
|
S
|
O
|
S
|
n
|
S
|
O
|
|
DC power
|
n
|
n
|
O
|
n
|
O
|
O
|
|
Ability to display and track historical power, temperature, and utilization data
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Alternate HMC
|
O
|
O
|
O
|
O
|
O
|
O
|
|
Alternate Support Element
|
S
|
O
|
S
|
S
|
S
|
S
|
|
Hardware Management Appliance (FC 0100)
|
O1
|
O
|
n
|
n
|
n
|
n
|
|
Bolt down kit for low-raised floor and high-raised floor installation
|
O
|
O
|
O
|
O
|
O
|
O
|
|
Bolt down kit for nonraised floor installation
|
O
|
O
|
O
|
O
|
O
|
O
|
|
Concurrent channel adapter add
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Concurrent book/processor drawer add
|
S
|
S2
|
S
|
n
|
S
|
n
|
|
Concurrent PCIe I/O drawer add
|
Sc
|
Sc
|
S
|
S3
|
S
|
S
|
|
Dynamic Fabric repair (CP-SC and SC-SC)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Concurrent PU conversions
|
O
|
O
|
O
|
O
|
O
|
O
|
|
Console Integration (CI)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Digitally signed firmware provided by the HMC and SE
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Dynamic change to partition cryptographic coprocessor configuration
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Dynamic add of a logical processor to an LPAR
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Dynamic LCSS add without preplanning
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Dynamic memory bit lane sparing
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Dynamic memory sparing4
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Dynamic oscillator switchover
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Dynamic partition add without preplanning
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Dynamic subchannel set add without preplanning
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Enhanced application preservation
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Enhanced drawer availability (EDA) for processor drawer5
|
S
|
S
|
S
|
n
|
S
|
n
|
|
Fault tolerant design
|
S
|
S
|
S
|
S
|
S
|
S
|
|
FCP program directed IPL
|
O
|
O
|
O
|
O
|
O
|
O
|
|
FICON channel link error problem analysis
|
S
|
S
|
S
|
S
|
S
|
S
|
|
FICON dynamic routing (FIDR)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
FICON forward error correction (FEC) for FICON Express16S
|
S
|
S
|
S
|
S
|
S
|
S
|
|
FICON link incident reporting
|
O
|
S
|
O
|
O
|
O
|
O
|
|
FICON SAN Fabric I/O Priority for WLM
|
S
|
S
|
S
|
S
|
S
|
S
|
|
FICON multihop cascaded directors (max number of directors)
|
4
|
4
|
4
|
4
|
4
|
4
|
|
Fixed HSA
|
S
|
S
|
S
|
S
|
S
|
S
|
|
HMC and SE IPv6 support
|
S
|
S
|
S
|
S
|
S
|
S
|
|
HMC FCP Problem Determination panels
|
S
|
S
|
S
|
S
|
S
|
S
|
|
HMC instant messenger
|
S
|
S
|
S
|
S
|
S
|
S
|
|
I/O interface reset
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Internal Battery Feature (IBF)
|
O
|
n
|
O
|
n
|
O
|
O
|
|
IPL from alternative subchannel set
|
S
|
S
|
S
|
S
|
S
|
S
|
|
LICCC memory upgrade
|
S
|
S
|
S
|
S
|
S
|
S
|
|
LICCC processor upgrade
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Memory RAIM
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Monitor and track power consumption, internal temperature, and utilization data of the CPC using monitor dashboard task on the HMC
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Multipath IPL - with z/OS
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Nondisruptive I/O removal
|
S
|
S
|
S
|
S
|
S
|
S
|
|
N+1 power supplies
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Partial CP restart
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Partial memory restart
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Power - balanced power
|
O
|
n
|
O
|
n
|
O
|
O
|
|
Power - dual power feeds
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Power - plan ahead power cords
|
O
|
n
|
O
|
n
|
O
|
O
|
|
Power consumption estimator tool (IBM Resource Link®)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Precheck function to detect conflicts between a new permanent upgrade and any active temporary resources
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Processor drawer degradation mode
|
S
|
S
|
S
|
S
|
S
|
S
|
|
PU sparing (if spare available, config dependent)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
SAP reassignment
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Sparing for storage protect keysd
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Subspace group facility
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Subsystems storage protect
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Symbol Error Correction Code (ECC) on L4 cache
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Symbol Error Correction Code (ECC) on L3 cache configuration array
|
S
|
S
|
S
|
S
|
S
|
S
|
|
System-initiated CHPID reconfiguration
|
S
|
S
|
S
|
S
|
S
|
S
|
|
System-managed CF structure duplexing
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Top exit I/O cabling
|
O
|
O
|
O
|
O
|
O
|
O
|
|
Top exit power cabling
|
O
|
O
|
O
|
O
|
O
|
O
|
|
Water manifold for processor cooling as FRU
|
S
|
n
|
S
|
n
|
S
|
n
|
|
Worldwide port name (WWPN) tool to help with preplanning and setting up SAN environment before installation
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Concurrent maintenance
|
||||||
|
Channel - Adapter
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Cooling units (water cooled6 or air cooled)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
S
|
S
|
S
|
n
|
S
|
S
|
|
|
Enhanced driver maintenance
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Hardware Management Console (HMC)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Flash Express cards
|
na
|
na
|
na
|
na
|
S
|
S
|
|
IFB-MP
|
na
|
na
|
O
|
n
|
O
|
O
|
|
I/O drawer
|
na
|
na
|
n
|
n
|
S
|
S
|
|
Oscillator
|
S
|
S
|
S
|
S
|
S
|
S
|
|
PCIe I/O drawer or PCIe+ I/O drawerc
|
S
|
S
|
S
|
S
|
S
|
S
|
|
PCI-IN (PCIe Interconnect)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Point of Load (POL) - CPC drawer power regulators
|
Sh
|
S
|
S
|
S8
|
S
|
S
|
|
Single Chip Modules (SCM)
|
S
|
Se
|
S
|
S
|
S
|
S
|
|
Support Element (SE)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Concurrent MCL apply
|
||||||
|
CFCC9
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Channel features
|
||||||
|
CE LR
|
S
|
S
|
S
|
S
|
S10
|
S
|
|
Crypto-Express
|
S
|
S
|
S
|
S
|
S
|
S
|
|
FICON-Express
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Flash Express
|
na
|
na
|
na
|
na
|
S
|
S
|
|
IC
|
S
|
S
|
S
|
S
|
S
|
S
|
|
ICA SR
|
S
|
S
|
S
|
S
|
S
|
S
|
|
IFB
|
na
|
na
|
S
|
na
|
S
|
S
|
|
OSA-Express
|
S
|
S
|
S
|
S
|
S
|
S
|
|
zHyperLink
|
S
|
S
|
S
|
S
|
n
|
n
|
|
Hardware Management Console (HMC)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Processor types
|
||||||
|
CP
|
S
|
S
|
S
|
S
|
S
|
S
|
|
SAP
|
S
|
S
|
S
|
S
|
S
|
S
|
|
ICF
|
S
|
S
|
S
|
S
|
S
|
S
|
|
IFL
|
S
|
S
|
S
|
S
|
S
|
S
|
|
IFP
|
S
|
S
|
S
|
S
|
S
|
S
|
|
zIIP
|
S
|
S
|
S
|
S
|
S
|
S
|
|
Support Element (SE)
|
S
|
S
|
S
|
S
|
S
|
S
|
|
PU core engineering data
|
S
|
S
|
S
|
S
|
S
|
S
|
1 Hardware Management Console running on the Support Element hardware; Available with initial order only (no MES)
2 From z15 T02 Max31 to Max65 only; Other upgrades are disruptive.
3 The z15, and z14 ZR1 is housed in a industry standard, 19-inch format frame. A new PCIe+ I/O drawer (capable of hosting up to 16 PCIe features) was designed and built to fit the 19-inch rack. z15 and z14 ZR1 does not support PCIe I/O drawer (capable of hosting 32 PCIe features).
4 Sparing can be done with steering or marking technology.
5 Two or more CPC drawers installed only.
6 z15 T01, z14 M0x, and z13 only.
7 Applies to multiple processor drawer systems only.
8 z14 ZR1 uses, and z15 can use as an option redundant, hot swappable Power Supply Units (PSUs)
9 Might require reactivation of CFCC.
10 Check the latest z13 HMC driver level information for support.
Authors
This paper was produced by a team of specialists from around the world working at the IBM Redbooks, Poughkeepsie Center.
Frank Packheiser is a Senior zIT Specialist at the Field Technical Sales Support office in Germany. He has over 25 years of experience in IBM Z. Frank has worked for 10 years in the IBM Education Center in Germany, developing and providing professional training. He also provides professional services to IBM Z and mainframe clients. In 2008 and 2009, Frank supported clients in Middle East/North Africa (MENA) as a zIT Architect. In addition to co-authoring several IBM Redbooks® publications since 1999, he has been an official ITSO presenter at ITSO workshops since 2010.
Octavian Lascu is an IBM Redbooks Project Leader and a Senior IT Consultant for IBM Romania with over 25 years of experience. He specializes in designing, implementing, and supporting complex IT infrastructure environments (systems, storage, and networking), including high availability and disaster recovery solutions and high-performance computing deployments. He has developed materials for and taught over 50 workshops for technical audiences around the world. He is the author of several IBM publications.
Bill White is an IBM Redbooks Project Leader and Senior Networking and Connectivity Specialist at IBM Redbooks, Poughkeepsie Center.
Thanks to the following people for their contributions to this project:
Michael Groetzner
Joyce Anne Porter
Garry Sullivan
Dave Surman
Marna Walle
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