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Appendix A: Postcodes

Postcodes are a sign of life on embedded systems. A postcode is typically a small number that designates where in the startup of the firmware or its “power on self test” the firmware has last reached. Typically, all embedded devices are flashed with released versions of system firmware, which means postcodes are the only possible way to detect any failures. Depending on the endpoint, postcodes could be either 1 or 2 bytes in width. Each system firmware uses its own implementation of postcodes to report device boot state. Tables A-1 and A-2 list the postcodes used in the FSP specification and Table A-3 lists coreboot as the boot firmware. Table A-4 lists postcodes when coreboot and FSP work in hybrid mode.

Table A-1

Generic FSP Postcodes

FSP API: TempRamInit
Postcode	Description
0x0000	TempRamInit API Entry
0x007F	TempRamInit API Exit
FSP API: FspMemoryInit
0xD800	FspMemoryInit API Entry
0xD87F	FspMemoryInit API Exit
0xDC00	Pre-Mem Entry
0xDC7F	Pre-Mem Exit
FSP API: TempRamExit
0xB800	TempRamExit API Entry
0xB87F	TempRamExit API Exit
FSP API: FspSiliconInit
0x9800	FspSiliconInit API Entry
0x987F	FspSiliconInit API Exit
0x9C00	Post-Mem Entry
0x9C7F	Post-Mem Exit
FSP API: NotifyPhase
0x6800	NotifyPhase API Entry
0x687F	NotifyPhase API Exit

Table A-2

Platform-Specific FSP Postcodes (Subject to Change)

Postcode	Description
0xDA00	Pre-Mem SaInit Entry
0xDA01	DeviceConfigurePreMem Start
0xDA06	Programming SA BARs
0xDA08	Install SA HOBs
0xDA10	Initializing DMI
0xDA50	Initializing Graphics
0xDB00	PCH API Entry
0x9A00	Post-Mem SaInit Entry
0x9A01	DeviceConfigure Start
0x9A03	Initializing Pei Display
0x9A05	CallPpiAndFillFrameBuffer
0x9A06	GraphicsPpiInit
0x9A07	GraphicsPpiGetMode
0x9A61	Set BIOS_RESET_CPL to indicate all configurations complete
0x9A63	GraphicsPmInit Start
0x9B01 - 0x980D	Post-Mem Device Configuration
0x9B40	Post-Mem OnEndOfPEI Entry
0x9B4F	Post-Mem OnEndOfPEI Exit

Table A-3

coreboot Generic Postcodes

Postcode	Description
0x01	Reset Vector jumps into correct code segment
0x10	Entry into protected mode
0x11	Prior ramstage is loaded into memory (decompressed if compressed before copying)
0x12	Represents the end of romstage (ramstage is copied into memory and about to jump there)
0x13	Entry into ramstage
0x34	Pre-memory init preparation start
0x36	Pre-memory init preparation end
0x39	Console is initialized and is ready to use
0x40	Console boot message has successfully transmitted
0x60	Prior enabling the cache
0x6e	Pre call to ramstage main() function
0x6f	Starting of ramstage (represents ramstage has loaded and executed successfully)
0x70	Boot State Machine: Before device probe
0x71	Boot State Machine: Initialize chips
0x72	Boot State Machine: Start device enumeration
0x73	Boot State Machine: Device resource allocation
0x74	Boot State Machine: Device enable
0x75	Boot State Machine: Device initialization
0x76	Boot State Machine: Device probe
0x77	Boot State Machine: OS resume check
0x78	Boot State Machine: OS resume
0x79	Boot State Machine: Write tables
0x7a	Boot State Machine: Load payload
0x7b	Boot State Machine: Boot payload
0x96	Indicates entry into ACPI _PTS control method
0x97	Indicates entry into ACPI _WAK control method
0xe1	Invalid or corrupt CBFS
0xe4	Hardware initialization failure
0xe5	TPM state or failure during communication
0xee	Entry into dead code (function that shouldn’t have returned)
0xef	Resume from suspend failure
0xf3	Jumping to payload
0xfd	Successfully able to resume from suspend
0xfe	Successfully able to boot to OS
0xff	Error code attached with boot stage or payload

Table A-4

coreboot Postcodes with FSP in Hybrid Mode

0x88	Prior calling FSP Notify phase (End of Firmware)
0x89	After calling FSP Notify phase (End of Firmware)
0x90	Before calling FSP TempRamInit
0x91	Before calling FSP TempRamExit
0x92	Before calling FSP Memory Init
0x93	Before calling FSP Silicon Init
0x94	Before calling FSP Notify phase (after PCI enumeration)
0x95	Before calling FSP Notify phase (ready to boot)
0x98	After calling FSP Memory Init
0x99	After calling FSP Silicon Init
0xa0	Before calling FSP Multiphase Silicon Init
0xa1	After calling FSP Multiphase Silicon Init

Appendix B: Data Types

In the type-based system programming language that is used for system firmware development, such as C, a data type represents the attribute of the data. Every bootloader has its own way to tell the compiler how they intended to use the data. Each bootloader implements its own data types, so developers need to have an understanding of the different data types used by popular open source bootloaders, such as EFI/UEFI or coreboot, while working on architecture migration from closed source firmware projects. Tables B-1 and B-3 provide a high-level overview of the most common data types and modifiers in system firmware development. Table B-2 lists unique EFI data types. When adding new compiler support using these bootloaders, developers should be aware of which file to locate, such as the file ProcessorBind.h in EDKII to add UEFI data types and stdint.h in a coreboot project to add compiler-specific data types. These data types can be used to build more complex data structures.

Table B-1

Common EFI and coreboot Data Types

EFI Mnemonic	coreboot Mnemonic	Description
BOOLEAN	bool	Logical Boolean Size: 1-byte Possible Values: 1 for TRUE/true, 0 for FALSE/false
INT8	int8_t	Signed 1-byte value Min Value: 0x80 Max Value: 0x7F
UINT8	uint8_t	Unsigned 1-byte value Max Value: 0xFF
INT16	int16_t	Signed 2-byte value Min Value: 0x8000 Max Value: 0x7FFF
UINT16	uint16_t	Unsigned 2-byte value Max Value: 0xFFFF
INT32	int32_t	Signed 4-byte value Min Value: 0x8000_0000 Max Value: 0x7FFF_FFFF
UINT32	uint32_t	Unsigned 4-byte value Max Value: 0xFFFF_FFFF
INT64	int64_t	Signed 8-byte value Min Value: 0x80000000_00000000 Max Value: 0x7FFFFFFF_FFFFFFFF
UINT64	uint64_t	Unsigned 8-byte value Max Value: 0xFFFFFFFF_FFFFFFFF
INTN	intmax_t	Signed n-byte value n = 4 bytes on 32-bit and 8 bytes on 64-bit operations
UINTN	uintmax_t	Unsigned n-byte value n = 4 bytes on 32-bit and 8 bytes on 64-bit operations
CHAR8	char	1-byte character
VOID	void	Undeclared type When used in a function, referred as no return value has the return type as void. Similarly no argument value in function calls uses void argument. Using pointers represents the address of an object, which can be cast into any other data type.
Enumerated Type (Enum)		Elements inside an enum are a signed value

Table B-2

Unique EFI Data Types

EFI Mnemonic	Description
EFI_GUID	128-bit number that represents a global unique identifier. Any ppi, protocol, device, instance, and image defined in UEFI should be associated with an EFI_GUID type.
EFI_STATUS	Represents an EFI status code in INTN type. This could be a combination of success, failure, warning, and device states.

Table B-3

Common EFI and coreboot Modifiers

EFI Mnemonic	Coreboot	Description
CONST	DEVTREE_CONST	This modifier associated with a data type makes the data read only. This allows the compiler to enable optimization to generate more efficient code.
STATIC	MAYBE_STATIC_NONZERO	Having a local scope while defined in a function and defined as a variable increases its scope to lifetime while the program is running.
VOLATILE	volatile	Defines a variable as volatile and tells the compiler that it’s exempt from optimization because the value of the variable may change without any action being taken as part of the code. This data type should be used on variables accessing the hardware device.

Glossary

ACPI Advanced Configuration and Power Interface

AL After Life; in the context of this book, any runtime service that is part of system firmware is referred to as AL.

ALU Arithmetic-logic unit; a part of the CPU that performs arithmetic and logical operations on the operands. It is divided into two units, an arithmetic unit (AU) and a logic unit (LU).

AMBA Advanced Microcontroller Bus Architecture

AP Application processor; typically, in a multicore environment, any other processor cores apart from the powered-on default processor are referred to as application processors. Also, in embedded systems, application processors are referred to as the core that runs the bootstrap program.

APCB AMD PSP Control Block

ARM Advanced RISC Machine, formerly known as Acorn RISC machine

ASL ACPI source language

BAR(s) Base Address Register(s); typically used to access the device address space that is behind the host bus

BIOS Basic input/output system; in the context of this book, the bootloader, boot firmware, and payload are all part of the BIOS, which does the basic hardware initialization and boot to OS.

BIU Bus Interface Unit

BLx Boot Loader stages as part of Trusted Firmware; examples are BL1, BL2, and BL3x

BSP Boot Strap Processor, which comes out from the power-on reset and handles the platform initialization

CBFS CBFS is a scheme for managing independent blocks of data as part of ROM. Though not a true filesystem, the style and concepts are similar to the coreboot filesystem.

CCD Closed Case Debugging

CISC Complex instruction set computer architecture; the idea here is that a single instruction can perform a number of low-level operations like a load from memory or an arithmetic operation that also stores or reads from memory, hence multiple steps can be accommodated using a single instruction.

coreboot An open sourced, extended firmware platform that delivers a lightning fast and secure boot experience on embedded systems

CPU Central processing unit

CSE Intel® Converged Security Engine

CU Control unit, a component of the CPU that directs operations within the processor

DCI Intel® Direct Connect Interface

Depthcharge Depthcharge is responsible for performing the Chrome OS-specific operations required prior to boot to OS and also act as bootloader for Chrome OS

DMI Direct Media Interface, a proprietary link between the northbridge and southbridge on a computer motherboard

DSP Digital signal processors

e820 A legacy mechanism to pass the memory map from boot firmware to the operating system

eNEM enhanced NEM (No-Evict Mode)

EBC EFI Byte Code

FSP Firmware Support Package, a specification designed with standard API interface to perform silicon initialization and provide information back to the boot firmware

GCC GNU Compiler Collection

GUID Globally unique identifier, a unique identifier used in UEFI-based firmware is specified by a GUID

HOB(s) Hand-off blocks; define a way to pass information between different phases of types of boot firmware

Hybrid The term hybrid is used in the context of this book to define a firmware development model that allows open-source firmware development using limited SoC vendor provided blobs, such as coreboot. A coreboot firmware project accepts minimal boot critical SoC blobs integrated as part of the ROM image.

ICH I/O controller hub; managed data communication between the CPU and motherboard components

IDE An integrated development environment is used for software development.

IMD In-memory database; an IMD resides in the cbmem region for creating a dynamic cbmem infrastructure

IRQ Interrupt request

ISA Instruction Set Architecture, also used in bus specification as Industry Standard Architecture

LinuxBoot LinuxBoot was intended to be a firmware for modern servers that replaces specific firmware functionality like the UEFI DXE phase with a Linux kernel and runtime.

MCH Intel® Memory Controller Hub

MIPS Microprocessor without interlocked pipeline stages, a part of the RISC family

MMU Memory management unit, responsible for translating all CPU virtual addresses into physical addresses and additionally controlling memory accesses

Multithreading An environment that allows all possible processor cores to operate at same time using dedicated code and data stack without any coherency and resource conflicts

NEM No-eviction mode

Payload A separate firmware block that is responsible for booting to the kernel

PCH Peripheral Controller Hub, the next generation to ICH that controls certain data paths and support functions used in conjunction with CPUs

PCI Peripheral Component Interconnect

PCIe Peripheral Component Interconnect Express

Product Development Phase Typically, an embedded system goes through several phases starting from schematics design to the product reaching shelves. These stages are categories between Proto, Engineering Validation Test (EVT), Design Validation Test (DVT), Production Validation Test (PVT), and Mass Production (MP).

PSP AMD Platform Security Processor, used to provide the trusted execution environment

Reset Vector A 32-bit address where the CPU will start fetching the instruction post CPU reset. This address can be different between CISC and RISC architectures, and in most cases, this address is patchable using monitor code.

RISC Reduced instruction set computer architecture; the idea here is to use simple commands that can be divided into several instructions but operate within a single clock cycle.

RISC-V An open source instruction set architecture based on the RISC family

SA System agent, traditionally known as uncore. Defined as a part of a microprocessor that is not in the core but still closely connected to the core to achieve high performance.

SBL Slim Bootloader

SIMD Single instruction multiple data

SPARC Scalable Processor Architecture is a family member of RISC, originally developed by Sun Microsystems.

TF Trusted Firmware, formerly known as ARM Trusted Firmware

Tianocore An open source implementation of UEFI. In some cases, it’s used as a payload with other bootloaders, such as coreboot and SBL.

TLB Translation lookaside buffer, contains a translated entry for the virtual address and the access control logic to determine the access if permitted

TOLUD Top of lower usable DRAM

TOM Top of memory

TOUUD Top of upper usable DRAM

TSEG Top of the main memory segment; this region is used to specify the amount of memory space required while operating in System Management Mode (SMM).

UEFI Unified Extensible Firmware Interface

U-root Universal root, an open source project hosted on GitHub

UPD Updatable product data, a data structure that holds configuration regions being part of FSP binary

x86 A family member of CISC. x86 is typically used to refer to the 8086 processor family.

Reference

Websites

Coredna. What is Open Source Software?, Comparing Open Source Software vs Closed Source Software (Introduction): www.coredna.com/blogs/comparing-open-closed-source-software

Christian. Open-source-firmware-why-should-we-support-it, Alternatives for the Basic Input Output System for server or client devices (Introduction): https://hackernoon.com/open-source-firmware-why-should-we-support-it-xqdy3bjg

Abhishek Pande. ARM Processor Modes, Understanding the ARM Processor Operational Modes (Chapter 2): www.slideshare.net/abhi165/arm-modes

John Catsoulis. Designing Embedded Hardware, Explore a preview version of Designing Embedded Hardware (Chapter 2): www.oreilly.com/library/view/designing-embedded-hardware/0596007558/ch01.html

GeeksforGeeks. I/O Interface (Interrupt and DMA Mode), Understanding the method that is used to transfer information between internal storage and external I/O devices is known as I/O interface (Chapter 2): www.geeksforgeeks.org/io-interface-interrupt-dma-mode/

Deep Raj Bhujel. Functional Block Diagram of 8086 microprocessor, A simple overview of 8086 microprocessor (Chapter 2): https://deeprajbhujel.blogspot.com/2015/12/functional-block-diagram-of-8086.html

Intel Corporation. Intel 64 and IA-32 Architectures Software Developer Manuals, These manuals describe the architecture and programming environment of the Intel 64 and IA-32 architectures (Chapter 2): www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html

Alex Dzyoba. Basic X86 interrupts, Knowledge to initialIze x86 interrupts (Chapter 2): https://alex.dzyoba.com/blog/os-interrupts/

ARM Limited. Trusted Firmware Open Governance Project, The reference implementation of Secure world software for Arm architectures (Chapter 3): https://developer.arm.com/tools-and-software/open-source-software/firmware/trusted-firmware

Chromium OS. ARM Trusted Firmware Design, Understanding ARM Trusted Firmware (Chapter 3): https://chromium.googlesource.com/external/github.com/ARM-software/arm-trusted-firmware/+/v0.4-rc1/docs/firmware-design.md

Brett Daniel. Giant List of Intel’s Advanced Technologies, Intel’s processors are equipped with a multitude of technologies that can improve the overall performance of your rugged server or workstation (Chapter 3): www.trentonsystems.com/blog/giant-list-intel-advanced-technologies

Science Direct. Reset Vector, By enabling the reset Vector-Catch feature and resetting the system (Chapter 3): www.sciencedirect.com/topics/engineering/reset-vector

Coreboot GitHub. Starting from scratch, This document to guide about how to build coreboot (Chapter 4): https://doc.coreboot.org/tutorial/part1.html

TrustedFirmware.org. Trusted Firmware-A Documentation, Trusted Firmware-A (TF-A) provides a reference implementation of secure world software for Arm SoCs (Chapter 4: https://trustedfirmware-a.readthedocs.io/en/latest/

Slim Bootloader. Slim Bootloader Project Documentation, Slim Bootloader Open Source Project (version 1.0) documentation! (Chapter 4): https://slimbootloader.github.io/index.html

PhoenixTS. UEFI-vs-Legacy-BIOS, UEFI vs Legacy BIOS Booting: What’s the Difference? (Chapter 4): https://phoenixts.com/blog/uefi-vs-legacy-bios/

David Morelo. Coreboot Versus UEFI, High level difference between coreboot and UEFI (Chapter 4): https://linuxhint.com/coreboot-vs-uefi/

Universal Scalable Firmware. Linux Payload, To build a basic Linux payload conforming to universal payload standard (Chapter 6):

https://github.com/UniversalScalableFirmware/linuxpayload

Universal Scalable Firmware. Welcome to the Universal Scalable Firmware project, Universal Scalable Firmware Specification (Chapter 6): https://github.com/UniversalScalableFirmware

Tianocore. UEFI Payload for Coreboot Project, Understanding Tianocore UefiPayloadPkg (Chapter 6): https://github.com/tianocore/tianocore.github.io/wiki/Coreboot_UEFI_payload

Chromium OS Document. USB Type-C PD Firmware, Understanding firmware update for TCPC chips (Chapter 6): https://chromium.googlesource.com/chromiumos/docs/+/master/pd_firmware_update.md

LWN.net. LinuxBoot: Linux as firmware, Application for Linux as Firmware (Chapter 6 and Chapter 7): https://lwn.net/Articles/748586/

Coreboot GitHub. Starting from scratch, This document to guide about how to build coreboot (Chapter 7): https://doc.coreboot.org/tutorial/part1.html

Lowrisc. Open source silicon, Open silicon makes it easier to create derivative designs and reduces time to market, while significantly lowering the barriers to producing an SoC design (Chapter 7): www.lowrisc.org/

Subrata Banik and Barnali Sarkar, Intel Corporation. Reduce-firmware-booting-time-whitepaper, Open Source Firmware Development Reduce Firmware Booting Time Using Multi-Threaded Environment (Chapter 7): www.intel.com/content/dam/www/public/us/en/documents/white-papers/reduce-firmware-booting-time-whitepaper.pdf

FOSDEM, Intel Corporation. Capsule Update and LVFS Improving System Firmware Update (Chapter 7): https://archive.fosdem.org/2020/schedule/event/firmware_culisfu/attachments/slides/3709/export/events/attachments/firmware_culisfu/slides/3709/FOSDEM_2020_Intel_Capsule_Update.pdf

References for the Chapter 1

Books

[B-1] Jiming Sun, Vincent Zimmer, Marc Jones, Stefan Reinauer, Embedded Firmware Solutions, Apress 2015.

[B-2] Vincent Zimmer, Michael Rothman, Suresh Marisetty, Beyond BIOS: Developing with the Unified Extensible Firmware Interface, 3rd edition, DeG, 2017.

[B-3] Vincent Zimmer, Michael Rothman, Robert Hale, UEFI: From Reset Vector to Operating System, in Chapter 3 of Hardware-Dependent Software, Springer, 2009.

[B-4] Sunil Cheruvu, Anil Kumar, Ned Smith, David M. Wheeler, Demystifying Internet of Things Security, Apress, 2020.

Conferences, Journals, and Papers

[P-1] David Weston, “Hardening With Hardware”, in BlueHat 2018 https://github.com/microsoft/MSRC-Security-Research/blob/master/presentations/2018_01_BlueHatIL/BlueHatIL18_Weston_Hardening_With_Hardware.pdf

[P-2] David Weston, “Advanced Windows Security”, in Platform Security Summit 2019, www.platformsecuritysummit.com/2019/speaker/weston/

[P-3] Eclypsium, “Anatomy of a Firmware Attack”, 2019, https://eclypsium.com/2019/12/20/anatomy-of-a-firmware-attack/

[P-4] Eclypsium, “FISMA compliance firmware security best practices”, 2019, https://eclypsium.com/2019/05/13/fisma-compliance-firmware-security-best-practices/

[P-5] NIST, “Hardware-Enabled Security for Server Platforms”, in NIST whitepaper, 2020, available at https://nvlpubs.nist.gov/nistpubs/CSWP/NIST.CSWP.04282020-draft.pdf

Specifications and Guidelines

[S-1] UEFI Organization, “UEFI Specification”, 2019, available at www.uefi.org/

[S-2] UEFI Organization, “UEFI Platform Initialization Specification”, 2019, available at www.uefi.org/

[S-3] UEFI Organization, “ACPI Specification”, 2019, available at www.uefi.org/

[S-4] PCI-SIG, “PCI Express Base Specification”, 2019, https://pcisig.com/

[S-5] CXL Org, “Compute Express Link Specification”, 2019, www.computeexpresslink.org/

Websites

Tianocore. What is TianoCore?, TianoCore, the community supporting an open source implementation of the Unified Extensible Firmware Interface (UEFI): www.tianocore.org/

Coreboot. Fast, secure and flexible OpenSource firmware, an open source project that provides auditability and maximum control over technology: www.coreboot.org/

Linuxboot. Linux as Firmware, LinuxBoot is a firmware for modern servers that replaces specific firmware functionality like the UEFI DXE phase with a Linux kernel and runtime: www.linuxboot.org

Slim Booloader. Slim Bootloader Project Documentation, Welcome to Slim Bootloader Open Source Project (version 1.0) documentation!: https://slimbootloader.github.io/

U-Boot. Das U-Boot -- the Universal Boot Loader, Welcome to the Wiki area for cooperating on U-Boot development. www.denx.de/wiki/U-Boot

Intel. Intel Firmware Support Package (FSP), Intel Firmware Support Package (Intel FSP) provides key programming information for initializing Intel silicon and can be easily integrated into a boot loader of the developer’s choice: www.intel.com/FSP

GitHub. Sound Open Firmware (SOF), Sound Open Firmware is an open source community that provides an open source audio DSP firmware and SDK for audio or signal processing on modern DSPs: https://github.com/thesofproject

GitHub. Open Baseboard Management Controller (openbmc), OpenBMC is a Linux distribution for management controllers used in devices such as servers, top of rack switches or RAID appliances. https://github.com/openbmc/openbmc

GitHub. Open Power, A place to collaborate on OpenPOWER firmware related projects: https://github.com/open-power

IBM. Technical Reference for developing BIOS for IBM PC/AT Platform: http://bitsavers.informatik.uni-stuttgart.de/pdf/ibm/pc/at/6183355_PC_AT_Technical_Reference_Mar86.pdf

References for Chapter 5

ACPI. Advanced Configuration and Power Interface, version 6.0, www.uefi.org

BSF. Boot Setting File (BSF) Specification, https://firmware.intel.com/sites/default/files/BSF_1_0.pdf

EDK2. UEFI Developer Kit, www.tianocore.org

EDKII specification. A set of specifications describe EDKII DEC/INF/DSC/FDF file format, as well as EDKII BUILD. http://tianocore.sourceforge.net/wiki/EDK_II_Specifications

FSP EAS. FSP External Architecture Specification, www.intel.com/content/www/us/en/embedded/software/fsp/fsp-architecture-spec-v2.html

FSP Consumer. Yao, Zimmer, Rangarajan, Ma, Estrada, Mudusuru, A_Tour_Beyond_BIOS_Using_the_Intel_Firmware_Support_Package_with_the_EFI_Developer_Kit_II_(FSP2.0), https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-white-papers

UEFI Book. Zimmer, et al, Beyond BIOS: Developing with the Unified Extensible Firmware Interface, 2^nd edition, Intel Press, January 2011

UEFI Overview. Zimmer, Rothman, Hale, “UEFI: From Reset Vector to Operating System,” Chapter 3 of Hardware-Dependent Software, Springer, 2009.

UEFI PI Specification. UEFI Platform Initialization (PI) Specifications, volumes 1-5, Version 1.4, www.uefi.org

Index

ACPI BIOS

DSDT

post-OS boot

pre-OS boot

ACPI fixed hardware/register

ACPI namespace

ACPI platform firmware

SeeACPI BIOS

ACPI Source Language (ASL)

ACPI specification

ADD assembly instruction

Address bus

Advanced Configuration and Power Interface (ACPI)

components

hardware/register

ACPI-compliant hardware platform

fixed

generic

programming model

OSPM enabling interface

platform firmware

software specification

system description tables

system power states

Advanced Power Management (APM)

Advanced programmable interrupt controller (APIC)

Advanced RISC Machines (ARM)

Advanced technology (AT)

Advanced vector extensions (AVX)

After Life (AL)

ALU operations instructions

Always On Processor (AOP)

AMBA High-Speed Bus (AHB)

AMBA Peripheral Bus (APB)

AMD Generic Encapsulated Software Architecture (AGESA)

AmdInitEntry

AMD Opteron

Analytical Engine

AP initialization sequence

Application binary interfaces (ABIs)

Application, hybrid firmware architecture

BIOS region (coreboot)

booting, SPI NOR

Chrome OS platform

closed source blobs, pre-CPU reset flow

closed source firmware

CPU

CSE partition

current industry trend

descriptor

hardware components

host CPU initialization process

Intel SoC platform

post-memory initialization phase

pre-CPU reset flow

pre-memory initialization phase

Intel SoC SPI layout

memory controller(s)

non-boot critical firmware

open vs. closed source firmware, Intel SoC SPI

platform initialization, BIOS/coreboot region

post-memory initialization phase

ramstage operation

type-C subsystem enablement process

Application processors (APs)

Architectural MSRs

Arithmetic-logic unit (ALU)

ARM Advanced Microcontroller Bus Architecture (AMBA)

ARM CPU core hardware block diagram

ARM instruction sets

ARM memory bus architecture (AMBA)

ARM processor internals

cache

exception levels

instruction sets

MMU

processor core design

processor modes

program counter registers

program status registers

registers

RISC architecture-based CPU, 100

ARM Trusted Firmware (TF-A)

Assembly language

Base Address Register (BAR)

Baseboard management controller (BMC)

Basic input/output system (BIOS)

boot

characteristics

boot

self-supporting

simple

definition

firmware

hardware block diagram

operations

platform reset architecture

programming

Binary-based PI

Binary Configuration Tool (BCT)

Binary PI model

BIOS/coreboot region

BIOS data area (BDA)

BIOS types

coreboot

Slim Bootloader

trusted firmware

U-Boot

UEFI

BIOS work model

boot flow

drivers, 152

high-level function

intermediate layer

OS loader/payload

POST

pre-CPU reset

BIOS writer’s Guide (BWG)

BlParseLib library

Bootblock

Boot device initialization

Boot device selection (BDS)

Boot firmware

Boot firmware configuration (TB_FW_CONFIG)

Booting

Bootloader

Boot loader stages

ARM FVP platform

exception level

stage 1

stage 2

stage 3-1

stage 3-3

Boot operational phases

Boot partition (BP)

Boot Policy Manifest (BPM)

Bootstrapping

Bootstrap processor (BSP)

BSP initialization sequence

Built-in payloads

Build_rule.txt file

Bulk transfer

Bus architecture

AHB

AMBA

APB

connections

EISA bus

electrical signals

ISA bus

motherboard components

parallel/serial communication

PCI bus

SeePeripheral component interconnect (PCI) bus

PCIe bus

SATA

types

USB

Bus interface unit (BIU)

bzImage

Cache

fast memory

hit and unavailability

organizations

Cache Allocation Technology (CAT)

Cache as RAM (CAR)

Cache hierarchy

Cache memory

CBMEM

CbParseLib

Central processing unit (CPU)

Chain of trust (CoT)

ChromeOS, login screen

Chrome OS platform

Chromium OS

CISC processor architecture

Clear interrupt enable flag instruction (cli)

Closed-source binary blob

Closed source firmware development model

Cloud storage

Code segment register

Common instruction sets

Complex Instruction Set Computer (CISC)

Computer architecture

Analytical Engine

assembly language instruction

definition

embedded systems

Harvard architecture

Internals

SeeCPU internals

ISA

microarchitecture

microprocessor

system architecture

von Neumann architecture

Computer industry

Computing devices

Configuration address space

ConnectController() function

Control bus

Control flow instructions

Control logic

Control Program for Microcomputers (CP/M)

Control register (CR)

Control unit (CU)

Conventional closed source firmware

AGESA

AMD AGESA communication interface

BL1 performs platform initialization

BL31 performs platform initialization

FSP

SeeIntel Firmware Support Package (FSP)

generic TF-A boot flow

Qualcomm’s QTISECLIB, TF-A

silicon vendor-provided binaries

Conventional memory

Converged Security Engine (CSE)

coreboot

booting time

boot-time measurement

boot-time optimize

BSP

components

CPU multi-processor

Depthcharge

eMMC storage

flash

hand-off

payload-related features

PCI enumeration

SDHC

source code

static information

SYSINFO

task lists

UEFI capsule update

coreboot architecture

design

development philosophy

in 1999

overview

payloads

platform initialization (see Coreboot platform initialization boot phases)

proprietary silicon initialization binary

source tree structure

Seecoreboot code structures

coreboot code structures

common code architecture

converged IP model-based

mainboard

baseboard and variant structure

dynamic generation of ACPI table

SoC support and common code

software view

traditional motherboard development approach

SoC

coreboot file system (CBFS)

coreboot generic postcodes

coreboot platform initialization boot phases

bootblock

boot state machine

CBFS

device tree

operational diagram

payload

postcar

ramstage

romstage

runtime services

table creation, coreboot

verstage

Coreboot table

CP/M operating system

CPU architecture

BDS phase

code base

DXE phase

ELIXIR

firmware device design

goal/motivation

implementation schema

PEI phase

reasons

RISC

SEC phase

software stack

UEFI

CPU internals

ARM processor internals

x86 processor

Seex86 processor internals

CPU registers

Crosh shell

Data bus

Data of stolen memory (DSM)

Data register

Data segment register

Datasheet dependency

Data types

common EFI

unique EFI

Depthcharge

architecture

bootloader

libpayload

boot flow

code structure

faster

secure

simpler

thinner

vboot

boot modes

kernel verification

shell

Depthcharge shell

Developer mode

Device firmware

Device path

Device tree

Differentiated System Description Table (DSDT)

Direct memory access (DMA)

DMA protected range (SPR)

DRAM Power Management (DPM) firmware

Driver connection process

Driver execution environment phase (DXE)

architectural protocols

components

definition

device drivers

dispatcher

drivers

dynamic configuration

FileSystem driver

foundation

IDE BUS

network stack

operational diagram

PCI

protocols

responsibilities

Dual inline memory modules (DIMM)

DXE phase

e820 table

Early chipset initialization

EAX register

EBP register

EBX register

ECX register

EDI register

EDX register

EFI byte code (EBC)

EFI Developer Kit (EDK)

EFI Developer Kit II (EDKII)

EFI driver binding protocol

EFI system table

8086 Microarchitecture

BIU

address generation circuit

Bus Control Logic

interface access

prefetch instruction queue

elements

ALU

control system

instruction decoder

instruction register

instructions and data

evolution

internal architecture

16-bit processor

ELIXIR processor

Embedded boot loader(EBL)

Embedded controllers (EC)

Embedded devices

eMMC storage

enhanced NEM (eNEM)

ESI register

ESP register

EU control system

Exception levels

Executable and Linkable Format (ELF)

Execution-In-Place (XIP)

Execution unit (EU)

Extended Industry Standard Architecture (EISA) Bus

Extensible Firmware Interface (EFI)

External Architecture Specification (EAS)

External payloads

fbnetboot

Firmware

architecture

authentication

cutting-edge technologies

definition

device

engineers

global embedded device market

hardware

Intel 8080 processor

non-host

open source vs. closed source

operating systems

origin

over-dependency

platform stack

programming knowledge

vs. software

specialized education

technological advancements, embedded device market

Zilog Z80 processor

Firmware boot flow

Firmware Configuration Framework (FCONF)

Firmware evolution

adolescence (2000 to 2015)

ACPI

alternative ecosystem approach

Itanium platform layout

LinuxBIOS

open firmware

security

UEFI

Adulthood (the modern era of firmware since 2015)

closed-source nature

coreboot project commits trends, YoY

hybrid firmware architecture

modern system programming language

next generation firmware

openness

security

basic I/O system

childhood (Mid-1980s to Late 1990s)

BIOS interrupt calls

BIOS services

BIOS setup utility

IBM PC/AT platform

IBM platform

PnP BIOS

POST (Power-On Self-Test)

user interface

CP/M platform

footprint

hardware space

human life cycle

IBM PC/AT platform

infancy (Early 1970 to Mid-1980s)

phases

Firmware Image Package (FIP)

Firmware Support Package (FSP)

Firmware Update Payload

Firmware volumes (FVs)

Fixed range MTRRs

Flags

FLAGS register

Flash map

Flattened Device Tree (FDT)

FSP External Architecture Specification (EAS)

FW_CONFIG

FWU mode

GbE firmware

General purpose partition (GPP)

General purpose registers (GPR)

Generic FSP postcodes

Global descriptor table (GDT)

Globally unique identifier (GUIDs)

GPIO programming

Graphics initialization

Graphics Output Protocol (GOP)

GTT stolen memory (GSM)

Handle database

Hand-Off Blocks (HOBs)

Hardware blocks

Hardware configuration (HW_CONFIG)

Hardware interrupts

Harvard architecture

Higher-level system software

High-level operating systems (HLOS)

High-level system software

Host firmware

Hybrid driver

Hybrid firmware architecture

ABI-based model

application

SeeApplication, hybrid firmware architecture

business goals

Chrome AP firmware development

conventional closed source firmware

SeeConventional closed source firmware

firmware development

hardware layer

layer

software/kernel layer

ground rules

modern firmware development

open community with closed sourcing, challenges

SeeOpen community with closed sourcing, challenges

silicon vendors with open sourcing

SeeSilicon vendors, challenges

supply chain

SeeSystem firmware supply chain

types of firmware development

Hybrid firmware development model

Hybrid firmware model

current industry trends

generic AMD SoC platform

Intel-based platforms

leading SoC vendors

MediaTek MT8192 platform

Qualcomm Snapdragon 7c platform

Hybrid work model

ACPI mode

computing machines

coreboot

FSP

goal/motivation

hardware

hidden mode

implementation schema

LPSS device

mainboard

opportunities

PCI mode

scalability/reliability/flexibility

SkipInit mode

SoC vendors

SPD hex data file

UPD

USB

WLAN device

IA-based platform

IBM PC/AT BIOS

IBM platform

IMC firmware

Independent BIOS Vendors (IBV)

Industry Standard Architecture (ISA) Bus

init() function

Initial Boot Block (IBB)

Initial Boot Block Loader (IBBL)

In-memory database (IMD)

Input/output advanced programmable interrupt controller (I/OAPIC)

Input/output (I/O) devices

DMA

interrupt-initiated I/O

legacy devices

modern devices

programmed I/O

Instruction

cycling

decoder

pointer register

set

Instruction Pointer Registers (IP)

Instruction Set Architecture (ISA)

Integrated firmware image (IFWI)

Intel Boot Initiative (IBI) program

Intel Firmware Support Package (FSP)

binaries

component logical view

configuration data region

coreboot

coreboot boot flow, FSP 2.2 specification binary

data structure

design philosophy

EDKII

evolution

FSP_INFO_HEADER, ImageBase

FSP_INFO_HEADER layout

glue layer

IntelFsp2Pkg handles context switching

output

PeiCore

producer/consumer model

silicon initialization

stack

2.0 specification

UEFI design philosophy

usage model

Intel SoC-based Chrome device

Intel SoC platform

Internet of Things (IoT)

Interrupt

APIC

definition

events

foundational principles

INTR

IOxAPIC

ISR

LAPIC

MSI

new program control

NMI

PIC

types

Interrupt descriptor table (IDT)

Interrupt enable (IF) flag

Interrupt-initiated I/O

Interrupt request (INTR)

Interrupt service routine (ISR)

Interrupt transfer

Interrupt vector table (IVT)

I/O address space

I/O advanced programmable interrupt controller (IOxAPIC)

Isochronous transfer

JEDEC initialization sequence

Kaby Lake-based new board

Kaby Lake-based sample mainboard

Key Manifest (KM)

Last level cache (LLC)

Late chipset initialization

boot media initialization

GPIO programming

graphics initialization

interrupts

minimal operations

PCI enumeration

Legacy access control (lac)

Legacy address range

Legacy BIOS

Legacy devices

Legacy mode

LinuxBIOS

LinuxBoot

advantages

architecture

benefits

BIOS

bootloader

bzImage

code structure

components

Depthcharge

DXE

fbnetboot

goal/motivation

hardware

implementation

init process

initramfs

kernel

localboot

ramstage

romstage

squared board

SystemBoot

u-root

u-root shell

Linux payload

LITE firmware

Local advanced programmable interrupt controller (LAPIC)

Localboot

Local descriptor table (LDT)

Machine language

Mainboard directory

Main memory address range

DPR

DSM

GSM

ISA hole

reserved memory ranges

TOLUD register

TSEG

Main memory upper address range

beyond 4GB

memory remapping

algorithm

REMAPBASE and REMAPLIMIT registers

TOM

upper PCI

TOUUD

MCUPM firmware

Memory address space

Memory initialization

Memory management

Memory management unit (MMU)

Memory Reference Code (MRC)

Memory type range registers (MTRRs)

caching

fixed range

mechanism

processor capability control registers

variable range

Message signaled interrupt (MSI)

Microarchitecture

8086 microarchitecture

instruction cycling

Microcode

Microprocessor

Microsoft Disk Operating System (MS-DOS)

Minimal bootloader flow (post reset)

host CPU, reset vector

memory initialization

mode switching

operating modes

post memory

SeePost memory initialization

pre-memory initialization

Minimalistic Bootloader design, x86 platform

BIOS AL services

BIOS runtime services

designing factors

frameworks

OS loader

post reset

SeeMinimal bootloader flow (post reset)

pre-reset flow

SPI flash

SeeSPI flash layout

Min Platform Architecture (MPA)

MMU hardware block

Model-specific register (MSR)

MTRRs

SeeMemory type range registers (MTRRs)

processor-specific control register

RDMSR

Modern computing device hardware

Modern computing devices

Modern consumer electronics devices

Modern devices

Modern firmware

Modern system programming language

Moore’s Law

Motherboard

Motherboard-associated device initialization

MP2 firmware

MTRRCap register Bit 8:0 VCNT offset

Multi-function PCI device

Multiprocessor environment

Multi-processor (MP)

Multiprocessor specification (MP Spec)

Multithreading

MXCSR register

Native function

Netboot

Non-Evict Mode (NEM)

Non-host firmware

Non-maskable interrupt (NMI)

Non-PRQ’ed Silicon

Non-x86 based SoC platform

OEM Boot Block (OBB)

Open and closed source system firmwares

benefits

business goals

Chrome OS platform

code change list (CL)

flip side

hybrid firmware development model

impacts

Intel SoC platform

OEM

project development cost

simplicity

Open community with closed sourcing, challenges

hard to debug

motivational issues

platform enabling model

security

silicon vendors

ungoverned growth, closed source blobs

Open Compute Project (OCP)

Open firmware (OF)

Open-source-based silicon development

Open Source Firmware development

Open Source Firmware (OSF)

Open Source Initiative (OSI)

Open source software movement

advantage

freedom and ensuring trust

free software

fundamental rights

German government

global geopolitical issues

government agencies

security

specialized systemic knowledge

trust

vendor-independent support

Open-system design

OpenTitan

Operands

Option ROM (OpROM)

OS-directed configuration and power management (OSPM)

OS handoff lists

ACPI table creation

e820 Table

MP Spec table

PIR table

SMBIOS table

OS loader

communication management

handoff lists

Payload

OS-to-hardware communication

Parallel computing

Payload

vs. bootloader

Depthcharge

GRUB2

LinuxBoot

SeaBIOS

UEFI

PC/AT BIOS

PCI configuration cycles

PCI configuration space

PCIe root ports

PCI header region fields

base address registers (read-write)

class code (read-only)

device ID (read-only)

header type (read-only)

interrupt line (read-write)

interrupt pin (read-write)

vendor ID (read-only)

PCI memory address range

PEIM-to-PEIM Interfaces (PPIs)

Peripheral Component Interconnect Express (PCIe) Bus

Peripheral component interconnect (PCI) bus

configuration space

CPU and system devices connecting

flexibility

header region fields

SeePCI header region fields

multi-bus topology

physical address spaces

unique identity

Peripheral Connect Interface (PCI)

Personal Computer/AT (PC/AT)

Pipelining

PI specification

after life phase

BDS phase

boot phases

DXE phase

SeeDriver Execution Environment (DXE) phase

hardware components

overview

PEI phase

SeePre-EFI initialization phase

PIWG

RT phase

security phase

transient system load phase

UEFI specification

Platform bootup time

Platform enabling model

Platform initialization (PI)

Platform Initialization Working Group (PIWG)

Platform-specific FSP postcodes

Plug and Play BIOS (PnP BIOS)

PMU firmware

Portable Executable (PE)

Port X Enable (PxE)

Postcar

Postcodes

Post memory initialization

foundation block

late chipset initialization

memory test

MP initialization

shadowing

SIPI

tear down the CAR

Power Management Controller (PMC)

Power-on self-test (POST)

Power State Coordination Interface (PSCI)

Pre-CPU reset

Pre-EFI Initialization Modules (PEIMs)

Pre-EFI initialization phase

dispatcher

DXE foundation dispatch

foundation

FVs

HOBs

operational diagram

PEIMs

PEI-to-DXE handoff

PI architecture

PPIs

responsibilities

services

Prefetch instruction queue

Pre-reset flow

boot flow

controllers and microcontrollers

IA-architecture

IA-based platforms

IBB

IBBL

OBB

Privileged/system instructions

Processor modes

IVT

protected mode

real mode

SMM

Product Ready Quality (PRQ)

Program counter registers

Programmable interrupt controller (PIC)

Programmable interrupt routing (PIR) table

Programmable read-only memory (PROM)

Programmed I/O

Programming Language for Microcomputers (PL/M)

Program status registers

Protected mode

PSP firmware

Public-key cryptography standards (PKCS)

PUNIT

QC-SEC

QTISECLIB

Qualcomm SoC platform

Qualcomm Unified Peripheral (QUP)

QUP firmware

Ramstage

coreboot

responsibilities

Read-only memory (ROM)

Real addressing mode

Real mode

Real-time clock (RTC)

Recovery mode

Reduced Instruction Set Computer (RISC)

Registers

definition

EFLAGS

GPR

EAX

EBX

ECX

EDX

MSR

SeeModel-specific register (MSR)

segment register

size

SPR

vector registers

Relocatable Modules (rmodules)

RISC processor

Romstage

CBMEM

IMD

responsibilities

rmodules

Root system description pointer (RSDP)

RT (run time) phase

Runtime phase

Runtime (RT) services

SblParseLib

SeaBIOS

Secondary System Description Table (SSDT)

SEC (security) phase

Secure Monitor Call (SMC)

Secure processing environments (SPEs)

Security

Security phase (SEC)

Segment descriptor

Segment register

Segments

Segment selector

Self-supportive

Separate instruction and data cache

Serial AT attachment (SATA)

Serial peripheral interconnect (SPI)

Serial presence detect (SPD)

Shadowing

Shared static RAM (SRAM)

Silicon reference code

Silicon vendors

hardware partners

software vendors

Silicon vendors, challenges

closed-source mindset

datasheet dependency

distinguished product features

documentation

Non-PRQ’ed silicon

Intel’s FSP development

limited customer demand

silicon reference code development without compatibility

system firmware architecture

third-party ip restrictions

UEFI platform-independent FSP development

Single instruction, multiple data (SIMD)

Slim Bootloader (SBL) architecture

board customization

configuration flow

dynamic

static

boot flow

boot stages

stage 1

stage 2

component IDs

coreboot

firmware update flow

flash layout

flash map

redundant partitions

Intel Apollo Lake platform

Intel FSP interfaces

Intel platforms, IoT market

payloads

built-in

external

interface

payload stage

platform initialization

QEMU virtual platform support

source tree structure

base tools

Bootloader common and core package

payload package

platform package

silicon package

UEFI and coreboot comparison

UEFI EDKII project

SoC architecture

SoC code structures

SoC firmware configuration (SOC_FW_CONFIG)

Socketed memory

Software Developer Manuals (SDM)

Software development kit (SDK)

Software interrupts

Soldered memory

Solid state devices (SSDs)

Source index register (ESI)

SPD hex data file

Special purpose registers (SPR)

SPI flash

SPI flash layout

BIOS region

firmware integration

flash region registers

IFWI

x86-based embedded systems

Xeon processor-based server platform

SPI NOR

SPM firmware

SRAM/DRAM

SSPM firmware

Stack segment register

Standard communication method

Startup inter-processor interrupt (SIPI)

AP initialization sequence

APs

BSP initialization sequence

Static configuration

Status and control register (EFLAGS)

Stitching tools

System Agents (SA)

System architecture

buses

hardware blocks

I/O devices

memory unit

Systemboot

System firmware

computing systems

definition

hardware architecture

high-level system software

loosely coupled

target hardware

tightly coupled

System firmware development model

closed source firmware development

generic

hybrid work model

legacy BIOS

open source firmware initiatives

OSI

silicon vendors

typical platform initialization guidelines

x86-based SoC platform

System firmware execution

System firmware program

System firmware supply chain

blocks

boot firmware

dictatorship by silicon vendors

open-source firmware development approach

wrapper layer

System initialization

System Management BIOS (SMBIOS)

System management interrupt (SMI)

System management mode (SMM)

System management RAM (SMRAM)

System memory map

legacy address range

conventional memory

regions

upper memory

main memory address range

main memory upper address range

PCI memory address range

system firmware

System memory range

System-on-chip (SoC)

System Power Manager (SPM)

System power states

System timer

Table indicator (TI)

Target hardware architecture

Task Priority Level (TPL)

Test Setup Engine (TSE)

TF architecture

ARM architecture

boot loader stages

FCONF

FIP

firmware authentication

initialization process

Third-party IP restrictions

32-bit registers

Thumb instruction set

Tianocore

Timers

Top of main memory segment (TSEG)

Top of Memory (TOM)

Top of Upper Usable DRAM (TOUUD)

Traditional x86-based platform coreboot code structure

Transient system load (TSL) phase

Translation look-aside buffer (TLB)

Trusted Board Boot (TBB)

Trusted Computing Base (TCB)

Trusted execution environments (TEEs)

Trusted Firmware-A (TF-A)

Trusted Firmware minimalistic bootloader

Trusted Firmware-M (TF-M)

Trusted Firmware (TF)

exception levels

PSCI

SMC calling convention

TBB requirements

TF-A

TF-M

Trusted-Firmware (TF-A)

Type 0 PCI configuration cycle

Type 1 PCI configuration cycle

Type-C Port Controller (TCPC)

U-boot

UEFI architecture

hardware-specific initializations

overview

PI specification

SeePI specification

specification

SeeUEFI specification

UEFI-based firmware

UEFI-based system firmware

UEFI capsule update process

UEFI images

application

boot service drivers

driver

operation

parameters

PE/COFF image header

platform hardware

runtime drivers

types

UEFI driver model

UEFI payload

architecture

boot flow

bootloader

code structure

flash layout

value-added services

UEFI PI model

UEFI specification

concepts

device path

driver connection process

EFI byte code

EFI system table

events

GUIDs

handle database

motherboard component

objects

protocols

types of UEFI images

UEFI driver model

definition

device initialization

EFI driver binding protocol

EFI_DRIVER_BINDING_PROTOCOL

UEFI images

UEFI services

boot services

runtime service function

Uncacheable (UC)

Unified cache

Unified Extensible Firmware Interface (UEFI)

architecture

SeeUEFI architecture

data tables

definition

EDKII

firmware complexity

firmware development, computer systems

generic EDKII code

implementations

layout

legacy BIOS implementation

modern firmware development model

PC/AT BIOS

security vulnerabilities

system firmware development model

system firmware development, modern hardware

Universal Boot Loader (U-Boot)

Universal Payload Layer (UPL)

coreboot

Depthcharge

extra image

format

Image Information Section

implementation

interface

LinuxBoot

SBL

specification

UEFI

Universal Serial Bus (USB)

Updateable product data (UPD)

Upper memory region

extended system BIOS area

legacy video area

programmable attribute map

VBIOS area

Upper PCI memory address range

u-root

User interface

Value-added services

EC software sync

PD firmware update

Variable range MTRRs

Vector registers

Verified boot (vboot)

Verstage

Video BIOS (vBIOS)

Volatile memory

cache

CPU registers

local disks

remote storage

SRAM/DRAM

von Neumann architecture

Watchdog timer (WDT)

Wired for Management (WfM)

Wrapper layer

Write-back (WB)

Write combining (WC)

Write-protected (WP)

Write-through (WT)

x86-based silicon vendors

x86-based SoC platform

x86 processor internals

16-bit (D0-D15) bidirectional data bus

BIU

interrupt

modes

SeeProcessor modes

registers

SeeRegisters

RTC

system timer

timers

von Neumann architecture machine

xHCI firmware

XMM registers

Y, Z

YMM registers

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