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FPGA Programming for Beginners

Release Date: 2021/03/01
ISBN: 9781789805413
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Get started with FPGA programming using SystemVerilog, and develop real-world skills by building projects, including a calculator and a keyboard

Key Features

  • Explore different FPGA usage methods and the FPGA tool flow
  • Learn how to design, test, and implement hardware circuits using SystemVerilog
  • Build real-world FPGA projects such as a calculator and a keyboard using FPGA resources

Book Description

Field Programmable Gate Arrays (FPGAs) have now become a core part of most modern electronic and computer systems. However, to implement your ideas in the real world, you need to get your head around the FPGA architecture, its toolset, and critical design considerations. FPGA Programming for Beginners will help you bring your ideas to life by guiding you through the entire process of programming FPGAs and designing hardware circuits using SystemVerilog.

The book will introduce you to the FPGA and Xilinx architectures and show you how to work on your first project, which includes toggling an LED. You'll then cover SystemVerilog RTL designs and their implementations. Next, you'll get to grips with using the combinational Boolean logic design and work on several projects, such as creating a calculator and updating it using FPGA resources. Later, the book will take you through the advanced concepts of AXI and serial interfaces and show you how to create a keyboard using PS/2. Finally, you'll be able to consolidate all the projects in the book to create a unified output using a Video Graphics Array (VGA) controller that you'll design.

By the end of this SystemVerilog FPGA book, you'll have learned how to work with FPGA systems and be able to design hardware circuits and boards using SystemVerilog programming.

What you will learn

  • Understand the FPGA architecture and its implementation
  • Get to grips with writing SystemVerilog RTL
  • Make FPGA projects using SystemVerilog programming
  • Work with computer math basics, parallelism, and pipelining
  • Explore the advanced topics of AXI and serial interfaces
  • Discover how you can implement a VGA interface in your projects

Who this book is for

This FPGA design book is for embedded system developers, engineers, and programmers who want to learn FPGA and SystemVerilog programming from scratch. FPGA designers looking to gain hands-on experience in working on real-world projects will also find this book useful.

Table of Contents

  1. FPGA Programming for Beginners
  2. Contributors
  3. About the author
  4. About the reviewer
  5. Preface
    1. Who this book is for
    2. What this book covers
    3. To get the most out of this book
    4. Download the example code files
    5. Download the color images
    6. Conventions used
    7. Get in touch
    8. Reviews
  6. Section 1: Introduction to FPGAs and Xilinx Architectures
  7. Chapter 1: Introduction to FPGA Architectures and Xilinx Vivado
    1. Technical requirements
    2. Hardware
    3. Software
    4. What is an ASIC?
    5. Why an ASIC or FPGA?
    6. How does a company create a programmable device using an ASIC process?
    7. Fundamental logic gates
    8. Assign statement
    9. Comments
    10. if statement
    11. Logical NOT (!)
    12. Logical AND (&&), bitwise AND (&)
    13. Logical OR (||), bitwise OR (|)
    14. XOR (^)
    15. More complex operations
    16. Introducing FPGAs
    17. Exploring the Xilinx Artix-7 and 7 series devices
    18. Combinational logic blocks
    19. Storage
    20. Clocking
    21. I/Os
    22. DSP48E1
    23. ASMBL architecture
    24. Introduction to the Vivado toolset and evaluation boards
    25. Evaluation boards
    26. Nexys A7 100T (or 50T)
    27. Basys 3
    28. Introducing Vivado
    29. Vivado installation
    30. Directory structure
    31. Running the example
    32. Loading the design
    33. Running a simulation
    34. Implementation
    35. Program the board
    36. Summary
    37. Questions
    38. Challenge
    39. Further reading
  8. Section 2: Introduction to Verilog RTL Design, Simulation, and Implementation
  9. Chapter 2: Combinational Logic
    1. Technical requirements
    2. Creating SystemVerilog modules
    3. How to create reusable code – parameters
    4. Introducing data types
    5. Introducing built-in data types
    6. Creating arrays
    7. Querying arrays
    8. Assigning to arrays
    9. Handling multiple-driven nets
    10. Handling signed and unsigned numbers
    11. Adding bits to a signal by concatenating
    12. Casting signed and unsigned numbers
    13. Creating user-defined types
    14. Accessing signals using values with enumerated types
    15. Packaging up code using functions
    16. Creating combinational logic
    17. Handling assignment operators
    18. Incrementing signals
    19. Making decisions – if-then-else
    20. Introducing the case statement
    21. Using the conditional operator to select data
    22. Using custom data types
    23. Creating structures
    24. Creating unions
    25. Project 1 – creating combinational logic
    26. Testbench
    27. Simulating using targeted testing
    28. Simulating using randomized testing
    29. Simulating using constrained randomization
    30. Implementing a leading-one detector using the case statement
    31. Controlling implementation using generate
    32. Designing a reusable leading-one detector using a for loop
    33. Setting SELECTOR = DOWN_FOR
    34. Setting SELECTOR = UP_FOR
    35. Counting the number of ones
    36. Implementing an adder/subtractor
    37. Add
    38. Subtractor
    39. Multiplier
    40. Bringing it all together
    41. Adding a latch
    42. Summary
    43. Questions
    44. Challenge
    45. Further reading
  10. Chapter 3: Counting Button Presses
    1. Technical requirements
    2. What is a sequential element?
    3. Clocking your design
    4. Looking at a basic register
    5. Creating a flip flop
    6. When to use always @() for FF generation
    7. Using non-blocking assignments
    8. Registers in the Artix 7
    9. How to hold onto state using clock enables
    10. Resetting the FF
    11. Project 2 – Counting button presses
    12. Introducing the seven-segment display
    13. Detecting button presses
    14. Analyzing timing
    15. Looking at asynchronous issues
    16. Using the asynchronous signal directly
    17. The problem with push buttons
    18. Designing a safe implementation
    19. Switching to decimal representation
    20. Introducing the ILA
    21. What about simulation?
    22. Deep dive on synchronization
    23. Why use multiple clocks?
    24. Two-stage synchronizer
    25. Synchronizing control signals
    26. Passing data
    27. Summary
    28. Questions
    29. Challenge
    30. Further reading
  11. Chapter 4: Let's Build a Calculator
    1. Technical requirements
    2. Implementing our first state machine
    3. Writing a purely sequential state machine
    4. Splitting combination and sequential logic in a state machine
    5. Designing a calculator interface
    6. Designing a Moore state machine
    7. Implementing a Mealy state machine
    8. Practical state machine design
    9. Project 3 – Building a simple calculator
    10. Packaging for reuse
    11. Coding the top level
    12. Changing frequencies by using a PLL or MMCM
    13. Investigating the divider
    14. Building a non-restoring divider state machine
    15. Simulating the divider
    16. Sizing the intermediate remainder
    17. Project 4 – Keeping cars in line
    18. Defining the state diagram
    19. Displaying our traffic lights
    20. Pulse width modulation
    21. Implementing delays with a counter
    22. Summary
    23. Questions
    24. Challenge
    25. Extra challenge
    26. Further reading
  12. Chapter 5: FPGA Resources and How to Use Them
    1. Technical requirements
    2. Project 5 – Listening and learning
    3. What is a PDM microphone?
    4. Simulating the microphone
    5. Introducing storage
    6. RAM – Inferring versus instantiating versus the IP catalog
    7. Basic RAM types
    8. Instantiating memories using xpm_memory
    9. Using the IP catalog to create memory
    10. Capturing audio data
    11. Project 6 – Using the temperature sensor
    12. Handling the data
    13. Smoothing out the data
    14. Deeper dive into FIFOs
    15. Constraints
    16. Generating our FIFO
    17. Summary
    18. Questions
    19. Further reading
  13. Chapter 6: Math, Parallelism, and Pipelined Design
    1. Technical requirements
    2. Introduction to fixed-point numbers
    3. Project 7 – Using fixed-point arithmetic in our temperature sensor
    4. Using fixed-point arithmetic to clean up the bring-up time
    5. Temperature conversion using fixed-point arithmetic
    6. What about floating-point numbers?
    7. Floating-point addition and subtraction
    8. Floating-point multiplication
    9. Floating-point reciprocal
    10. A more practical floating-point operation library
    11. A quick look at the AXI streaming interface
    12. Project 8 – Updating the temperature sensor project to a pipelined floating-point implementation
    13. Fix to floating point conversion
    14. Floating-point math operations
    15. Float to fixed point conversion
    16. Simulation
    17. Parallel designs
    18. ML and AI and massive parallelism
    19. Parallel design – a quick example
    20. Summary
    21. Questions
    22. Challenge
    23. Further reading
  14. Section 3: Interfacing with External Components
  15. Chapter 7: Introduction to AXI
    1. Technical requirements
    2. AXI streaming
    3. Project 9 – creating IPs for Vivado using AXI streaming interfaces
    4. Seven-segment display streaming interface
    5. Developing the ADT7420 IP
    6. Understanding the flt_temp core
    7. IP integrator
    8. IP integrator debugging
    9. AXI4 interfaces (full and AXI-Lite)
    10. Developing IPs – AXI-Lite, full, and streaming
    11. Adding an unpackaged IP to the IP integrator
    12. Summary
    13. Questions
    14. Further reading
  16. Chapter 8: Lots of Data? MIG and DDR2
    1. Technical requirements
    2. Project 10 – introducing external memory
    3. Introduction to DDR2
    4. Generating a DDR2 controller using the Xilinx MIG
    5. Setting AXI parameters
    6. Setting memory options
    7. Defining the FPGA options
    8. Modifying the design for use on the board
    9. Other external memory types
    10. Quad Data Rate (QDR) SRAM
    11. HyperRAM
    12. SPI RAM
    13. Summary
    14. Questions
    15. Challenge
    16. Further reading
  17. Chapter 9: A Better Way to Display – VGA
    1. Technical requirements
    2. Project 11 – Introducing the VGA
    3. Defining registers
    4. Coding a simple AXI Lite interface
    5. Generating timing for the VGA
    6. Monitor timing generator
    7. Displaying text
    8. Requesting memory
    9. Testing the VGA controller
    10. Examining the constraints
    11. Summary
    12. Questions
    13. Challenge
    14. Further reading
  18. Chapter 10: Bringing It All Together
    1. Technical requirements
    2. Investigating the keyboard interface
    3. Project 12 – keyboard handling
    4. Testing the PS/2
    5. Project 13 – bringing it all together
    6. Displaying PS/2 keycodes on the VGA screen
    7. Displaying the temperature sensor data
    8. Adding a custom character to the text ROM
    9. Displaying audio data
    10. Summary
    11. Questions
    12. Challenge
    13. Further reading
  19. Chapter 11: Advanced Topics
    1. Technical requirements
    2. Exploring more advanced SystemVerilog constructs
    3. Interfacing components using the interface construct
    4. Using structures
    5. Block labels
    6. Looping using for loops
    7. Looping using do…while
    8. Exiting a loop using disable
    9. Skipping code using continue
    10. Using constants
    11. Exploring some more advanced verification constructs
    12. Introducing SystemVerilog queues
    13. Display enhancements
    14. A quick introduction to assertions
    15. Using $error or $fatal in synthesis
    16. Other gotchas and how to avoid them
    17. Inferring single bit wires
    18. Bit width mismatches
    19. Upgrading or downgrading Vivado messages
    20. Handling timing closure
    21. How to pipeline a design
    22. Summary
    23. Questions
    24. Further reading
    25. Why subscribe?
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