Index
ACD (Analog Comparator Disable bit), 46
ACI (Analog Comparator Interrupt flag), 46
ACIC (Analog Comparator Input Capture Enable bit), 47
ACISO/ACIS1 (Analog Comparator Interrupt Mode Select bits), 47
ACSR (Analog Comparator Control and Status register), 46
ADC (Add with Carry), 71
ADD (Add without Carry), 72
Addressing modes, memory, 63–71
ADIW (Add Immediate to Word), 72
ALU (arithmetic logic unit), 12–14
Analog comparator, 43–48
AND (Logical AND), 72
ANDI (Logical AND with Immediate), 73
ANSI C libraries, 151
Architectural overview, 9–13
Architecture, 1–5
AVR microcontrollers based on new RISC, 9
internal, 5
reduced-instruction-set computer (RISC), 9
von Neumann, 3
ASR (Arithmetic Shift Right), 73
Assemble menu, 134
ATMELAVR, 131–39
example programs in AVR, 179–261
AT90S1200, 180–228
first test, 180–83
including interrupts, 183–89
programming duty cycles, 189–95
programming timer periods, 189–95
query keys, 198–202
security enhancement in data transmission by CRe, 215–18
software SPI, 218–28
software time delays, 195–98
software UART, 202–10
tables in EEPROM, 210–14
AT90S8515, 228–61
first test, 228–31
pulse-width modulation (PWM), 231–34
serial communication with internal UART, 235–37
serial data exchange with SPI, 241
software I2C, 241–61
tables in code area, 273–41
Assembler source code, editing, 134–39
Assemble menu, 134
Directives, 135–38
File> Open, 134
Macros, 138–39
Options menu, 134–35
AT90S1200, assembler programs for, 180–228
first test, 180–83
including interrupts, 183–89
programming duty cycles, 189–95
programming timer periods, 189–95
query keys, 198–202
security enhancement in data transmission by CRC, 215–18
software SPI, 218–28
software time delays, 195–98
software UART, 202–10
tables in EEPROM, 210–14
AT90S8515, assembler programs for, 228–61
first test, 228–31
pulse-width modulation (PWM), 231–34
serial communication with internal UART, 235–37
serial data exchange with SPI, 241
software I2C, 241–61
tables in code area, 273–41
AT90S8515, serial communication for, 266–72
application notes and software, 301–3
AVRassembler, 131–39
editing assembler source code, 134–39
AVR development board from, 169–71
Debug menu, 141
Help> Option menu, 141
Options> AVR Options menu, 140
AVR studio, 144–46
Options > Simulator Options menu, 146
assembler example programs, 179–261
microcontrollers based on new RISC architecture, 9
Pascal from E-Lab computers, 155–65
tools, 148
example programs in, 265–72
microcontroller test, 265–66
PWM (pulse-width modulation), 266–72
serial communication for AT90S8515, 266–72
from Silicon Studio, 166–68
AVR development board from Atmel, 169–71
Tools > Program Device menu, 170
AVR embedded workbench, EWA90 demo of, 153–55
example programs in, 265–72
microcontroller test, 265–66
PWM (pulse-width modulation), 266–72
serial communication for AT90S8515, 266–72
Baud rate generator, 43
BCLR (Bit Clear in SREG), 73
Bit definitions, 281–86
BLD (Bit Load from T flag in SREG), 74
evaluation, 168–77
programmer, 168–77
Branches, conditional, 120–23
BRBC (Branch If Bit in SREG Is Cleared), 74
BRBS (Branch If Bit in SREG Is Set), 74
BRCC (Branch If Carry Is Cleared), 75
BRCS (Branch If Carry Is Set), 75
BREQ (Branch If Equal), 75–76
BRGE (Branch If Greater or Equal [Signed]), 76
BRHC (Branch If Half Carry Flag Is Cleared), 76–77
BRHS (Branch If Half Carry Flag Is Set), 77
BRID (Branch If Global Interrupt Is Disabled), 77
BRIE (Branch If Global Interrupt Is Enabled), 77–78
BRLO (Branch If Lower), 78
BRLT (Branch If Less Than [Signed]), 78–79
BRMI (Branch If Minus), 79
BRNE (Branch If Not Equal), 79–80
BRPL (Branch If Plus), 80
BRSH (Branch If Same or Higher [Unsigned]), 80–81
BRTC (Branch If T Flag Is Cleared), 81
BRTS (Branch If T Flag Is Set), 81
BRVC (Branch If Overflow Flag Is Cleared), 82
BRVS (Branch If Overflow Flag Is Set), 82
BSET (Bit Set in SREG), 82
BST (Bit Store from Bit in Register to T Flag), 83
ANSI libraries, 151
compilers, JAR, 148–50
example program in, 261–65
CALL (Long Call to a Subroutine), 83
Calls, 69–71
CBI (Clear Bit in I/O Register), 83–84
CBR (Clear Bits in Register), 84
Circuit, reset, 6
CLC (Clear Carry Flag), 84
CLH (Clear Half Carry Flag), 84
CLI (Clear Global Interrupt Flag), 85
CLK (clock cycle), 2
CLN (Clear Negative Flag), 85
Clock, 60–62
Clock/counter, real-time, 7
CLR (Clear Register), 85
CLS (Clear Sign Flag), 86
CLT (Clear T Flag), 86
CLV (Clear Overflow Flag), 86
CLZ (Clear Zero Flag), 86
Code area, tables in, 237–41
COM (One’s Complement), 87
IAR C, 148–50
Pascal, 155–65
Conditional branches, 120–23
Constructs, program, 120–27
Contacts, 307–8
Converter, decimal-to-Hex-to-ASCII, 299–300
Counter, real-time, 7
CP (Compare), 87
CPC (Compare with Carry), 87
CPI (Compare with Immediate), 87–88
CPSE (Compare Skip If Equal), 88
CRC (cyclic redundancy check), security enhancement in data transmission by, 215–18
CWA90 debugger/simulator, IAR, 151–53
Cycles, programming duty, 189–95
Data memories, 14–21
Data memory, EEPROM, 17–21
Data memory, SRAM, 14–16
Data reception, 39–40
Data transmission, 37–39
DDRB (data direction register B), 37
Debug menu, 141
Debugger/simulator, JAR CWA90, 151–53
DEC (Decrement), 88
Decimal-to-Hex-to-ASCII converter, 299–300
Defensive programming, 127–29
polling inputs, 128–29
refreshing important registers, 127–28
refreshing port pins, 127–28
Defined loops, 124–25
Design philosophy, RISC, 4
Development boards from Atmel, AVR, 169–71
Development tools, 131–77
ATMEL AVR assembler, 131–39
editing assembler source code, 134–39
ATMEL AVR studio, 144–46
AVR BASIC from Silicon Studio, 166–68
AVR Pascal from E-Lab Computers, 155–65
evaluation boards, 168–77
IAR embedded workbench EWA90, 146–51
programmer and evaluation boards, 168–77
Directives, 135–38
DORD (Data Order bit), 34
Downloadable flash program memory, 14
Duty cycles, programming, 189–95
E-Lab Computers, AVR Pascal from, 155–65
data memory, 17–21
defined, 6
tables in, 210–14
EERE (EEPROM read enable), 20
EEWE (EEPROM write enable), 20–21
Intel Hex file format, 297
Timer/CounterO, 21–24
Embedded workbench, EWA90 demo of AVR, 153–55
Endless loops, 126–27
EOR (Exclusive OR), 89
EPROM (electrical programmable read-only memory) defined, 6
Equinox, ISP starter kit from, 171–73
Evaluation boards, 168–77
EWA90 demo of AVR embedded workbench, 153–55
Example programs, 179–272
External reset, 60
bit, 42
flag, 40
File> Open, 134
8-Bit Intel format, 297
general purpose register, 16
Flash memory defined, 6
Flash program memory, downloadable, 14
Frequency, PWM output, 30
reset and interrupt, 112–15
watchdog, 115
Hardware resources, 63–129
architectural overview, 9–13
arithmetic logic unit (ALU), 13–14
of AVR microcontrollers, 9–62
clock, 60–62
data memories, 14–21
defensive programming, 127–29
polling inputs, 128–29
refreshing important registers, 127–28
refreshing port pins, 127–28
instruction set, 71–111
memory addressing modes, 63–71
I/O direct addressing, 63–65
constant addressing using LPM instruction, 69
jumps and calls, 69–71
register direct addressing, 63
SRAM direct addressing, 65
SRAM indirect addressing, 65–69
peripherals, 21–56
I/O ports, 48–56
analog comparator, 43–48
SPI (serial peripheral interface), 32–37
timer/counters, 21–31
UART (universal asynchronous receiver and transmitter), 37–43
watchdog timer, 31–32
program constructs, 120–27
conditional branches, 120–23
program loops, 123–27
program and data memories, 14–21
I/O register, 16–17
downloadable flash program memory, 14
EEPROM data memory, 17–21
general purpose register file, 16
SRAM data memory, 14–16
reset and interrupt handling, 112–15
reset and interrupt system, 57–60
interrupt vector table, 57–58
reset sources, 58–60
stack, 116–20
watchdog handling, 115
Help > Option, menu, 141
Hex file format, 8 -Bit Intel, 297
Hex-to-ASCII converter, 299–300
I2C software, 241–61
I/O (input and/or output), 1
direct addressing, 63–65
ports, 48–56
access to external SRAM, 54–56
PortA, 51–52
PortB, 52–53
PortC, 53–54
PortD, 54
ports defined, 6
registers, 16–17
C compiler, 148–50
CWA90 debugger/simulator, 151–53
embedded workbench EWA90, 146–51
C compiler, 148–50
ANSI C libraries, 151
CWA90 debugger/simulator, 151–53
workbench, 153–55
linker, 151
routines, 150–51
summary of available AVR tools, 148
ICALL (Indirect Call to Subroutine), 89
ICFl (Input Capture Flag 1), 28
IJMP (Indirect Jump), 89
IN (Load an I/O Port to Register), 90
INC (Increment), 90
Initialization, program, 7
Inputs, polling, 128–29
Installation, program, 7
Instruction set, 71–111
CLI (Clear Global Interrupt Flag), 85
CLV (Clear Overflow Flag), 86
ADC (Add with Carry), 71
ADD (Add without Carry), 72
ADIW (Add Immediate to Word), 72
AND (Logical AND), 72
ANDI (Logical AND with Immediate), 73
ASR (Arithmetic Shift Right), 73
BCLR (Bit Clear in SREG), 73
BLD (Bit Load from T flag in SREG), 74
BRBC (Branch If Bit in SREG Is Cleared), 74
BRBS (Branch If Bit in SREG Is Set), 74
BRCC (Branch If Carry Is Cleared), 75
BRCS (Branch If Carry Is Set), 75
BREQ (Branch If Equal), 75–76
BRGE (Branch If Greater or Equal [Signed]), 76
BRHC (Branch If Half Carry Flag Is Cleared), 76–77
BRHS (Branch If Half Carry Flag Is Set), 77
BRID (Branch If Global Interrupt Is Disabled), 77
BRIE (Branch If Global Interrupt Is Enabled), 77–78
BRLO (Branch If Lower), 78
BRLT (Branch If Less Than [Signed]), 78–79
BRMI (Branch If Minus), 79
BRNE (Branch If Not Equal), 79–80
BRPL (Branch If Plus), 80
BRSH (Branch If Same or Higher [Unsigned]), 80–81
BRTC (Branch 1fT Flag Is Cleared), 81
BRTS (Branch If T Flag Is Set), 81
BRVC (Branch If Overflow Flag Is Cleared), 82
BRVS (Branch If Overflow Flag Is Set), 82
BSET (Bit Set in SREG), 82
BST (Bit Store from Bit in Register to T Flag), 83
CALL (Long Call to a Subroutine), 83
CBI (Clear Bit in I/O Register), 83–84
CBR (Clear Bits in Register), 84
CLC (Clear Carry Flag), 84
CLH (Clear Half Carry Flag), 84
CLN (Clear Negative Flag), 85
CLR (Clear Register), 85
CLS (Clear Sign Flag), 86
CLT (Clear T Flag), 86
CLZ (Clear Zero Flag), 86
COM (One’s Complement), 87
CP (Compare), 87
CPC (Compare with Carry), 87
CPI (Compare with Immediate), 87–88
CPSE (Compare Skip If Equal), 88
DEC (Decrement), 88
EOR (Exclusive OR), 89
ICALL (Indirect Call to Subroutine), 89
IJMP (Indirect Jump), 89
IN (Load an I/O Port to Register), 90
INC (Increment), 90
JMP (Jump), 90–91
LD (Load Indirect from SRAM to Register Using Index X), 91
LD (Load Indirect from SRAM to Register Using Index Y), 91–92
LD (Load Indirect from SRAM to Register Using Index Z), 92–93
LDI (Load Immediate), 93
LDS (Load Direct from SRAM), 94
LPM (Load Program Memory), 94
LSL (Logical Shift Left), 94–95
LSR (Logical Shift Right), 95
MOV (Copy Register), 95
MUL (Multiply), 95–96
NEG (Two’s-Complement), 96
NOP (No Operation), 96
OR (Logical OR), 97
ORI (Logical OR with Immediate), 97
OUT (Store Register to I/O Port), 97
POP (Pop Register from Stack), 98
PUSH (Push Register on Stack), 98
RCALL (Relative Call to Subroutine), 98–99
RET (Return from Subroutine), 99
RETI (Return from Interrupt), 99
RJMP (Relative Jump), 100
ROL (Rotate Left through Carry), 100
ROR (Rotate Right through Carry), 100–101
SBC (Subtract with Carry), 101
SBCI (Subtract Immediate with Carry), 101
SBI (Set Bit in I/O Register), 101–2
SBIC (Skip If Bit in I/O Register Is Cleared), 102
SBIS (Skip If Bit in I/O Register Is Set), 102
SBIW (Subtract Immediate from Word), 102–3
SBR (Set Bits in Register), 103
SBRC (Skip If Bit in Register Is Cleared), 103
SBRS (Skip If Bit in Register Is Set), 104
SEC (Set Carry Flag), 104
SEH (Set Half Carry Flag), 104
SEI (Set Global Interrupt Flag), 105
SEN (Set Negative Flag), 105
SER (Set All Bits in Register), 105
SES (Set Signed Flag), 106
SET (Set T Flag), 106
SEV (Set Overflow Flag), 106
SEZ (Set Zero Flag), 106–7
SLEEP (Sleep), 107
ST (Store Indirect from Register to SRAM Using Index X), 107–8
ST (Store Indirect from Register to SRAM Using Index Y), 108
ST (Store Indirect from Register to SRAM Using Index Z), 109
STS (Store Direct to SRAM), 109–10
SUB (Subtract without Carry), 110
SUBI (Subtract Immediate), 110
SWAP (Swap Nibbles), 111
TST (Test for Zero or Minus), 111
WDR (Watchdog Reset), 111
Intel Hex file format, 8 -Bit, 297
Interface, serial peripheral, 32–37
Internal architecture defined, 5
Interrupts, 183–89
handling, 112–15
systems, 57–60
vector tables, 57–58
ISP starter kit from Equinox, 171–73
LD (Load Indirect from SRAM to Register Using Index X), 91
LD (Load Indirect from SRAM to Register Using Index Y), 91–92
LD (Load Indirect from SRAM to Register Using Index Z), 92–93
LDI (Load Immediate), 93
LDS (Load Direct from SRAM), 94
Libraries, ANSI C, 151
Linker, 151
Literature, 305
defined, 124–25
endless, 126–27
program, 123–27
undefined, 125–26
LPM (Load Program Memory), 94
instruction, 69
LSB (least significant bit), 7
LSL (Logical Shift Left), 94–95
LSR (Logical Shift Right), 95
Macro-assembler, 150–51
Macros, 138–39
Mbyte, 7
MCUCR (MCU control register), 52–53
addressing modes, 63–71
I/O direct addressing, 63–65
instruction, 69
jumps and calls, 69–71
register direct addressing, 63
SRAM direct addressing, 65
SRAM indirect addressing, 65–69
data, 14–21
defined, 5–6
downloadable flash program, 14
EEPROM data, 17–21
flash, 6
program, 14–21
SRAM, 9
SRAM data, 14–16
Assemble, 134
debug, 141
Help> Option, 141
Options, 134–35
Options> AVR Options, 140
Options> Simulator Options, 146
Tools > Program Device, 170
hardware resources of AVR, 9–62
tests, 265–66
Modules, schematics of SIMMSTICK, 277–79
MOV (Copy Register), 95
MSB (most significant bit), 7
MSTR (Master/Slave Select bit), 35
MUL (Multiply), 95–96
NEG (Two’s-Complement), 96
NOP (No Operation), 96
Notes, Atmel’s application, 301–3
Numbering system, part, 273–74
Numbers, 7–8
OCFIA10CFIB (Output Compare flag 1), 28
OCRIA (Output Compare register 1A), 29
OCRIB (Output Compare register 1B), 29
Options> AVR Options menu, 140
Options> Simulator Options menu, 146
Options menu, 134–35
OR (Logical OR), 97
ORI (Logical OR with Immediate), 97
Oscillator defined, 6
OTP-ROM (one-time programmable EPROM) defined, 6
OUT (Store Register to I/O Port), 97
Parallel port programmer BAIFB, 175–76
Part numbering system, 273–74
Pascal compiler, 155–65
PDIP (plastic dual inline package), 7
Periods, programming timer, 189–95
Peripherals, 21–56
analog comparator, 43–48
serial interfaces, 32–37
SPI (serial peripheral interface), 32–37
timer/counters, 21–31
DART (universal asynchronous receiver and transmitter), 37–43
watchdog timer, 31–32
configurations of, 273–74
refreshing port, 127–28
PLCC (plastic J-Ieaded chip carrier), 7
Polling inputs, 128–29
PonyProg, serial port programmer, 176–77
POP (Pop Register from Stack), 98
Port pins, refreshing, 127–28
PortA, 51–52
PortB, 52–53
PortD, 54
Power-on reset, 59–60
Prescaler, Timer/Counter, 21
Program; See also Programs
constructs, 120–27
conditional branches, 120–23
program loops, 123–27
I/O register, 16–17
downloadable flash program memory, 14
EEPROM data memory, 17–21
general purpose register file, 16
SRAM data memory, 14–16
initialization defined, 7
installation defined, 7
loops, 123–27
defined loops, 124–25
endless loops, 126–27
undefined loops, 125–26
memories, 14–21
downloadable flash, 14
Programmer and evaluation boards, 168–77
AVR development board from Atmel, 169–71
ISP starter kit from Equinox, 171–73
parallel port programmer BA1FB, 175–76
serial port programmer PonyProg, 176–77
SIMMSTICK from Silicon Studio, 173–75
defensive, 127–29
duty cycles, 189–95
timer periods, 189–95
for AT90S1200, assembler, 180–228
for AT90S8515, assembler, 228–61
example, 179–272
in C, 261–65
assembler programs for AT90S8515, 228–61
in AVR BASIC, 265–72
example programs in AVR assembler, 179–261
Pull-down resistor defined, 7
Pull-up resistor defined, 7
PUSH (Push Register on Stack), 98
mode, 29–31
output frequency, 30
RAM (random access memory) defined, 6
RCALL (Relative Call to Subroutine), 98–99
IRD (read strobe), 55
Real-time clock/counter defined, 7
important registers, 127–28
port pins, 127–28
Register direct addressing, 63
I/O, 16–17
and Bit definitions, 281–86
files, 16
refreshing important, 127–28
circuit defined, 6
external, 60
and interrupt handling, 112–15
and interrupt system, 57–60
interrupt vector table, 57–58
reset sources, 58–60
power-on, 59–60
sources, 58–60
watchdog, 60
pull-down, 7
pull-up, 7
RET (Return from Subroutine), 99
RETI (Return from Interrupt), 99
architecture, 9
design philosophy, 4
RJMP (Relative Jump), 100
ROL (Rotate Left through Carry), 100
ROR (Rotate Right through Carry), 100–101
Routines, time-critical, 150–51
RS-232, fundamentals of, 287–91
RS-422, fundamentals of, 293–95
RS-485, fundamentals of, 293–95
RXC (Receive Complete bit), 41
RXCIE (RX Complete Interrupt Enable bit), 42
RXEN (Receiver Enable bit), 42
SBC (Subtract with Carry), 101
SBCI (Subtract Immediate with Carry), 101
SBI (Set Bit in I/O Register), 101–2
SBIC (Skip If Bit in I/O Register Is Cleared), 102
SBIS (Skip If Bit in I/O Register Is Set), 102
SBIW (Subtract Immediate from Word), 102–3
SBR (Set Bits in Register), 103
SBRC (Skip If Bit in Register Is Cleared), 103
SBRS (Skip If Bit in Register Is Set), 104
Schematics of SIMMSTICK Modules, 277–79
SEC (Set Carry Flag), 104
Security enhancement in data transmission by CRC, 215–18
SEH (Set Half Carry Flag), 104
SEI (Set Global Interrupt Flag), 105
SEN (Set Negative Flag), 105
SER (Set All Bits in Register), 105
for AT90S8515, 266–72
with internal UART, 235–37
Serial data exchange with SPI, 241
Serial port programmer PonyProg, 176–77
SES (Set Signed Flag), 106
SET (Set T Flag), 106
SEV (Set Overflow Flag), 106
SEZ (Set Zero Flag), 106–7
AVR BASIC from, 166–68
SIMMSTICK from, 173–75
from Silicon Studio, 173–75
Modules, 277–79
IAR CWA90 debugger, 151–53
16-Bit Timer/Counter, 24–31
SLEEP (Sleep), 107
I2C, 241–61
Atmel’s application, 301–3
SPI, 218–28
time delays, 195–98
UART, 202–10
SOIC (small-outline integrated circuit), 7
Source code, editing assembler, 134–39
Sources, reset, 58–60
SP (stack pointer), 12
SPCR (SPI Control register), 34
SPE (SPI Enable bit), 34
serial data exchange with, 241
software, 218–28
SPIE (SPI Interrupt Enable bit), 34
SPRx (SPI Clock Rate Select bits), 36
SPSR (SPI Status register), 33–34
SRAM (static random-access memory), 12
access to external, 54–56
data memory, 14–16
direct addressing, 65
indirect addressing, 65–69
memory, 9
SRE (External SRAM Enable bit), 52–53
SREG (status register), 12
(Store Indirect from Register to SRAM Using Index X), 107–8
(Store Indirect from Register to SRAM Using Index Y), 108
(Store Indirect from Register to SRAM Using Index Z), 109
Stack, 116–20
Structogram, 180–81
STS (Store Direct to SRAM), 109–10
SUB (Subtract without Carry), 110
SUBI (Subtract Immediate), 110
SWAP (Swap Nibbles), 111
in code area, 273–41
in EEPROM, 210–14
interrupt vectors, 57–58
TCCRIB (Timer/Counter1 control register), 25
Terminal defined, 7
Terms, 5–7
I/O ports defined, 6
EEPROM (electrical erasable and programmable read-only memory) defined, 6
EPROM (electrical programmable read-only memory) defined, 6
flash memory defined, 6
internal architecture defined, 5
Kbyte, 7
LSB (least significant bit), 7
Mbyte, 7
memory defined, 5–6
MSB (most significant bit), 7
oscillator defined, 6
OTP-ROM (one-time programmable EPROM) defined, 6
PDIP (plastic dual inline package), 7
PLCC (plastic J-Ieaded chip carrier), 7
initialization defined, 7
installation, 7
pull-down resistor defined, 7
pull-up resistor defined, 7
RAM (random access memory) defined, 6
real-time clock/counter defined, 7
reset circuit defined, 6
SOIC (small-outline integrated circuit), 7
terminal defined, 7
watchdog defined, 6
Tests, microcontroller, 265–66
Time delays, Software, 195–98
Time-critical routines, 150–51
Timer periods, programming, 189–95
Timer, watchdog, 31–32
Timer/CounterO, 8 -bit, 21–24
Timer/Counterl, 16 -Bit, 24–31
Timer/Counterl in PWM mode, 29–31
Timer/counter prescaler, 21
Timer/counters, 21–31
TIMSK (Timer Interrupt Mask register), 47
AVR, 148
development, 131–77
Tools > Program Device menu, 170
Transmission, data, 37–39
TST (Test for Zero or Minus), 111
TXC (TX Complete flag), 38
TXCIE (TX Complete Interrupt Enable bit), 42
TXEN (Transmitter Enable bit), 43
baud rate generator, 43
control, 40–43
data reception, 39–40
data transmission, 37–39
serial communication with internal, 235–37
software, 202–10
UCR (UART control register), 42
UDR (UART I/O Data register), 37–38
UDRIE (UART Data Register Empty Interrupt Enable bit), 42
Undefined loops, 125–26
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