Bibliography

[1] Nov Bailey, D., Benschneider, B. Clocking Design and Analysis for a 600-MHz Alpha Microprocessor. IEEE J. Solid-State Circuits. 1998;vol. 33(no. 11):1627–1633.

[2] Feb. Bearden, D., et al. A 133 MHz 64b Four-Issue CMOS Microprocessor. ISSCC Dig. Tech. Papers. 1995:174–175.

[3] Feb. Benschneider, B., et al. A lGHz Alpha Microprocessor. ISSCC Dig. Tech. Papers. 2000:86–87.

[4] Oct Boonstra, L., Lambrechtse, C., Salters, R. A 4096-b One-Transistor per Bit Random-Access Memory with Internal Timing and Low Dissipation. IEEE J. Solid-State Circuits. 1973;vol. SC-8(no. 5,):305–310.

[5] Feb. Bowhill, W., et al. A 300 MHz 64 b Quad-Issue CMOS Microprocessor. ISSCC Dig. Tech. Papers. 1995:182–183.

[6] Bowhill, W., et al. Circuit Implementation of a 300-MHz 64-Bit Second-Generation CMOS Alpha CPU. Digital Technology Journal. 1995;vol. 7(no. 1):100–119.

[7] June Burks, T., Sakallah, K., Mudge, T. Critical Paths in Circuits with Level-Sensitive Latches. IEEE Trans. VLSI Sys. 1995;vol. 3(no. 2):273–291.

[8] June Champernowne, A., Bushard, L., Rusterholtz, J., Schomburg, J. Latch-to-Latch Timing Rules. IEEE Trans. Comput. 1990;vol. 39(no. 6):798–808.

[9] Nov. Chao, T., Hsu, Y., Ho, J., Kahng, A. Zero Skew Clock Routing with Minimum Wirelength. IEEE Trans. Circuits Syst.-II. 1992;vol. 39(no. 11):799–814.

[10] May Chapiro, D., Globally-Asynchronous Locally Synchronous Systems. Ph.D. dissertation. Stanford, CA: CS Department, Stanford University; 1984.

[11] Nov. Chappell, T., Chappell, B., et al. A 2-ns Cycle, 3.8-ns Access 512-kb CMOS ECL SRAM with a Fully Pipelined Architecture. IEEE J. Solid-State Circuits. 1991;vol. 26(no. 11):1577–1585.

[12] Dec. Chu, K., Pulfrey, D. Design Procedures for Differential Cascode Voltage Switch Circuits. IEEE J. Solid-State Circuits. 1986;vol. SC-21(no. 6):1082–1087.

[13] Feb. Colwell, R., Steck, R. A 0.6μm BiCMOS Processor with Dynamic Execution. ISSCC Dig. Tech. Papers. 1995:176–177.

[14] Dally, W., Poulton, J. Digital Systems Engineering. New York: Cambridge University Press; 1998.

[15] Feb. DasGupta, S., Eichelberger, E., Williams, T. LSI Chip Design for Testability. ISSCC Dig. Tech. Papers. 1978:216–217.

[16] Nov Dobberpuhl, D., et al. A 200 MHz 64 b Dual-Issue CMOS Microproces-sor. IEEE J. Solid-State Circuits. 1992;vol. 27(no. 11):1555–1567.

[17] Dobberpuhl, D., et al. A 200-MHz 64-Bit Dual-issue CMOS Microprocessor. Digital Technology Journal. 1992;vol. 4(no. 4):35–50.

[18] Feb. Fair, H., Bailey, D. Clocking Design and Analysis for a 600 MHz Alpha Microprocessor. ISSCC Dig. Tech. Papers. 1998:398–399.

[19] Friedman E., ed. Clock Distribution Networks in VLSI Circuits and Systems. New York: IEEE Press, 1995.

[20] Feb. Gaddis, N., Lotz, J. A Quad-Issue Out-of-Order RISC CPU. ISSCC Dig. Tech. Papers. 1996:210–211.

[21] Nov. Gaddis, N., Lotz, J. A 64-b Quad-Issue CMOS RISC Microprocessor. IEEE J. Solid-State Circuits. 1996;vol. 31(no. 11):1697–1702.

[22] Feb. Gieseke, B., et al. A 600 MHz Superscalar RISC Microprocessor with Out-of-Order Execution. ISSCC Dig. Tech. Papers. 1997:176–177.

[23] Oct. Ginosar, R., Kol, R. Adaptive Synchronization. Proc. Intl. Conf. Comp. Design. 1998:188–189.

[24] June Gonclaves, N., De Man, H. NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures. IEEE J. Solid-State Circuits. 1983;vol. SC-18(no. 3):261–266.

[25] Sept. Gonzalez, R., Horowitz, M. Energy Dissipation in General Purpose Microprocessors. IEEE J. Solid-State Circuits. 1996;vol. 31(no. 9):1277–1284.

[26] Gronowski, P., Bowhill, B., Dynamic Logic and Latches—Part II. VLSI Circuits Symp. June. Proc. VLSI Circuits Workshop. 1996.

[27] Nov. Gronowski, P., et al. A 433-MHz 64-b Quad-Issue RISC Microprocessor. IEEE J. Solid-State Circuits. 1996;vol. 31(no. 11):1687–1696.

[28] May Gronowski, P., et al. High-Performance Microprocessor Design. IEEE J. Solid-State Circuits. 1998;vol. 33(no. 5):676–686.

[29] Dec. Hall, A., Synthesis of Double Rank Sequential Circuits. Tech. Report #53. EE Digital Systems Lab, Princeton University; 1966.

[30] Nov. Harris, D., Horowitz, M. Skew-Tolerant Domino Circuits. IEEE J. Solid-State Circuits. 1997;vol. 32(no. 11):1702–1711.

[31] July Harris, D., Oberman, S., Horowitz, M. SRT Division Architectures and Implementations. Proc. 13th IEEE Symposium on Computer Arithmetic. 1997.

[32] Feb. Heald, R., et al. Implementation of a 3rd-Generation SPARC V9 64b Microprocessor. ISSCC Dig. Tech. Papers. 2000:412–413.

[33] Feb. Heikes, C. A 4.5 mm2 Multiplier Array for a 200MFLOP Pipelined Coprocessor. ISSCC Dig. Tech. Papers. 1994:290–291.

[34] Feb. Heikes, C., Colon-Bonet, G. A Dual Floating Point Coprocessor with an FMAC Architecture. ISSCC Dig. Tech. Papers. 1996:354–355.

[35] Feb. Heller, L., Griffin, W., Davis, J., Thoma, N. Cascode Voltage Switch Logic: A Differential CMOS Logic Family. ISSCC Dig. Tech. Papers. 1984:16–17.

[36] Chapter 1. Hennessy, J., Patterson, D. Computer Architecture: A Quantitative Approach. San Francisco: Morgan Kaufmann; 1999.

[37] Hitchcock, R., Timing Verification and Timing Analysis Program. Years of Electronic Design Automation. New York: IEEE/ACM; 1988.

[38] Feb. Hofstee, P., et al. A 1 GHz Single-Issue 64b PowerPC Processor. ISSCC Dig. Tech. Papers. 2000:92–93.

[39] June Horowitz, M., High Frequency Clock Distribution. Proc. VLSI Circuits Workshop, VLSI Circuits Symp. 1996.

[40] IBM J. Research & Dev. 1996;vol. 40(no. 1).

[41] U.S. Patent #5, 517 Intel, Corporation. May 14. Opportunistic Time-Borrowing Domino Logic. 1996;136.

[42] Santa Clara, CA Intel, Corporation, Intel Microprocessor Quick Reference Guide. courtesy of Intel Museum. 1997.

[43] U.S. Patent #5,880,608, March 9 Intel, Corporation, Pulsed Domino Latches. 1999.

[44] Jan. Ishii, A., Leiserson, C., Papaefthymiou, M. Optimizing Two-Phase, Level-Clocked Circuitry. J. ACM. 1997;vol. 44(no. 1):148–199.

[45] Jouppi, N., Timing Verification and Performance Improvement of MOS VLSI Designs. Ph.D. thesis. Stanford University; 1984.

[46] Feb. von Kaenel, V., et al. A 600 MHz CMOS PLL Microprocessor Clock Generator with a 1.2 GHz VCO. ISSCC Dig. Tech. Papers. 1998:396–397.

[47] June Klass, F., Semi-Dynamic and Dynamic Flip-Flops with Embedded Logic. Symposium on VLSI Circuits Dig. Tech. Papers. 1998:108–109.

[48] May Klass, F., et al. A New Family of Semidynamic and Dynamic Flip-Flops with Embedded Logic for High-Performance Processors. IEEE J. Solid-State Circuits. 1999;vol. 34(no. 5):712–716.

[49] Krambeck, R., Lee, C., Law, H. High-Speed Compact Circuits with CMOS. IEEE J. Solid-State Circuits. 1982;vol. SC-17(no. 3):614–619.

[50] Apr. Kuskin, J., et al. The Stanford FLASH Multiprocessor. Proc. Intl. Symp. Comp. Arch.,. 1994:302–313.

[51] June Larsson, P., Svensson, C. Noise in Digital Dynamic CMOS Circuits. IEEE J. Solid-State Circuits. vol. 29(no. 6), 1994.

[52] June Lev, L., Signal and Power Network Integrity. Proc. VLSI Circuits Workshop, VLSI Circuits Symp. 1996.

[53] Nov. Lev, L., et al. A 64-b Microprocessor with Multimedia Support. IEEE J. Solid-State Circuits. vol. 30(no. 11), 1995.

[54] Feb. Lotz, J., et al. A Quad-Issue Out-of-Order RISC CPU. ISSCC Dig. Tech. Papers. 1996:210–211.

[55] Dec. Matsui, M., et al. A 200-MHz 13 mm2 2-D DCT Macrocell Using Sense-Amplifier Pipeline Flip-Flop scheme. IEEE J. Solid-State Circuits. 1994;vol. 29(no. 12):1482–1491.

[56] Mead, C., Conway, L. Introduction to VLSI Systems. Reading, MA: Addison-Wesley; 1980.

[57] Microprocessor Report. MicroDesign Resources: Sebastopol, CA, 1995.

[58] Nov. Montanaro, J., et al. A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor. IEEE J. Solid-State Circuits. 1996;vol. 31(no. 11):1703–1714.

[59] Apr. Moore, G. Cramming More Components onto Integrated Circuits. Electronics. 1965:114–117.

[60] Mukherjee, A. Introduction to nMOS and CMOS VLSI Systems Design. Englewood Cliffs, NJ: Prentice-Hall; 1986.

[61] Jan. Noice, D. A Clocking Discipline for Two-Phase Digital Integrated Circuits. Stanford University Technical Report. 1983.

[62] Oct. Nowka, K., Galambos, T. Circuit Design Techniques for a Gigahertz Integer Microprocessor. Proc. Intl. Conf. Comp. Design. 1998:11–16.

[63] July Ousterhout, J. A Switch-Level Timing Verifier for Digital MOS VLSI. IEEE Trans. Computer-Aided Design. 1985;vol. CAD-4(no. 3):336–349.

[64] Feb. Partovi, H., et al. Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements. ISSCC Dig. Tech. Papers. 1996:138–139.

[65] Chapter 5. Penny, W., Lau, L. MOS Integrated Circuits: Theory, Fabrication, Design and Systems Applications of MOS LSI. New York: Van Nostrand, Reinhold; 1973.

[66] Rabaey, J. Digital Integrated Circuits. Upper Saddle River, NJ: Prentice-Hall; 1996.

[67] Razavi B., ed. Monolithic Phase-Locked Loops and Clock Recovery Circuits. New York: IEEE Press, 1996.

[68] June Restle, P., Deutsch, A., Designing the Best Clock Distribution Network. Proc. VLSI Symp. 1998:2–5.

[69] July Rubinstein, J., Penfield, P., Horowitz, M. Signal Delay in RC Tree Networks,” IEEE Trans. Computer-Aided Design. 1983;vol. CAD-2(no. 3):202–211.

[70] Mar. Sakallah, K., Mudge, T., Olukotun, O. Analysis and Design of Latch-Controlled Synchronous Digital Circuits. IEEE Trans. Computer-Aided Design. 1992;vol. 11(no. 3):322–333.

[71] ( notes.sematech. org/97melec. htm) Semiconductor, Industry Association. The National Technology Roadmap for Semiconductors. Austin, TX: SEMATECH; 1997.

[72] Semiconductor, Industry Association, International Technology Roadmap for Semiconductors. 1999. http://www.itrs.net/199SIARoadmap/Home.htm.

[73] Shenoy, N., Timing Issues in Sequential Circuits. Ph.D. dissertation. Berkeley: University of California; 1993.

[74] Shenoy, N., Brayton, R., Sangiovanni-Vincentelli, A., A Pseudo-Polynomial Algorithm for Verification of Clocking Schemes. Tau, 92. 1992.

[75] July–Sept. Shepard, K., et al. Design Methodology for the S/390 Parallel Enterprise Server G4 Microprocessors. IBM J. Research and Development. 1997;vol. 41(no. 4–5):515–547.

[76] Aug. Shepard, K., Narayanan, V., Rose, R. Harmony: Static Noise Analysis of Deep Submicron Digital Integrated Circuits. IEEE Trans. Computer-Aided Design. 1999;vol. 18(no. 8):1136–1150.

[77] Sept. Shoji, M., Electrical Design of BELLMAC-32A Microprocessor. Proc. IEEE Int’l Conf. Circuits and Computers. 1982:112–115.

[78] Oct. Shoji, M. Elimination of Process-Dependent Clock Skew in CMOS VLSI. IEEE J. Solid-State Circuits. 1986;vol. SC-21(no. 5):875–880.

[79] Shoji, M. High-Performance CMOS Circuits. Englewood Cliffs, NJ: Prentice-Hall; 1988.

[80] Feb. Singer, G., Rusu, S. The First 1A-64 Microprocessor: A Design for Highly Parallel Execution. ISSCC Dig. Tech. Papers. 2000:422–423.

[81] Apr. Stojanovic, V., Oklobdzija, V. Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems. IEEE J. Solid-State Circuits. 1999;vol. 34(no. 4):536–548.

[82] Sutherland, I., Sproull, R., Harris, D. Logical Effort. San Francisco, CA: Morgan Kaufmann; 1999.

[83] Szymanski, T., LEADOUT: A Static Timing Analyzer for MOS Circuits. ICCAD-86Dig. Tech. Papers. 1986:130–133.

[84] Szymanski, T., Computing Optimal Clock Schedules. Proc. 29th Design Automation Conf. 1992:399–404.

[85] Nov. Szymanski, T., Shenoy, N. Verifying clock schedules. ICCAD Dig. Tech. Papers. 1992:124–131.

[86] May Takahashi, O., Aoki, N., Silberman, J., Dhong, S. A 1-GHz Logic Circuit Family with Sense Amplifiers. IEEE J. Solid-State Circuits. 1999;vol. 34(no. 5):616–622.

[87] Nov. Thorp, T., Yee, G., Sechen, C., Domino Logic Synthesis Using Complex Gates. Proc. Intl. Conf. Computer-Aided Design. 1998.

[88] Feb. Tsay, R. An Exact Zero-Skew Clock Routing Algorithm. IEEE Trans. Computer-Aided Design. 1993;vol. 12(no. 2):242–249.

[89] Oct. Unger, S., Tan, C. Clocking Schemes for High-Speed Digital Systems. IEEE Trans. Comput. 1986;vol. C-35(no. 10):880–895.

[90] Nov. Vasseghi, N., et al. 200 MHz Superscalar RISC Processor. IEEE J. Solid-State Circuits. 1996;vol. 31(no. 11):1675–1686.

[91] March Vittal, A., Marek-Sadowska, M. Crosstalk Reduction for VLSI. IEEE Transactions on CAD. 1997;vol. 16(no. 3):290–298.

[92] Weste, N., Eshraghian, K. Principles of CMOS VLSI Design. Reading, MA: Addison-Wesley; 1993:351.

[93] May Williams, T., Self-Timed Rings and Their Application to Division. Ph.D. dissertation. Stanford, CA: EE Department, Stanford University; 1991.

[94] Nov. Williams, T., Horowitz, M. A Zero-Overhead Self-Timed 160-ns 54-b CMOS Divider. IEEE J. Solid-State Circuits. 1991;vol. 26(no. 11):1651–1661.

[95] Ye, Y. Interior Point Algorithms: Theory and Analysis. New York: Wiley; 1997.

[96] Feb. Yuan, J., Svensson, C. High Speed CMOS Circuit Technique. IEEE J. Solid-State Circuits. 1989;vol. 24(no. 1):62–69.

[97] Jan. Yuan, J., Svensson, C. New Single-Clock SMOS Latches and Flipflops with Improved Speed and Power Savings. IEEE J. Solid-State Circuits. 1997;vol. 32(no. 1):62–69.

[98] Dec. Yuan, J., Svensson, C., Larsson, P. New Domino Logic Precharged by Clock and Data. Electronics Letters. 1993;vol. 29(no. 25):2188–2189.

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