PLL Ideal Behavior

A PLL will adjust the phase of its output such that its reference input REFclk and its feedback clock are perfectly aligned, or in phase.

Consider the ASIC PLL circuit shown in Figure C.2. In this ideal circuit, the PLL will perfectly align the arrival time of the feedback clock, t_FB, with the arrival time of the reference clock, t_REF (t_FB = t_REF). The output of the PLL is distributed throughout the ASIC with the use of a clock-distribution network that is perfectly balanced such that the delay from the PLL output to every ASIC register is equal (dly_a = dly_b).

The arrival time of the PLL output can be expressed as:

Equation C.1

Since in this ideal case t_REF = t_FB and dly_a = dly_b,

Equation C.2

or

Equation C.3

and the arrival time of the clock at a register, regA, can be expressed as

Equation C.4

So, in this case, the arrival time of a clock at any register is perfectly aligned with t_REF. Note that the delay of the clock-distribution network is not a term of the arrival time, t_A. This shows how a PLL can be used to minimize the effects of on-chip clock latency.

Consider also two ASICs fed by the same clock, but whose clock-distribution networks have different latency times. Using PLLs in each of the ASICs will make the respective clocks appear to be in phase with each other.

Equation C.5

and

Equation C.6

hence,

Equation C.7