Accelerated Strategic Computing Initiative (ASCI)

Address generation interlock (AGI)

Algorithm and data structures See also General matrix-matrix multiplication (GEMM)

    design rules

    differences

    molecular dynamics (MD)

        efficient vectorization and optimal cache reuse

        molecules and atoms

        scalable parallelization

    Monte Carlo simulation

        efficient vectorization

        European option pricing

        optimal cache reuse

        scalable parallelization

    stencil operations

        efficient vectorization

        graphical representation

        optimal cache reuse

        scalable parallelization

Application design and implementation

    algorithms and data structures

    challenges

        data and task dependency

        load imbalance

        parallelization overhead

        shared resource access overhead

    communications

        file input/output (I/O)

    data alignment considerations

    data transfer BW optimization

    grid shape

        algorithm considerations

        data structure

        load balance

        offload overhead

    memory management

    mixed-precision arithmetic

    parallel implementation

    workload considerations

    workload-related

        Amdahl’s law

        Gustafson’s law

        scaled speedup

        serialization

Application development tools, Xeon Phi

    APIs

    asynchronous data transfer over PCI express

    CAPS compiler

    categories

    debugging applications

    IDB

    Intel C/C++ Composer XE

    Intel Cluster tools

        Bright Cluster Manager

        PBS Professional

    Intel Fortran composer XE

        APIs

        directives

        macros

    Intel Vtune Amplifier XE

    intrinsics

        C++ class libraries

    keywords

        _Cilk_offload and _Cilk_shared

        rules

        using shared virtual memory

    libraries

        automatic offload version

        compiler-assisted offload

        native/symmetric execution

    macros

        _INTEL_OFFLOAD macro

        _KNC_ macro

        _MIC_ macro

    OpenMP 4.0 extensions

    pragmas

        offload_attribute

        offload_transfer and offload_wait

        pragma offload

    third-party compilers

    third-party debuggers

        DDT

        GNU debugger

        TotalView

    third-party math libraries

        ArrayFire

        Magma MIC

Application programming interfaces (APIs) See also Intel Xeon Phi architecture

    compiler options

    environment variables

        MIC_ENV_PREFIX

        MIC_LD_LIBRARY_PATH

        MIC_PROXY_IO

        MIC_STACKSIZE

        OFFLOAD_DEVICES

        OFFLOAD_INIT

        OFFLOAD_REPORT

    offload libraries

Array of Structures-to-Structure of Arrays (AoS-to-SoA) transformation

Best-known methods (BKMs)

Boot strap processor (BSP)

Cilk Plus notation

Cluster-Level Tuning

Computer-aided design (CAD)

Computer architecture (cache subsystem)

Coprocessor Communication Link (CCL)

Cyclic redundancy control (CRC)

Data structures. See Algorithm and data structures

Detecting application execution

    code execution issues

    data access issues/stalls

        bandwidth saturation

        memory access latencies

        TLB issues

    hotspot

    locate hotspots

    parallel execution overhead

    performance events

    system-level issues

Development tools, Xeon Phi

    language extensions

        compiling and running

        host and coprocessor

        IDE

        link time

        nonshared memory program

        virtual shared memory

    offload environment variables

Direct memory access (DMA)

Distribute Debugging Tool (DDT)

DMA engine

    channel descriptor ring

    device data transfer

        align(ALIGN)

        #define ALIGN

        pciebw.out application

        pciebw test run output

        #pragma offload target(mic)

    device-to-host data transfer

    most significant bit

    SCIF

Efficient vectorization

Elapsed-time counter (ETC)

Error correction code (ECC)

General matrix-matrix multiplication (GEMM)

    efficient vectorization

    scalable parallelization and optimal cache reuse

    triple-nested loop

Global descriptor table (GDT)

GNU debugger (GDB)

Heterogeneous manycore architecture

High-level optimization (HLO)

Host channel adaptor (HCA)

InfiniBand host channel adaptor (HCA)

Installable client driver (ICD)

Instruction fetches (IF)

Instruction set architecture (ISA)

Intel C++ Compiler

Intel Cluster tools

    Bright Cluster Manager

    PBS Professional

Intel debugger (IDB)

Intelligent Platform Management Bus (IPMB) protocol

Intel Math Kernel Library (MKL)

Intel Threading Building Blocks (TBB)

Intel Vtune Amplifier XE

Intel Xeon Phi architecture

    coprocessor card

    core and memory

        instruction-level parallelism

        multicore and manycore architecture

        multithreading

        pipeline stages

        SIMD feature

    critical chip components

    evolution

        computer architecture (cache subsystem)

        Von Neumann architecture

    features

    hardware architecture

    history

    interconnect and cache improvements

        manycore processor architecture

        system interconnect

    Larrabee 1 silicon block diagram

    logical layouts

    microarchitectural design

    MPI and KNC

    pipeline

        increased clock rate

        instruction

        out-of-order instruction execution

        stages

        superscalar architecture

    SIMD and SMT

    technical computing

Interconnect topologies

    bidirectional ring topology

    2D mesh topology

    3D mesh topology

    2D torus topology

    3D torus topology

    fat tree topology

    GDDR memory characteristics

    hierarchical ring networks

    L2 cache

        cache coherency protocol

        Data transactions

        hardware prefetcher

        Tag directory

    memory transactions

        cacheable and uncacheable

        cache hierarchy

        control and data flow

    ringstops

Knights Corner (KNC)

Linux development environment. See Windows OS application

Linux virtual file system (Sysfs and Procfs)

    current configuration

    /proc virtual file system

    SCIF layer

    Xeon Phi Coprocessor Sysfs virtual file system /sys

Many Integrated Core (MIC)

Math Kernel Library (MKL)

Memory interconnects

    Intel Xeon Phi coprocessors

    PCIe and I/O protocol

    system

Message Passing Interface (MPI)

MIC system management and configuration (micsmc)

Molecular dynamics (MD)

    efficient vectorization and optimal cache reuse

    molecules and atoms

    scalable parallelization

Monte Carlo simulation

    efficient vectorization

    European option pricing

    optimal cache reuse

    scalable parallelization

Multicore and manycore architecture

Multiple instructions and multiple data (MIMD)

Multithreading

Network File System (NFS)

Open Computing Language (OpenCL)

    building and running

    installation purposes

        packages

        rpm packages

        steps

    performance optimization

Open Fabrics Enterprise Distribution (OFED)

Optimal cache reuse

Optimizing code

    compiler-driven optimizations

        code restructuring techniques

        prefetching

    data alignment

    Intel Cilk Plus array notation

        Intel Compiler

        OpenMP/Cilk Plus/TBB

    large pages

        cache blocking

        loop fusion/fission

        loop interchange

        loop peeling

        loop unrolling

        page size

        THP

        unroll and jam

    removing pointer aliasing

    steaming store

    vectorization

        compiler report

        vectorizing code

Particle dynamics/n-body applications. See Molecular dynamics (MD)

Peripheral Component Interconnect Express (PCIe)

Power management and reliability features

    coprocessor OS

    core C6 state

    CRC and ECC protection

    C0 state

    C1 state

    demand-based switching

    host driver component

    idle state selection

    Package C3 state

    power reduction

    P-states

Printed circuit board (PCB)

Processor microarchitecture

Remote direct memory access (RDMA)

Ring 0 driver layer components. See also MIC Platform Software Stack (MPSS)

    application and system functionalities

    coprocessor OS

    Linux virtual file system (Sysfs and Procfs)

        current configuration

        /proc virtual file system

        SCIF layer

        Xeon Phi Coprocessor Sysfs virtual file system /sys

    mic0

    MPSS stack during runtime

    network stacks

    NFS

    OFED and MPI

    system boot process

    system software application components

        miccheck

        micctrl

        micflash

        micinfo

        micnativeloadex

        micrasd

        micsmc

    third-party coprocessor OS

        ‘dmesg’ output

        GDT

        POST code

Scalable parallelization

Short Vector Math Library (SVML)

Single instruction multiple data (SIMD)

Single program multiple data (SPMD)

Software Development Kit (SDK)

Stencil operations

    efficient vectorization

    graphical representation

    optimal cache reuse

    scalable parallelization

Superscalar architecture

Swizzle

    command

    data broadcast

    data conversions

    operation with vector instructions

    register memory

    register operation

    shuffles

    and shuffles instructions code

Symmetric communication interface (SCIF)

Symmetric multithreading (SMT)

System interconnect. See Memory interconnects

System interface unit (SIU)

System management bus (SMBus)

System management component and controller (SMC)

System management controller (SMC)

System software components See also Ring 0 driver layer components

    application components

        miccheck

        micctrl

        micflash

        micinfo

        micnativeloadex

        micrasd

        micsmc

    application layer

    Xeon Phi software layers

Threading building blocks (TBB)

Timing applications

Transaction control unit (TCU)

Translation look-aside buffer (TLB)

Transparent huge page (THP)

Tuning application See also Detecting application execution; Optimizing code

    baseline data

    BKMs

    cluster-level tuning

    Math Kernel Library

    node-level optimization cycle

    optimization process

    target performance

    timing applications

U-Pipelines

Vector ISA

    arithmetic and logic operation

        carry propagate instructions

        fused multiply-add

    categories

        conversions, data

        data broadcasts

        mask operations

        register memory swizzle

        shuffles

        swizzle commandoperation

    code, swizzle and shuffle

    data access operations

        memory alignment

        non-temporal data

        pack/unpack

        prefetch instructions

        scatter/gather

        streaming stores

    data types

    operand performance

    shift operation

        arithmetic

        logical shift

    type conversion, memory load

    vector instruction syntax

    vector nomenclature

Vector processing unit (VPU)

Virtual ethernet (VE)

Virtual shared memory model

Virtual shared memory programming

    dynamic memory allocation

    functions

        _Cilk_shared void f()

        _Cilk_offload keyword

        error message

        for loop expression

        rules

        synchronous and asynchronous execution

    Host and Coprocessors

    host compile time

    illegal access error

    linked list data structures

    multiple host threads

    shared_allocator<T>

    static fields

    variable declaration

Visual Studio Integrated Development Environment (IDE)

Von Neumann architecture

V-Pipelines

VPU pipeline

    double precision (DP)

    extended math unit (EMU)

    instruction stalls

        DP instruction

        EMU instruction

        SP/SP-independent instruction pipeline

    mask pipeline

    pairing rules

    scatter/gather pipeline

    single precision (SP)

    stages, core pipeline

    store pipeline

    vector execution pipeline

VTune Amplifier XE tool

Windows OS application. See also Development tools, Xeon Phi

    CAD

    debugging offload execution

        PuTTY

        steps

    MPSS installation

        micctrl

        MicFlash

        MicInfo tool

        MicRas

        MicSmc

        package

        SDK (Binutils)

        system components

    native programs build applications

    VTune Amplifier XE tool

Xeon Phi

    code generation

        execution mode

        MIC architecture

        offload syntax

    development tools

        Intel Composer XE

        software

    execution models

    installation

        development tools

        MPSS stack

    language extensions

        declare functions and variables

        execution constructs

        heterogeneous computing model

        modification

        Offload Pragmas

        OFFLOAD_REPORT

        reduce function

        restrictions

        runtime library

        target update

        terminology

    software performance

    tools (see Application development tools, Xeon Phi)

Xeon Phi coprocessors

    COI and SCIF

    components

        APIC logic

        PCB

        SIU and TCU

        SMBus

        SMC

        SPI

    DMA engine

    DMA transfer

    PCIe slots

    system configuration

Xeon Phi core architecture

    cache

    computing

    lmbench benchmark

    L2 cache

    pipeline stages

        ALUs

        D0 stage

        D1 and D2 stage

        global stall pipeline architecture

        instruction fetch

        picker function

        pre-thread picker function

        TLB

        4-way multithreaded

        WB stage

    time-multiplexed multithreading

        AGI

        Gflops operations

        pairing rules

        prefix decode

    TLB

        linear address

        page table data structures

        paging mechanism

        transparent huge page

    turbo modes

    vector units

    2-wide processor

Xeon Phi Vector

    instruction set architecture (ISA)

        code, swizzle and shuffle

        data access operations

        data types

        fused multiply and add (FMA)

        groups (categories)

        instruction, syntax

        logical and arithmetic operations

        mask operation

        memory load type conversion

        operand performances

        shift (logical and arithmetic) operation

        swizzle (see Swizzle)

        vector nomenclature

    microarchitecture

        extended math unit (EMU)

        latency and throughput of transcendental functions

        vector mask registers

        vector registers

        VPU pipeline (see VPU pipeline)

    vector processing unit (VPU)