1.6. The Life Cycle of Computer Architectures
Successive implementations of a computer architecture are routinely brought forth by a hardware innovator at fairly frequent intervals. A completely new architecture, or a whole new class of architectures, appears much less frequently.
Contemporary architectures fall into three classes. Complex Instruction Set Computers (CISC) typically include large numbers of machine instructions of many different styles. That complexity poses difficulties of implementation, because each style of instruction may require substantial real estate on the computer chip. Reduced Instruction Set Computers (RISC) are defined by smaller numbers of machine instructions of very few styles. The savings in space on a computer chip can, in favorable situations, make possible intrinsically faster circuitry. RISC programs can thus potentially execute faster than CISC programs, even though they usually contain more machine instructions. The third and newest class of contemporary architecture, Explicitly Parallel Instruction Computers (EPIC), includes the Itanium architecture that this book uses as its central example.
Computer architectures may also be classified according to the width of the datapath, the internal components through which information flows—e.g., 64 bits for Itanium architecture.
When new architectures emerge, they may appear to be evolutionary because they evince strong family resemblances to earlier architectures from the same vendor. On the other hand, they may appear revolutionary because they offer a clean break with the past. We now illustrate these concepts through the history of three families of computer architectures.
1.6.1. The 32-Bit Intel® Architecture and Its Predecessors
In 1971, Intel® Corporation integrated all of the traditional functionality of a central processing unit (CPU) into a single microcomputer chip, given the marketing number 4004. This pioneering chip could handle data 4 bits at a time and could access 640 bytes of memory. A year later, the 8008 microprocessor chip appeared with the ability to handle data 8 bits at a time and access 16,384 bytes of memory.
Table 1-3 looks at the characteristics of successive members of the family of processors starting with the Intel 8080, which was the basis for some of the earliest inexpensive general-purpose personal computers. As memory technologies improved, the push toward convenient addressing of larger amounts of memory drove Intel and other manufacturers to redesign their products with successively greater widths for the internal registers and pathways where addresses (pointers) as well as data are manipulated. By 1990 this trend settled on 32 bits as the prevailing standard register width for even the smallest computers, which had come to be called microcomputers because of their physical size, and not as a measure of their computing power.
An important feature of these Intel processors is that each generation can execute most programs prepared for the previous generation because of similarities of integer registers. The right half of a 16-bit register can be used to manipulate 8-bit integers, the right half of a 32-bit register can be used to manipulate 16-bit integers, and the right quarter of a 32-bit register can be used to manipulate 8-bit integers. Assembly language programs written for the 8080 could automatically be translated into a format suitable for the 8086 processor, and programs written for the 16-bit processors can run directly on the 32-bit processors. We shall discuss some of the other information in Table 1-3 in later sections of this book.
1.6.2. The Alpha™ Architecture and Its Predecessors
The design of the IBM System/360 strongly influenced many subsequent computer architectures, including 16-bit minicomputers brought forth by numerous manufacturers during the 1970s. Quite possibly the most successful among those designs, the PDP®-11 by Digital® Equipment Corporation, not only persisted through about a dozen implementations over more than two decades, but also came to be seen as the progenitor of families of 32-bit VAX® and 64-bit Alpha™ computers.
Some of the attributes of the PDP11, VAX, and Alpha product lines are summarized in Table 1-4. The VAX (Virtual Addressing eXtension) is frequently cited as the exemplar of a Complex Instruction Set Computer (CISC). The Alpha processor was the first 64-bit Reduced Instruction Set Computer (RISC) to attain wide commercial deployment. Several other manufacturers had already marketed successful 32-bit RISC designs, but Digital Equipment Corporation opted to make its move to 64 bits simultaneously with its move from CISC to RISC. We shall discuss some of the other information in Table 1-4 later in this book.
| Datapath width | 8 bits (1 byte) | 16 bits (2 bytes) | 32 bits (4 bytes) |
|---|---|---|---|
| Marketing names | 8080, 8085 | 8086, 8088, 80286 | Intel386™, Intel486™, Pentium® |
| Physical formats | single chip | single chip | single chip |
| Complexity classification | classic micro | CISC | CISC |
| Number of integer registers | 8 | 14 | 16 |
| Interchangeability of registers | almost none | some | moderate |
| Instruction size | 1, 2, 3 bytes | 1–4 bytes | 1–17 bytes |
| Number of instruction styles | 7 | byte stream | byte stream |
| Number of opcodes | 74 | 133 | 154 |
| Number of operands | 0, 1, 2 | 0, 1, 2, 3 | 0, 1, 2, 3 |
| Allowed memory access | few instructions | many instructions | many instructions |
| Number of addressing modes | 6 | 8 | 8+ |
| Number of integer data types | 2 | 3 | 4 |
| Number of floating data types | 0 | 3[*] | 3[*] |
| Byte ordering | little-endian | little-endian | little-endian |
| Unidirectional branch range | full-range 64 KiB COND and JUMP | 127 bytes | 32 KiB |
| Logical address space | 64 KiB | 1 MiB[†] | 4 GiB[†] |
| Input/output strategy | IN, OUT | memory-mapped; IN, OUT | memory-mapped; IN, OUT |
| Date of introduction | 1974 | 1978 | 1985 |
[*] Floating-point operations required a second chip for all 16-bit processors and some 32-bit processors.
[†] Initially; subsequently extended.
| Datapath width | 16 bits (2 bytes) | 32 bits (4 bytes) | 64 bits (8 bytes) |
|---|---|---|---|
| Marketing names | PDP-11, LSI-11 | VAX, MicroVAX | Alpha |
| Physical formats | circuit board(s), single chip | circuit board(s), single chip | single chip |
| Complexity classification | classic mini | CISC | RISC |
| Number of integer registers | 8 | 16 | 32 |
| Interchangeability of registers | extensive | extensive | extensive |
| Instruction size | 2, 4, 6 bytes | 1 – 37 bytes | 4 bytes |
| Number of instruction styles | 6 | byte stream | 7 |
| Number of opcodes | > 100 | > 256 | > 100 |
| Number of operands | 0, 1, 2 | 0–6 | 0–3 |
| Allowed memory access | many instructions | many instructions | only load/store |
| Number of addressing modes | 8 | 12 | 2 |
| Number of integer data types | 2 | 5 | 2 |
| Number of floating data types | 2 | 4 | 5 |
| Byte ordering | little-endian | little-endian | little-endian[*] |
| Unidirectional branch range | 255 bytes | 127 bytes | 4 MiB |
| Logical address space | 64 KiB | 4 GiB | 16 EiB |
| Input/output strategy | memory-mapped | memory-mapped | memory-mapped |
| Lifetime as a marketed product | 1971–1995 | 1978–2000 | 1992– |
[*] Initially; subsequently extended.
1.6.3. The Itanium® Architecture and Its Predecessors
Both the VAX architecture and Intel's 32-bit architecture are cited as exemplars of Complex Instruction Set Computers (CISC). At the implementation level, the circuitry required on a chip to recognize and carry out many different styles of instructions can be elaborate and difficult to optimize for fast execution times. By the 1980s, research in computer science had led to serious proposals for a different approach to high performance: Select fewer instructions and design ways to execute them exceedingly quickly, rather than introduce more instructions of increasing specialization.
Although Intel engineers continually found ways to bring out further implementations of a successful 32-bit architecture without compromising performance, several other computer makers redirected their attention to the design of Reduced Instruction Set Computers (RISC). Hewlett-Packard® Company developed a 32-bit architecture that was at first called Precision Architecture, and later PA-RISC®. The salient features of RISC processors include fixed-size instructions, fewer instructions overall, larger numbers of integer registers to be used in similar ways, and restrictions on the number of instruction types that can directly manipulate data in the computer's memory. The 64-bit Alpha architecture (Table 1-4) and the 32- and 64-bit PA-RISC architectures (Table 1-5) follow these RISC principles.
Even as CISC and RISC designs coexisted amongst marketed computer systems in the 1990s, Intel collaborated with Hewlett-Packard in developing another fundamental class of computer architecture, Explicitly Parallel Instruction Computers (EPIC). In essence, an EPIC computer can simultaneously pursue more than one course of action, thus gaining a throughput advantage. An EPIC design can avoid certain time penalties that plague other architectures when the flow of instructions in a program has to change abruptly, as must occur for loop control. The earliest commercial product using EPIC design principles is the 64-bit Itanium processor, whose characteristics are compared with PA-RISC in Table 1-5.
1.6.4. The Naming of Architectures and Implementations
Sometimes the same or similar names have been given both to an architecture and to its implementations. In the case of VAX architecture, “VAX” was incorporated into the name of every implementation; moreover, the ISA remained very stable during the long prevalence of this architecture in the marketplace. There is no such continuing thread connecting the names of implementations within the various generations of products from Intel or several other corporations.
Intel Corporation has at various times designated its 16-, 32-, and 64-bit instruction sets as IA-16, IA-32, and IA-64. Any popular ISA, such as IA-32, accrues additional instructions over time. This leads to an ambiguity: whether the original designation defines the basic instruction set or the currently augmented set. Neither “IA-16” nor “IA-32” has appeared prominently in commercial product descriptions.
Intel used the phrase “IA-64 architecture” while the new 64-bit architecture was under development, but changed to “Itanium architecture” when marketing the first implementation, which was called “the Itanium processor.” As the Itanium 2 processor (code name McKinley) reached production, Intel established the primacy of “Itanium Architecture” over “IA-64” or the lesser-known “Itanium Processor Family” (IPF). Thus, just as with VAX architecture and VAX processor implementations, we must accept some blurring of the distinction between the naming of an architecture and any implementation.
| Datapath width | 32 bits (4 bytes) | 64 bits (8 bytes) | 64 bits (8 bytes) |
|---|---|---|---|
| Marketing names | PA-RISC® 7xxx | PA-RISC® 8xxx | Itanium® |
| Physical formats | circuit board(s), single chip | single chip | single chip |
| Complexity classification | RISC | RISC | EPIC |
| Number of integer registers | 32 | 32 | 128 |
| Instruction size | 4 bytes | 4 bytes | (3 × 41) + 5 bits |
| Number of instruction styles | ~13 | > 20 | 6 |
| Number of principal opcodes | 45 | 59 | 41 |
| Number of operands | 0–3 | 0–3 | 0–5 |
| Allowed memory access | only load/store | only load/store | only load/store |
| Number of addressing modes | 4 | 4 | 5 |
| Number of integer data types | 5 | 5 | 4 |
| Number of floating data types | 3 | 3 | 3 |
| Byte ordering | big-endian[*] | big-endian, little-endian | little-endian, big-endian |
| Unidirectional branch range | 256 KiB | 256 KiB | 16 MiB |
| Logical address space | 4 GiB[*] | 15 EiB | 16 EiB |
| Input/output strategy | memory-mapped | memory-mapped | memory-mapped |
| Date of introduction | 1986 | 1996 | 2001 |
[*] Initially; subsequently extended.
The code-name issue deserves further discussion: When a company has something new under development, the company (or the trade press) may use a code name for it. The trade press wrote for several years about “Merced” as something forthcoming from Intel Corporation. It was not always clear whether Merced meant an implementation or an architecture. Furthermore, some future author writing retrospectively about Itanium architecture and/or the original Itanium processor might miss a lot of historical source material without using the Merced, IA-64, IA-64, and IPF as additional search keywords.