7493 4-Bit Ripple Counter with Separate MOD-2 and MOD-8 Counter Sections

The 7493's internal structure consists of four JK flip-flops connected to provide separate MOD-2 (0-to-1 counter) and MOD-8 (0-to-7 counter) sections. Both the MOD-2 and MOD-8 sections are clocked by separate clock inputs. The MOD-2 section uses C_p0 as its clock input, while the MOD-8 section uses C_p1 as its clock input. Likewise, the two sections have separate outputs: MOD-2's output is Q₀, while MOD-8's outputs consist of Q₁, Q₂, and Q₃. The MOD-2 section can be used as a divide-by-2 counter. The MOD-8 section can be used as a divide-by-2 counter (output tapped at Q₁), a divide-by-4 counter (output tapped at Q₂), or a divide-by-8 counter (output tapped at Q₃). If you want to create a MOD-16 counter, simply join the MOD-2 and MOD-8 sections by wiring Q₀ to C_p1, while using C_p0 as the single clock input.

The MOD-2, MOD-8, or the MOD-16 counter can be cleared by making both AND-gated master reset inputs (MR₁ and MR₂) high. To begin a count, one or both of the master reset inputs must be made low. When the negative edge of a clock pulse arrives, the count advances one step. After the maximum count is reached (1 for MOD-2, 111 for MOD-8, or 1111 for MOD-16), the outputs jump back to zero, and a new count begins.

7490 4-Bit Ripple Counter with MOD-2 and MOD-5 Counter Sections

The 7490, like the 7493, is another 4-bit ripple counter. However, its flip-flops are internally connected to provide MOD-2 (count-to-2) and MOD-5 (count-to-5) counter sections. Again, each section uses a separate clock: C_p0 for MOD-2 and C_p1 for MOD-5. By connecting Q₀ to C_p1 and using C_p0 as the single clock input, a MOD-10 counter (decade or BCD counter) can be created.

When master reset inputs MR₁ and MR₂ are set high, the counter's outputs are reset to 0—provided that master set inputs MS₁ and MS₂ are not both high (the MS inputs override the MR inputs). When MS₁ and MS₂ are high, the outputs are set to Q₀ = 1, Q₁ = 0, Q₂ = 0, and Q₃ = 1. In the MOD-10 configuration, this means that the counter is set to 9 (binary 1001). This master set feature comes in handy if you wish to start a count at 0000 after the first clock transition occurs (with master reset, the count starts out at 0001).

7492 Divide-by-12 Ripple Counter with MOD-2 and MOD-6 Counter Sections

The 7492 is another 4-bit ripple counter that is similar to the 7490. However, it has a MOD-2 and a MOD-6 section, with corresponding clock inputs C_p0 (MOD-2) and C_p1 (MOD-8). By joining Q₀ to C_p1, you get a MOD-12 counter, where C_p0 acts as the single clock input. To clear the counter, high levels are applied to master reset inputs MR₁ and MR₂.

74193 Presettable 4-Bit (MOD-16) Synchronous Up/Down Counter

The 74193 is a versatile 4-bit synchronous counter that can count up or count down and can be preset to any count desired—at least a number between 0 and 15. There are two separate clock inputs: C_pU is used to count up, and C_pD is used to count down. One of these clock inputs must be held high in order for the other input to count. The binary output count is taken from Q₀ (2⁰), Q₁ (2¹), Q₂ (2²), and Q₃ (2³).

To preset the counter to any desired count, a corresponding binary number is applied to the parallel inputs D₀ to D₃. When the parallel load input is pulsed low, the binary number is loaded into the counter, and the count, either up or down, will start from that number. The terminal count up ( ) and terminal count down ( ) outputs are normally high. The output is used to indicate when the maximum count has been reached and the counter is about to recycle to the minimum count (0000)—the carry condition. Specifically, this means that goes low when the count reaches 15 (1111) and the input clock (C_pU) goes from high to low. remains low until C_pU returns high. This low pulse at can be used as an input to the next high-order stage of a multistage counter. The terminal count down ( ) output is used to indicate that the minimum count has been reached (0000) and the counter is about to recycle to the maximum count 15 (1111)—the borrow condition. Specifically, this means that goes low when the down count reaches 0000 and the input clock (C_pD) goes low. Figure 12.90 provides a truth table for the 74193, along with a sample load, up-count, and down-count sequence.

74192 Presettable Decade (BCD or MOD-10) Synchronous Up/Down Counter

The 74192, shown in Fig. 12.91, is essentially the same device as the 74193, except it counts up from 0 to 9 and repeats or counts down from 9 to 0 and repeats. When counting up, the terminal count up ( ) output goes low to indicate when the maximum count is reached (9 or 1001) and the C_pU clock input goes from high to low. remains low until C_pU returns high. When counting down, the terminal count down output ( ) goes low when the minimum count is reached (0 or 0000) and the input clock C_pD goes low. The truth table and example load, count-up, and count-down sequence provided in Fig. 12.91 explain how the 74192 works in greater detail.

74190 Presettable Decade (BCD or MOD-10) and 74191 Presettable 4-Bit (MOD-16) Synchronous Up/Down Counters

The 74190 and the 74191 do basically the same things as the 74192 and 74193, but the input and output pins, as well as the operating modes, are a bit different. (The 74190 and the 74191 have the same pinouts and operating modes; the only difference is the maximum count.) Like the previous synchronous counters, these counters can be preset to any count by using the parallel load operation. However, unlike the previous synchronous counters, to count up or down requires using a single input: . When is set low, the counter counts up; when is high, the counter counts down.

A clock enable input ( ) acts to enable or disable the counter. When is low, the counter is enabled. When is high, counting stops, and the current count is held fixed at the Q₀ to Q₃ outputs.

Unlike the previous synchronous counters, the 74190 and the 74191 use a single terminal count output (TC) to indicate when the maximum or minimum count has occurred and the counter is about to recycle. In count-down mode, TC is normally low but goes high when the counter reaches zero (for both the 74190 and 74191). In count-up mode, TC is normally low but goes high when the counter reaches 9 (for the 74190) or reaches 15 (for the 74191).

The ripple-clock output ( ) follows the input clock (CP) whenever TC is high. This means, for example, that in count-down mode, when the count reaches zero, will go low when CP goes low. The output can be used as a clock input to the next higher stage of a multistage counter. This, however, leads to a multistage counter that is not truly synchronous because of the small propagation delay from CP to of each counter. To make a multistage counter that is truly synchronous, you must tie each IC's clock to a common clock input line. You use the TC output to inhibit each successive stage from counting until the previous stage is at its terminal count. Figure 12.92 shows various asynchronous (ripple-like) and synchronous multistage counters built from 74191 ICs.

Presettable 4-Bit (MOD-16) Synchronous Up/Down Counter

The 74160 and 74163 resemble the 74190 and 74191 but require no external gates when used in multistage counter configurations. Instead, you simply cascade counter ICs together, as shown in Fig. 12.93.

For both devices, a count can be preset by applying the desired count to the D₀ to D₃ inputs and then applying a low to the parallel enable input ; the input number is loaded into the counter on the next low-to-high clock transition. The master reset is used to force all Q output low, regardless of the other input signals. The two clock enable inputs (CEP and CET) must be high for counting to begin. The terminal count output (TC) is forced high when the maximum count is reached, but will be forced low if CET goes low. This is an important feature that makes the multistage configuration synchronous, while avoiding the need for external gating. The truth tables along with the example load, count-up, and count-down timing sequences in Figs. 12.93 and 12.94 should help you better understand how these two devices work.

60-Hz, 10-Hz, and 1-Hz Clock-Pulse Generator

7491A 8-Bit Serial-In/Serial-Out Shift Register IC

The 7491A is an 8-bit serial-in/serial-out shift register that consists of eight internally linked SR flip-flops. This device has positive edge-triggered inputs and a pair of data inputs (A and B) that are internally ANDed together, as shown in the logic diagram in Fig. 12.103. This type of data input means that for a binary 1 to be shifted into the register, both data inputs must be high. For a binary 0 to be shifted into the register, either input can be low. Data is shifted to the right at each positive clock edge.

74164 8-Bit Serial-In/Parallel-Out Shift Register IC

The 74164 is an 8-bit serial-in/parallel-out shift register. It contains eight internally linked flip-flops and has two serial inputs, D_sa and D_sb, which are ANDed together. Like the 7491A, the unused serial input acts as an enable/disable control for the other serial input. For example, if you use D_sa as the serial input, you must keep D_sb high to allow data to enter the register, or you can keep it low to prevent data from entering the register.

Data bits are shifted one position to the right at each positive clock edge. The first data bit entered will end up at the Q₇ parallel output after the eighth clock pulse. The master reset resets all internal flip-flops and forces the Q outputs low when it is pulsed low.

In the sample circuit shown in Fig. 12.104, a serial binary number 10011010 (15410) is converted into its parallel counterpart. Note the AND gate and strobe input used in this circuit. The strobe input acts as a clock enable input; when it is set high, the clock is enabled. The timing diagram paints the rest of the picture.

75165 8-Bit Serial-In or Parallel-In/Serial-Out Shift Register IC

The 75165 is a unique 8-bit device that can act as either a serial-to-serial shift register or as a parallel-to-serial shift register. When used as a parallel-to-serial shift register, parallel data is applied to the D₀–D₇ inputs and then loaded into the register when the parallel load input is pulsed low. To begin shifting the loaded data out of the serial output Q₇ (or if you want inverted bits), the clock enable input must be set low to allow the clock signal to reach the clock inputs of the internal D-type flip-flops. When used as a serial-to-serial shift register, serial data is applied to the serial data input DS. A sample shift, load, and inhibit timing sequence is shown in Fig. 12.105.

74194 Universal Shift Register IC

Figure 12.106 shows the 74194 4-bit bidirectional universal shift register. This device can accept either serial or parallel inputs, provide serial or parallel outputs, and shift left or right based on input signals applied to select controls S₀ and S₁. Serial data can be entered into either the serial shift-right input (D_SR) or the serial shift-left input (D_SL). Select controls S₀ and S₁ are used to initiate a hold (S₀ = low, S₁ = low), shift left (S₀ = low, S₁ = high), shift-right (S₀ = high, S₁ = low), or to parallel load (S₀ = high, S₁ = high) mode. A clock pulse must then be applied to shift or parallel load the data.

In parallel load mode (S₀ and S₁ are high), parallel input data is entered via the D₀ through D₃ inputs and transferred to the Q₀ to Q₃ outputs following the next low-to-high clock transition. The 74194 also has an asynchronous master reset input that forces all Q outputs low when pulsed low. To make a shift-right recirculating register, the Q₃ output is wired back to the D_SR input, while making S₀ = high and S₁ = low. To make a shift-left recirculating register, the Q₀ output is connected back to the D_SL input, while making S₀ = low and S₁ = high. The timing diagram in Fig. 12.106 shows a typical parallel load and shifting sequence.

74299 8-Bit Universal Shift/Storage Register with Three-State Interface

A number of shift registers have three-state outputs—outputs that can assume a high, low, or high impedance state (open-circuit or float state). These devices are commonly used as storage registers in three-state bus interface applications.

An example 8-bit universal shift/storage register with three-state outputs is the 74299, shown in Fig. 12.107. This device has four synchronous operating modes that are selected via two select inputs, S₀ and S₁. Like the 74194 universal shift register, the 74299's select modes include shifting right, shifting left, holding, and parallel loading (see the function table in Fig. 12.107). The mode-select inputs, serial data inputs (D_S0 and D_S7), and parallel-data inputs (I/O₀ through I/O₇) are positive edge triggered. The master reset input is an asynchronous active-low input that clears the register when pulsed low.

The three-state bidirectional I/O port has three modes of operation:

• The read-register mode allows data within the register to be available at the I/O outputs. This mode is selected by making both output-enable inputs ( and ) low and making one or both select inputs low.
• The load-register mode sets up the register for a parallel load during the next low-to-high clock transition. This mode is selected by setting both select inputs high.
• The disable-I/O mode acts to disable the outputs (set to a high impedance state) when a high is applied to one or both of the output-enable inputs. This effectively isolates the register from the bus to which it is attached.

16-Bit Serial-to-Parallel Converter

A simple way to create a 16-bit serial-to-parallel converter is to join two 74164 8-bit serial-in/parallel-out shift registers, as shown in Fig. 12.108. To join the two ICs, simply wire the Q₇ output from the first register to one of the serial inputs of the second register. (Recall that the serial input that is not used for serial input data acts as an active-high enable control for the other serial input.)

In terms of operation, when data is shifted out of Q₇ of the first register (or data output D₇), it enters the serial input of the second (the example uses D_Sa as the serial input) and will be presented to the Q₀ output of the second register (or data output D₈). For an input data bit to reach the Q₇ output of the second register (or data output D₁₅), 16 clock pulses must be applied.

8-Bit Serial-to-Parallel Converter with Simultaneous Data Transfer

Figure 12.109 shows a circuit that acts as a serial-to-parallel converter that outputs the converted 8-bit word only when all 8 bits have been entered into the register. Here, a 74164 8-bit serial-in/parallel-out shift register is used, along with a 74HCT273 octal D-type flip-flop and a divide-by-8 counter. At each positive clock edge, the serial data is loaded into the 74164. After eight clock pulses, the first serial bit entered is shifted down to the 74164's Q₇ output, while the last serial bit entered resides at the 74164's Q₀ output. At the negative edge of the eighth clock pulse, the negative-edge triggered divide-by-8 circuit's output goes high. During this high transition, the data present on the inputs of the 74HCT273 (which hold the same data present at the 74164's Q outputs) is passed to the 74HCT273's outputs at the same time. (Think of the 74HCT273 as a temporary storage register that dumps its contents after every eighth clock pulse.)

8-Bit Parallel-to-Serial Interface

Figure 12.110 shows a 74165 8-bit parallel-to-serial shift register used to accept a parallel ASCII word and convert it into a serial ASCII word that can be sent to a serial device. Recall that ASCII codes are only 7 bits long (for example, the binary code for & is 010 0110). How do you account for the missing bit? As it turns out, most 8-bit devices communicating via serial ASCII will use an additional eighth bit for a special purpose, perhaps to act as a parity bit or as a special function bit to enact a special set of characters. Often, the extra bit is simply set low and ignored by the serial device receiving it.

To keep things simple, let's set the extra bit low and assume that is how the serial device likes things done. This means that you will set the D₀ input of the 74165 low. The MSB of the ASCII code will be applied to the D₁ input, while the LSB of the ASCII code will be applied to the D₇ input. Now, with the parallel ASCII word applied to the inputs of the register, when you pulse the parallel load line ( ) low, the ASCII word, along with the "ignored bit," is loaded into the register. Next, you must enable the clock to allow the loaded data to be shifted out serially, by setting the clock enable input ( ) low for the duration it takes for the clock pulses to shift out the parallel word. After the eighth clock pulse (0 to 7), the serial device will have received all 8 serial data bits. Practically speaking, a microprocessor or microcontroller is necessary to provide the and lines with the necessary control signals to ensure that the register and serial device communicate properly.

Recirculating Memory Registers

A recirculating memory register is a shift register that is preloaded with a binary word that is serially recirculated through the register via a feedback connection from the output to the input. Recirculating registers can be used for a number of applications, from supplying a specific repetitive waveform used to drive IC inputs to driving output drivers used to control stepper motors.

In the leftmost circuit in Fig. 12.111, a parallel 4-bit binary word is applied to the D₀ to D₃ inputs of a 74194 universal shift register. When the S₁ select input is brought high (switch opened), the 4-bit word is loaded into the register. When the S₁ input is then brought low (switch closed), the 4-bit word is shifted in a serial fashion through the register, out Q₃, and back to Q₀ via the D_SR input (serial shift-right input) as positive clock edges arrive. Here, the shift register is loaded with 0111. As you begin shifting the bits through the register, a single low output will propagate down through high outputs, which in turn causes the LED attached to the corresponding low output to turn on. In other words, you have made a simple Christmas tree flasher.

The rightmost circuit in Fig. 12.111 is basically the same thing as the leftmost circuit. However, now the circuit is used to drive a stepper motor. Typically, a stepper motor has four stator coils that must be energized in sequence to make the motor turn at a given angle. For example, to make a simple stepper motor turn clockwise, you must energize its stator coils 1, 2, 3, and 4 in the following sequence: 1000, 0100, 0010, 0001, 1000, and so on. To make the motor go counterclockwise, apply the following sequence: 1000, 0001, 0010, 0100, 1000, and so on. You can generate these simple firing sequences with the 74194 by parallel loading the D₀ to D₃ inputs with the binary word 1000. To output the clockwise firing sequence, simply shift bits to the right by setting S₀ = high and S₁ = low. As clock pulses arrive, the 1000 present at the outputs will then become 0100, then 0010, 0001, 1000, and so on.

The speed of rotation of the motor is determined by the clock frequency. To output the counterclockwise firing sequence, simply shift bits to the left by setting S₀ = low and S₁ = high. To drive steppers, it is typically necessary to use a buffer/driver interface like the 7407 shown in Fig. 12.111, as well a number of output transistors, not shown. Also, different types of stepper motors may require different firing sequences than the one shown here. Stepper motors and the various circuits used to drive them are discussed in detail in Chap. 15.

ADC and DAC Basics

Figure 12.116 shows the basic idea behind analog-to-digital and digital-to-analog conversion. In the analog-to-digital figure, the ADC receives an analog input signal along with a series of digital sampling pulses. Each time a sampling pulse is received, the ADC measures the analog input voltage and outputs a 4-bit binary number that is proportional to the analog voltage measured during the specific sample. With 4 bits, we get 16 binary codes (0000 to 1111) that correspond to 16 possible analog levels (for example, 0 to 15 V).

In the digital-to-analog conversion figure, the DAC receives a series of 4-bit binary numbers. The rate at which new binary numbers are fed into the DAC is determined by the logic that generates them. With each new binary number, a new analog voltage is generated. As with the ADC example, we have a total of 16 binary numbers to work with and 16 possible output voltages.

As you can see from the graphs, both these 4-bit converters lack the resolution needed to make the analog signal appear continuous (without steps). To make things appear more continuous, a converter with higher resolution is used. This means that instead of using 4-bit binary numbers, we use larger-bit numbers, such as 6-bit, 8-bit, 10-bit, 12-bit, 16-bit, or even 18-bit or higher numbers. If our converter has a resolution of 8 bits, we have 2⁸ = 256 binary numbers to work with, along with 256 analog steps. Now, if this 8-bit converter is set up to generate 0 V at binary 00000000 and 15 V at binary 11111111 (full scale), then each analog step is only 0.058 V high (¹⁄₂₅₆ × 15 V). With an 18-bit converter, the steps get incredibly tiny because we have 2¹⁸ = 262,144 binary numbers and steps. With 0 V corresponding to binary 000000000000000000 and 15 V corresponding to 111111111111111111, the 18-bit converter yields steps that are only 0.000058 V high! As you can see in the 18-bit case, the conversion process between digital and analog appears practically continuous.

Simple Binary-Weighted DAC

Figure 12.117 shows a simple 4-bit DAC that is constructed from a digitally controlled switch (74HC4066), a set of binary-weighted resistors, and an operational amplifier. The basic idea is to create an inverting amplifier circuit whose gain is controlled by changing the input resistance R_in. The 74HC4066 and the resistors together act as a digitally controlled R_in that can take on one of 16 possible values. You can think of the 74HC4066 and resistor combination as a digitally controlled current source. Each new binary code applied to the inputs of the 74HC4066 generates a new discrete current level that is summed by R_F to provide a new discrete output voltage level.

We choose scaled resistor values of R, R/2, R/4, and R/8 to give R_in discrete values that are equally spaced. To find all possible values of Rin, we use the formula provided in Fig. 12.117. This formula looks like the old resistors-in-parallel formula, but we must exclude those resistors that are not selected by the digital input code—that's what the coefficients A through D are for (a coefficient is either 1 or 0, depending on the digital input).

To find the analog output voltage, we simply use V_out = -V_ref(R_F/R_in)—the expression used for the inverting amplifier (see Chap. 8). Figure 12.117 shows what we get when we set V_ref = -5 V, R = 100 kΩ, and R_F = 20 kΩ, and take all possible input codes.

The binary-weighted DAC shown in Fig. 12.117 is limited in resolution (4-bit, 16 analog levels). To double the resolution (make an 8-bit DAC), you might consider adding another 74HC4066 and R/16, R/32, R/64, and R/128 resistors. In theory, this works; in reality, it doesn't. The problem with this approach is that when we reach the R/128 resistor, we must find a 0.78125-kΩ resistor, assuming R = 100 kΩ. Assuming we can find or construct an equivalent resistor network for R/128, we're still in trouble because the tolerances of these resistors will cause problems. This scaled-resistor approach becomes impractical when we deal with resolutions of more than a few bits. To increase the resolution, we scrap the scaled-resistor network and replace it with an R/2R ladder network. The manufacturers of DAC ICs do this as well.

R/2R Ladder DAC

An R/2R DAC uses an R/2R resistor ladder network instead of a scaled-resistor network, as was the case in the previous DAC. The benefit of using the R/2R ladder is that we need only two resistor values: R and 2R. Figure 12.118 shows a simple 4-bit R/2R DAC. For now, assume that the switches are digitally controlled (in real DACs, they are replaced with transistors).

The trick to understanding how the R/2R ladder works is realizing that the current drawn through any one switch is always the same, no matter if it is thrown up or down. If a switch is thrown down, current will flow through the switch into ground (0 V). If a switch is thrown up, current will flow toward virtual ground—located at the op amp's inverting input (recall that if the noninverting input of an op amp is set to 0 V, the op amp will make the inverting input 0 V, via negative feedback). Once you realize that the current through any given switch is always constant, you can figure that the total current (I) supplied by V_ref will be constant as well. Once you have that, you figure out what fractions of the total current pass through each of the branches within the R/2R network using simple circuit analysis. Figure 12.118 shows that ½I passes through S₃ (MSB switch), ¼I through S₂, ⅛I through S₁, and ¹⁄₁₆I through S₀ (LSB switch). If you're interested in how that was figured out, the circuit reduction shown in Fig. 12.119 should help.

Now that we have a means of consistently generating fractions of ¹⁄₂I, ¹⁄₄I, ¹⁄₈I, and ¹⁄₁₆I, we can choose, via the digital input switches, which fractions are summed together by the amplifier. For example, if switches S₃, S₂, S₁, and S₀ are thrown to 0101 (5), ¹⁄₄ I + ¹⁄₁₆ I combine to form I_sum. But what is I? Using Ohm's law, it's just I = V_ref / R = +5 V / 10 kΩ = 500 µA. This means that I_sum = ¹⁄₄(500 µA) + ¹⁄₁₆(500 µA) = 156.25 µA. The final output voltage is determined by V_out = -I_sumR_F = - (156.25 µA)(20 kΩ) = -3.125 V. The formulas and the table in Fig. 12.118 show the other possible binary/analog combinations.

To create an R/2R DAC with higher resolution, we simply add more runs and switches to the ladder.

Integrated DACs

Often, making DACs from scratch isn't worth the effort. The cost as well as the likelihood for conversion errors is great. The best thing to do is to simply buy a DAC IC. You can buy these devices from a number of different manufacturers (such as National Semiconductor, Analog Devices, and Texas Instruments). The typical resolutions for these ICs are 6, 8, 10, 12, 16, and 18 bits. DAC ICs also may come with a serial digital input, as opposed to the parallel input scheme shown in Figs 12.117 and 12.118. Before a serial-input DAC can make a conversion, the entire digital word must be clocked into an internal shift register.

Most often, DAC ICs come with an external reference input that is used to set the analog output range. There are some DACs that have fixed references, but these are becoming rare.

Often, you'll see a manufacturer list one of its DACs as being a multiplying DAC. A multiplying DAC can produce an output signal that is proportional to the product of a varying input reference level (voltage or current) times a digital code. As it turns out, most DACs, even those that are specifically designated as multiplying DAC on the data sheets, can be used for multiplying purposes simply by using the reference input as the analog input. However, many such ICs do not provide the same quality multiplying characteristics, such as a wide analog input range and fast conversion times, as those that are called multiplying DACs.

Multiplying is most commonly applied in systems that use ratiometeric transducers (for example, position potentiometers, strain gauges, and pressure transducers). These transducers require an external analog voltage to act as a reference level on which to base analog output responses. If this reference level is altered, say, by an unwanted supply surge, the transducer's output will change in response, and this results in conversion errors at the DAC end. However, if we use a multiplying DAC, we eliminate these errors by feeding the transducer's reference voltage to the DAC's analog input. If any supply voltage/current errors occur, the DAC will alter its output in proportion to the analog error.

DACs are capable of producing unipolar (single-polarity output) or bipolar (positive and negative) output signals. In most cases, when a DAC is used in unipolar mode, the digital code is expressed in standard binary. When used in bipolar mode, the most common code is either offset binary or 2's complement. Offset binary and 2's complement codes make it possible to express both positive and negative values. Figure 12.120 shows all three codes and their corresponding analog output levels (referenced from an external voltage source).

Common Digital Codes Used by DACs

Note that in the figure, FS stands for full scale, which is the maximum analog level that can be reached when applying the highest binary code. It is important to realize that at full scale, the analog output for an n-bit converter is actually (2ⁿ - 1) / 2ⁿ × V_ref, not 2ⁿ/2ⁿ × V_ref. For example, for an 8-bit converter, the number of binary numbers is 2⁸ = 256, while the maximum analog output level is 255/256 V_ref, not 256/256 V_ref, since the highest binary number is 255 (1111 1111). The "missing count" is used up by the LSB-1 condition (0 state).

Example DAC ICs

DAC0808 8-BIT DAC

The DAC0808 (National Semiconductor) is a popular 8-bit DAC that requires an input reference current and supplies 1 of 256 analog output current levels. Figure 12.121 shows a block diagram of the DAC0808, along with its IC pin configuration and a sample application circuit.

In the application circuit, the analog output range is set by applying a reference current (I_ref) to pin 14 (+V_ref). In this example, I_ref is set to 2 mA via an external +10 V/5 kΩ resistor combination. Note that another 5-kΩ resistor is required between pin 15 (-V_ref) and ground.

To determine the DAC's analog output current (I_out) for all possible binary inputs, we use the following formula:

At full scale (all A's high or binary 255), I_out = I_ref (255/256) = (2 mA)(0.996) = 1.99 mA. Considering that the DAC has 256 analog output levels, we can figure that each corresponding level is spaced 1.99 mA/256 = 0.0078 mA apart.

To convert the analog output currents into analog output voltages, we attach the op amp. Using the op amp rules from Chap. 8, we find that the output voltage is V_out = I_out × R_f. At full scale, V_out = (1.99 mA)(5 kΩ) = 9.95 V. Each analog output level is spaced 9.95 V/256 = 0.0389 V apart.

The DAC0808 can be configured as a multiplying DAC by applying the analog input signal to the reference input. In this case, however, the analog input current should be limited to a range from 16 µA to 4 mA to retain reasonable accuracy. See the National Semiconductor's data sheets for more details.

DAC8043A SERIAL 12-BIT INPUT MULTIPLYING DAC

The DAC8083A (Analog Devices) is a high-precision 12-bit CMOS multiplying DAC that comes with a serial digital input. Figure 12.122 shows a block diagram, pin configuration, and write cycle timing diagram for this device.

Before the DAC8043 can make a conversion, serial data must be clocked into the input register by supplying an external clock signal (each positive edge of the clock load one bit). Once loaded, the input register's contents are dumped off to the DAC register by applying a low pulse to the line. Data in the DAC register is then converted to an output current through the I_out terminal.

In most applications, this current is then transformed into a voltage by an op amp stage, as is the case within the two circuits shown in Fig. 12.123. In the unipolar (two-quadrant) circuit, a standard binary code is used to select from 4096 possible analog output levels. In the bipolar (four-quadrant) circuit, an offset binary code is used again to select from 4096 analog output levels, but now the range is broken up to accommodate both positive and negative polarities.

If you're interested in learning more about the DAC8043, go to Analog Device's website and check out the data sheet.

Another very similar device worth considering is the MAX522.

Successive Approximation

Successive approximation analog-to-digital conversion is the most common approach used in integrated ADCs. In this conversion technique, each bit of the binary output is found, one bit at a time—MSB first. This technique yields fairly fast conversion times (from around 10 to 300 µs) with a limited amount of circuitry. Figure 12.124 shows a simple 8-bit successive approximation ADC, along with an example analog-to-digital conversion sequence.

To begin a conversion, the (start conversion) input is pulsed low. This causes the successive approximation register (SAR) to first apply a high on the MSB (D₇) line of the DAC. With only D₇ high, the DAC's output is driven to one-half its full-scale level, which in this case is +5 V because the full-scale output is +10 V. The +5-V output level from the DAC is then compared with the analog input level, via the comparator. If the analog input level is greater than +5 V, the SAR keeps the D₇ line high; otherwise, the SAR returns the D₇ line low. At the next clock pulse, the next bit (D₆) is tried. Again, if the analog input level is larger than the DAC's output level, D₆ is left high; otherwise, it is returned low.

During the next six clock pulses, the rest of the bits are tried. After the last bit (LSB) is tried, the CC (conversion complete) output of the SAR goes low, indicating that a valid 8-bit conversion is complete, and the binary data is ready to be clocked into the octal flip-flop, where it can be presented to the Q₀–Q₇ outputs.

The timing diagram shows a 3.8652-V analog level being converted into an approximate digital equivalent. Note that after the first approximation (the D₇ try), the percentage error between the actual analog level and corresponding digital equivalent is 29.360 percent. However, after the final approximation, the percentage error is reduced to only 0.051 percent.

Until now, we've assumed that the analog input to our ADC was constant during the conversion. But what happens when the analog input changes during conversion time? Errors result. The more rapidly the analog input changes during the conversion time, the more pronounced the errors will become. To prevent such errors, a sample-and-hold circuit is often attached to the analog input. With an external control signal, this circuit can be made to sample the analog input voltage and hold the sample while the ADC makes the conversion.

With the exception of very high-speed ADCs, separate ADC ICs are now largely redundant and have been replaced with microcontrollers containing 12-bit or higher ADC channels.

Parallel-Encoded Analog-to-Digital Conversion (Flash Conversion)

Parallel-encoded analog-to-digital conversion, or flash conversion, is perhaps the easiest conversion process to understand. To illustrate the basics behind parallel encoding (also referred to as simultaneous multiple comparator or flash converting), let's take a look at the simple 3-bit converter in Fig. 12.125.

The set of comparators is the key feature to note in this circuit. Each comparator is supplied with a different reference voltage from the 1 kΩ voltage divider network. Since we've set up a +5V reference voltage, the voltage drop across each resistor within the voltage divider network is 0.625 V. From this, you can determine the specific reference voltages given to each comparator (see Fig. 12.125).

To convert an analog signal into a digital number, the analog signal is applied to all the comparators at the same time, via the common line attached to the inverting inputs of all the comparators. If the analog voltage is between, say, 2.500 and 3.125 V, only those comparators with reference voltage below 2.500 V will output a high. To create a 3-bit binary output, the eight comparator outputs are fed into an octal-to-binary priority encoder. A D latch also can be incorporated into the circuit to provide enable control of the binary output. The truth table should fill in the rest.

Direct Drive of Numeric LED Displays

Seven-segment LED displays come in two varieties: common anode and common cathode. Figure 12.128 shows single digital eight-segment (seven digit segments + decimal point) displays of both varieties.

When driving a multidigit display, say, one with eight digits, the previous technique becomes awkward. It requires eight discrete decoder/driver ICs. One way to avoid this problem is to use a special direct-drive LED display driver IC.

For example, National Semiconductor's MM5450, shown in Fig. 12.133, is designed to drive 4- or 5-digit alphanumeric common anode LED displays. It comes with 34 TTL-compatible outputs that are used to drive desired LED segments within a display. Each of these outputs can sink up to 15 mA. In order to specify which output lines are driven high or low, serial input data are clocked into the driver's serial input. The serial data chain that is entered is 36 bits long. The first bit is a start bit (set to 1), and the remaining 35 bits are data bits. Each data bit corresponds to a given output data line that is used to drive a given LED segment within the display. At the thirty-sixth positive clock signal, a LOAD signal is generated that loads the 35 data bits into the latches (see the block diagram in Fig. 12.133). At the low state of the clock, a signal is generated that clears the shift register for the next set of data. You can learn more about the MM5450 at http://www.micrel.com/_PDF/mm5450.pdf.

Multiplexed LED Displays

Another technique used to drive multidigit LED displays involves multiplexing. Multiplexing can drastically reduce the number of connections needed between display and control logic. In a multiplexed display, digits share common segment lines. Also, only one digit within the display is lighted at a time. To make it appear that a complete readout is displayed, all the digits must be flashed very rapidly in sequence, over and over again. The simple example in Fig. 12.129 shows multiplexing in action.To reduce the component count further, you can do away with the 74HC4511 and just use 7 digital outputs from the microcontroller.

Simple Alphanumeric Display

"Smart" Alphanumeric Display

Basic Explanation of How an LCD Works

An LCD consists of a number of layers that include a polarizer, a set of transparent electrodes, a liquid-crystal element, a transparent back electrode, a second polarizer, and a mirror (see the leftmost illustration in Fig. 12.132).

The transparent top electrodes are used to generate the individual segments of a digit, character, and so on, while the transparent back electrode forms a common plane, often referred to as the back plane (BP). The top electrode segments and the back electrode are wired to external contacts. With no potential difference between a given top electrode and the back electrode, the region where the top electrode is located appears silver in color against a silver background. However, when a potential is applied between a given top electrode and back electrode, the region where the top electrode is located appears dark against a silver background.

The circuit in Fig. 12.132 shows a basic way to drive a seven-segment LCD. It uses a 74HC4511 BCD decoder and XOR gates to generate the prior drive signals for the LCD. A very important thing to note in this circuit is the clock. As it turns out, an LCD actually requires ac drive signals (for example, squarewaves) instead of dc drive signals. If dc were used, the primary component of the display—namely, the liquid crystal—would undergo electrochemical degradation (more on the liquid crystal in a moment). The optimal frequency of the applied ac drive signal is typically from around 25 Hz to a couple hundred hertz. Now that we understand that, it is easy to see why we need the XOR gates.

As the clock delivers squarewaves to the back electrode (back plane, or BP), the XOR gates act as enable gates that pass and invert a signal and apply it to a given top electrode segment. For example, if a BCD code of 1001 (5) is applied to the decoder, the decoder's outputs a, c, d, f, and g go high, while outputs b and e go low. When a positive clock pulse arrives, XOR gates attached to the outputs that are high invert the high levels. XOR gates attached to outputs that are low pass on the low levels. During the same pulse duration, the back plane is set high. Potentials now are present between a, c, d, f, and g segments and the back plane, and therefore these segments appear dark. Segments b and e, along with the background, appear silverish because no potential exists between them and the back plane. Now, when the clock pulse goes low, the display remains the same (provided the BCD input hasn't changed), since all that has occurred is a reverse in polarity. This has no effect on the optical properties of the display.

Detailed Explanation of How an LCD Works (the Physics)

Figure 12.133 shows how an LCD generates a clear (silverish) segment. When control signals sent to the transparent top and back electrodes are in phase, no potential exists between the two electrodes. With no potential present, the cigar-shaped organic liquid crystals (nematic crystals) arrange themselves in spiral state, as shown in the figure.

The upper crystal aligns itself horizontal to the page, while the lowest crystal aligns itself perpendicular to the page. The upper crystal and the lower crystal are held in place by tiny grooves that are etched into the inner surfaces of the glass surfaces of the cell. Crystals in between the upper crystal and the lower crystal progressively spiral 90° due to electrostatic forces that exist between neighboring crystals. When polarized light passes through a region of the display that contains these spirals, the polarization angle of the light is rotated 90°.

Now, looking at the display as a whole, when incident unpolarized light passes through polarizer 1 (as shown in the figure), the light becomes polarized in the same direction of the plane of polarization of the first polarizer. The polarized light then passes through the transparent top electrode and enters the liquid-crystal cell. As it passes through the cell, its polarization angle is rotated 90°. The polarized light that exits the cell then passes through the transparent back electrode and the second polarizer without problems. (If we were to remove the liquid-crystal cell, all polarized light that passed through the first polarizer would be absorbed, since we would have crossed polarizers.) The light that passes through the second polarizer then reflects off the mirror, passes through the second polarizer, on through the liquid-crystal cell (getting rotated 90°), through the first polarizer, and finally reaches the observer's eye. This reflected light appears silver in color. Note that the background of LCDs constantly appears silver because no potential exists across the liquid-crystal cell in the background region.

Figure 12.134 shows how an LCD generates a dark segment. When control signals sent to the top and back electrodes are out of phase, a potential difference exists between the two electrodes. This causes the crystals to align themselves in a parallel manner, as shown in the figure. When the polarized light from the first polarizer passes through the cell region containing these parallel crystals, nothing happens—the polarization angle stays the same. However, when the light comes in contact with the second polarizer, it is absorbed because the angle of polarization of the light and the plane of polarization of the second polarizer are perpendicular to each other. Since light reaches the mirror, no light is reflected back to the observer's eye, and hence the segment appears dark.

The LCD shown in Fig. 12.133 represents what is referred to as a standard twisted nematic display. Another common LCD is the supertwist nematic display. Unlike the standard twisted display, this display's nematic crystals rotate 270° from top to bottom. The extra 180° twist improves the contrast and viewing angle.

Driving LCDs

CD4543B CMOS BCD-TO-SEVEN-SEGMENT LATCH/DECODER/DRIVER

The CD4543B (Texas Instruments), shown in Fig. 12.135, is a BCD-to-seven-segment latch/decoder/driver that is designed for LCDs, as well as for LED displays. When used to drive LCDs, a squarewave must be applied simultaneously to the CD4543B's Phase (Ph) input and to the LCD's back plane. When used to drive LED displays, a high is required at the Phase input for common cathode displays, while a low is required for common anode displays. To blank the display (set outputs a–g low), the BL input is set high. The CD4543B also comes with a Latch Disable input (LD), which can be used to latch onto input data, preventing new input data from altering the display.

MM5453 LCD DRIVER

The MM5453 (National Semiconductor) is a 40-pin IC that can drive up to 33 segments of an LCD, which can be used to drive 4½-digit seven-segment displays. It houses an internal oscillator section (requiring an external RC circuit) that generates the necessary squarewaves used to drive the LCD. To activate given segments within the display, a serial code is applied to the data input. The code first starts out with a start bit (high) followed by data bits that specify which outputs should be driven high or low. Figure 12.136 shows an example display circuit, along with corresponding data format required to drive a 4½-digit display.

VI-322-DP LCD AND ICL7106 3½-DIGIT LCD, ADC DRIVER

There are a number of specialized LCDs that can be found in the electronics catalogs. An example is Varitronix's VI-322-DP 3½-digit (plus ∼, +, BAT, Δ) LCD, shown in Fig. 12.136. This display is configured in a static drive arrangement (each segment has a separate lead) and is found in many test instruments. To drive this display, you first check to see what kind of driver the manufacturer suggests. In this case, the manufacturer suggests using Intersil's ICL7106. This IC is a 3½-digit LCD/LED display driver as well as an ADC. This dual-purpose feature makes it easy to interface transducers directly to the same IC that is driving the display. To learn how to use the ICL7106, check out Intersil's data sheet at http://www.intersil.com.

Multiplexed LCDs

We have just seen examples of static-drive-type LCDs, where each segment (to electrode) had its own lead, and a single common plane was used as the back electrode. Another type of LCD is designed with multiplexing in mind and is referred to as dynamic drive or multiplexed display.

As with the multiplexed LED display, multiplexed LCDs can greatly reduce the number of external connections required between the display and driver. However, they require increased complexity in drive circuitry (or software) to drive. In a multiplexed LCD, appropriate segments are connected together to form groups that are sequentially addressed by means of multiple back-plane electrodes.

"Intelligent" Dot-Matrix LCD Modules

Dot-matrix LCDs are used to display alphanumeric characters and other symbols. These displays are used in cell phones, calculators, vending machines, and many other devices that provide the user with simple textual information. Dot-matrix LCDs are also used in laptop computer screens; however, these displays incorporate special filters, multicolor back lighting, and so on. For practical purposes, we'll concentrate on the simple alphanumeric LCDs.

An alphanumeric LCD screen is usually divided into a number of 5 × 8 pixel blocks, with vertical and horizontal spaces separating each block. Figure 12.138 shows a display with 20 columns and 4 rows of 5 × 8 pixel blocks. Other standard configurations come with 8, 16, 20, 24, 32, or 40 columns and 1, 2, or 4 rows. To generate a character within a given block requires that each pixel within the block be turned on or off. As you can imagine, to control so many different pixels (electrode segments) requires a great deal of sophistication. For this reason, an intelligent driver IC is required.

Almost all alphanumeric LCD modules are controlled by Hitachi's HD44780 (or equivalent) driver IC. This driver contains the following:

• A permanent memory (CG ROM) that stores 192 alphanumeric characters
• A random access memory (DD RAM) used to store the display's contents
• A second random access memory (CG RAM) used to hold custom symbols
• Input lines for data and instruction control signals
• Multiplexed outputs for driving LCD pixels
• Additional outputs for communicating with expansion chips to drive more LCD pixels

This driver is built right into the LCD module. (You could attempt to construct your own module by interfacing the driver with an LCD, but it would not be worth the effort—the numerous tiny connections would drive you nuts.) From now on, all modules described in this section are assumed to be HD44780-driven.

BASIC OVERVIEW OF THE PINS

The standard LCD module comes with a 14-pin interface: eight data lines (D₀–D₇), three control lines (RS, W/R, and E), and three power lines (V_DD, V_SS, and V_EE).

V_DD (pin 2) and V_SS (pin 1) are the module's positive and negative power supply leads. Usually, V_DD is set to +5 V, while V_SS is grounded. V_EE (pin 3) is the display's contrast control. By changing the voltage applied to this lead, the contrast of the display increases or decreases. A potentiometer placed between supply voltages, with its wiper connected to V_EE, allows for manual adjustment.

D₀–D₇ (pins 7–14) are the data bus lines. Data can be transferred to and from the display either as a single 8-bit byte or as two 4-bit nibbles. In the latter case, only the upper four data lines (D₄–D₇) are used.

RS (pin 4) is the Register Select line. When this line is low, data bytes transferred to the display module are interpreted as commands, and data bytes read from the display module indicate its status. When the RS line is set high, character data can be transferred to and from the display module.

R/W (pin 5) is the Read/Write control line. To write commands or character data to the module, R/W is set low. To read character data or status information from the module, R/W is set high.

E (pin 6) is the Enable control input, which is used to initiate the actual transfer of command or character data to and from the module. When writing to the display, data on the D₀–D₇ lines is transferred to the display when the enable input receives a high-to-low transition. When reading from the display, data become available to the D₀–D₇ lines shortly after a low-to-high transition occurs at the enable input and will remain available until the signal goes low again.

Figure 12.139 shows the instruction set and standard set of characters for an LCD module. Next, we'll go through some examples illustrating how to use the instructions and how to write characters to the display.

TEST CIRCUIT USED TO DEMONSTRATE HOW TO CONTROL THE LCD MODULE

Figure 12.140 shows a simple test circuit that is quite useful for learning how to send commands and character data to the LCD module. (In reality, the LCD module is connected to a microprocessor or microcontroller, as shown to the left in the figure.) In this circuit, switches connected to data inputs use pullup resistors in order to supply a high (1) when the switch is open or supply a low (0) when the switch is closed.

The enable input receives its high and low levels from a debounced toggle switch. Debouncing the enable switch prevents the likelihood of multiple enable signals being generated. Multiple enable signals tend to create unwanted effects, such as generating the same character over and over again across the display. The 5-kΩ pot is used for contrast. Note that in this circuit, we've grounded the R/W line, which means we'll only deal with writing to the display.

WHEN POWER IS FIRST APPLIED

When power is first applied to the display, the display module resets itself to its initial settings. Initial settings are indicated in the LCD instruction set with an asterisk. As indicated, the display is actually turned off during the initial setting condition. If we attempt to write character data to the display now, nothing will show up. In order to show something, we must issue a command to the module telling it to turn on its display.

According to the instruction set, the Display & Cursor On/Off instruction can be used to turn on the display. At the same time, this instruction also selects the cursor style. For example, if we apply the command code 0000 1111 to D₇–D₀, making sure to keep RS low so the module will interpret data as a command, a blinking cursor with an underline should appear at the top leftmost position on the display. But before this command can take effect, it must be sent to the module by momentarily setting the Enable (E) line low.

Another important instruction that should be implemented after power-up is the Function Set command. When a two-line display is used, this command tells the module to turn on the second line. It also tells the module what kind of data transfer is going to be used (8-bit or 4-bit), and whether a 5 × 10 or 5 × 7 pixel format will be used (5 × 10 is found in some one-line displays). Assuming that the display used in our example circuit is a two-line display, we can send the command 0011 1000 telling the display to turn on both lines, use an 8-bit transfer, and provide a 5 × 7 pixel character format. Again, to send this command, we set RS low, then supply the command data to D₇–D₀, and finally pulse E low.

Now that the module knows what format to use, we can try writing a character to the display. To do this, we set the module to character mode by setting RS high. Next, we apply one of the 8-bit codes listed in the standard LCD character set table to the data inputs D₇–D₀. For example, if we want to display the letter Q, we apply 01010001 (hex 51 or 51_H). To send the character data to the LCD module, we pulse E low. A Q should then appear on the display. To clear the screen, we use the Clear Display command 0000 0001, remembering to keep RS low and then pulsing E low.

ADDRESSING

After power-up, the module's cursor is positioned at the far-left corner of the first line of the display. This display location is assigned a hexadecimal address of 00_H. As new characters are entered, the cursor automatically moves to the right to a new address of 01_H, then 02_H, and so on. Although this automatic incrementing feature makes life easy when entering characters, there are times when it is necessary to set the cursor position to a location other than the first address location.

To set the cursor to another address location, a new starting address must be entered as a command. There are 128 different addresses to choose from, although not all these addresses have their own display location. In fact, there are only 80 display locations laid out on a single line in one-line mode or 40 display locations laid out on each line in two-line mode. Now, as it turns out, not all display locations are necessarily visible on the screen at one time. This will be made more apparent in a moment. Let's first try a simple address example with the LCD module set to two-line mode (provided that two lines are actually available).

To position the cursor to a desired location, we use the Set Address command. This command is specified with the binary code 1000 0000 + (binary value of desired hex address). For example, to send a command telling the cursor to jump to the 07_H address location, we apply (1000 0000 + 0000 0111) = 1000 0111 to the D₇–D₀ inputs, remembering to hold RS low and then pulsing E low. The cursor should now be located at the eighth position over from the left.

It is important to realize that the relationship between addresses and display locations varies from module to module. Most displays are configured with two lines of characters, with the first line starting at address 00_H and the second line at address 40_H. Figure 12.141 shows the relationship between the address and display locations for various LCD modules. Note that the four-line module is really a two-line type with the two lines split, as shown in the figure.

SHIFTING THE DISPLAY

Regardless of their size, LCD modules have 80 display locations that can be written to. With smaller displays, not all 80 locations can be displayed at once on the screen. For example, if we were to enter all the letters of the alphabet onto the first line of a 20-character display, only letters A through T would appear on the screen. Letters S through Z, along with the cursor, would be "pushed off" to the right of the screen, hidden from view.

To bring these hidden characters into view, we can apply the Cursor/Display Shift command to shift all display locations to the left. The command for shifting to the left is 0001 1000. Every time this command is issued, the characters shift one step to the left. In our example, it would take seven of these commands to bring T through Z and the cursor into view.

To shift things to the right, we apply the command 0001 1100. To bring the cursor back to address 00_H and shift the display address 00_H back to the left-hand side of the display, a Cursor Home command (0000 0010) can be issued. Another alternative is to use the Clear Display command 0000 0001. However, this command also clears all display locations.

CHARACTER ENTRY MODE

If you do not want to enter characters from left to right, you can use the Character Entry Mode command to enter characters from right to left. To do this, the cursor must first be sent to the rightmost display location on the screen. After that, the Character Entry Mode command 0000 0111 is entered into the module. This sets the entry mode to autoincrement/display shift left. Now, when characters are entered, they appear on the right-hand side, while the display shifts left for each character entered.

USER-DEFINED GRAPHICS

Commands 0100 0000 to 0111 1111 are used to program user-defined graphics. To program these graphics on-screen, the display is cleared, and the module is sent a Set Display Address command to position the cursor at address 00H. At this point, the contents of the eight user character locations can be viewed by entering binary data 0000 0000 to 0000 0111 in sequence. These characters will appear initially as garbage.

To start defining the user-defined graphics, a Set CGRAM command is sent to the module. Any value between 0100 0000 (40H) and 0111 1111 (7F) will work. Data entered from now on will be used to construct the user-defined graph, row by row. For example, to create a light bulb, the following data entries are made: 0000 1110, 0001 0001, 0001 0001, 0001 0001, 0000 1110, 0000 1010, 0000 1110, 0000 0100. Notice that the first three most significant bits are always 0 because there are only 5 pixels per row. Other user-defined graphics can be defined by entering the 8-byte sequence, and so on. Figure 12.142 shows how the CGRAM address corresponds to the individual pixels of the user-defined graphic.

There are up to eight user-defined graphics that can be programmed. These then become part of the character set and can be displayed by using codes 0000 0000 to 0000 1111 or 0000 1000 to 0000 1111, both of which produce the same result.

One problem when creating user-defined graphics is they will be lost when power is removed from the module—a result of the volatile CGRAM. Typically, the user-defined graphic data is actually stored in an external nonvolatile EPROM or EEPROM, where the data is copied by a microprocessor and loaded into the display module sometime after power-up.

4-BIT DATA TRANSFER

As indicated in the Function Set command, the LCD module is capable of both 8-bit and 4-bit data transfer. In 4-bit mode, only data lines D₄–D₇ are used. The other four lines, D₀–D₃, are left either floating or tied to the power supply. To send data to the display requires sending two 4-bit chunks instead of one 8-bit word.

When power is first applied, the module is set up for 8-bit transfer. To set up 4-bit transfer, the Function Set command with binary value 0010 0000 is sent to the display. Note that since there are only four data lines in use, all 8 bits cannot be sent. However, this is not a problem, since the 8-bit/4-bit selection is on data bit D₄. From now on, 8-bit character and command bits must be sent in two halves, the first 4 most significant bits and then the remaining 4 bits. For example, to write character data 0100 1110 to the display requires setting RS high, applying 0100 to the data lines, pulsing E low, then applying 1110 to the data lines, and pulsing E low again.

The 4-bit transfer is frequently used when the LCD module is interfaced with a microcontroller that has limited I/O lines. See Fig. 12.142.

MROM

An MROM is a custom memory device that is permanently programmed by the manufacturer simply by adding or leaving out diodes or transistors within a memory matrix. In order to create a desired memory configuration, you must supply the manufacturer with a truth table stating which data configuration is desired. Using the truth table, the manufacturer then generates a mask that is used to create the interconnections within the memory matrix during the fabrication process.

As you can imagine, producing a custom MROM is not exactly cheap; in fact, it is rather costly (more than $1,000). It is only worthwhile using an MROM if you plan to mass produce some device that requires the same data instructions (for example, program instructions) over and over again—no upgrades to memory needed in the future. In this case, the cost for each IC—after the initial mask is made—is relatively cheap, assuming you need more than a couple thousand chips.

MROMs are commonly found in computers, where they are used to store system operating instructions and data that is used to decode keyboard instructions.

PROM

PROMs are fusible-link programmable ROMs. Unlike the MROM, with PROM devices, data is not etched in stone. Instead, the manufacturers provide you with a memory IC whose matrix is clean (full of 1s). The number of bits and the configuration (n × m) of the matrix vary depending on specific ROM. To program the memory, each fusible link must be blown with a high-voltage pulse (such as 21 V).

The actual process of blowing individual fuses requires a PROM programming unit. This PROM programmer typically includes a hardware unit (where the actual PROM IC is attached), along with programming cable that is linked to a computer (such as via a serial or parallel port). Using software provided by the manufacturer, you enter the desired memory configuration in the program running on the computer and then press a key, which causes the software program to instruct the external programming unit to blow the appropriate links within the IC.

PROMs are relatively easy to program once you have figured out how to use the software, but as with MROMs, once the device is programmed; the memory cannot be altered. In other words, if you mess things up, you must begin afresh with a new chip. These devices were popular some years ago, but today they are considered obsolete.

The most popular ROM-type devices used today are EPROM, EEPROM, and flash memory. These devices, unlike MROM and PROM devices, can be erased and reprogrammed—a very useful feature when prototyping or designing a gadget that requires future memory alterations.

EPROM

An EPROM is a device whose memory matrix consists of a number of specialized MOSFET transistors. Unlike a conventional MOSFET transistor, the EPROM transistor has an additional floating gate that is buried beneath the control gate—insulated from both the control gate and drain-to-source channel by an oxide layer (see Fig. 12.146).

In its erased (unprogrammed) state, the floating gate is uncharged and does not affect the normal operation of the control gate (which when addressed results in a high voltage or logic 1 being passed through to the data lines). To program an individual transistor, a high-voltage pulse (around 12 V) is applied between the control gate and the drain terminal. This pulse, in turn, forces energetic electrons through the insulating layer and onto the floating gate (referred to as hot electron injection). After the high voltage is removed, a negative charge remains on the floating gate and will stay there for decades under normal operating conditions.

With the negative charge in place, the normal operation of the control gate is inhibited; when the control gate is addressed, the charge on the floating gate prevents a high voltage from reaching the data line—the addressed data appears as a low, or logic 0.

In order to reprogram (erase) an EPROM, you must first remove the device from the circuit and then remove a sticker covering its quartz window. After that, you remove all stored charges on the floating gates by shining ultraviolet (UV) light through the window onto the interior transistor matrix. The UV light liberates the stored electrons within the floating gate region by supplying them with enough energy to force them through the insulation. It usually takes 20 minutes of UV exposure for the whole memory matrix to be erased. The number of times an EPROM can be reprogrammed is typically limited to a couple hundred cycles. After that, the chip degrades considerably.

EPROM is often used as nonvolatile memory within microprocessor-based devices that require the provision for future reprogramming. They are frequently used in prototyping and then substituted with MROMs during the mass-production phase. EPROMs are also integrated within microcontroller chips where their sole purpose is to store the microcontroller's main program (more on this in Chap. 13).

EEPROM

An EEPROM device uses a technology somewhat related to the EPROM, but it does not require out-of-circuit programming or UV erasing. Instead, an EEPROM device is capable of selective memory cell erasure by means of controlled electrical pulses.

In terms of architecture, an EEPROM memory cell consists of two transistors: one transistor resembles the EPROM transistor and is used to store data, and the other transistor is used to clear charge from the first transistor's floating gate. By supplying the appropriate voltage level to the second transistor, it is possible to selectively erase individual memory cells instead of having to erase the entire memory matrix, as is the case with EPROM. The only major disadvantage with EEPROM over EPROM is size—due to the two transistors. However, today, with the introduction of new fabrication processes, size is becoming less of an issue.

In terms of applications, EEPROM is ideal for remembering configuration and calibration settings of a device when the power is turned off. For example, EEPROM is found within TV tuners, where it is used to remember the channel, volume setting of the audio amplifier, and so on when the TV is turned off. EEPROM is also found on microcontrollers, where it can be used to store the main program or to hold other nonvolatile data

Flash Memory

Flash memory is generally regarded as the next evolutionary step in ROM technology that combines the best features of EPROM and EEPROM. These devices have the advantage of both in-circuit programming (like EEPROM) and high storage density (like EPROM).

Some variants of flash memory are electrically erasable, like EEPROM, but must be erased and reprogrammed on a device-wide basis, similar to EPROM. Other devices are based on a dual transistor cell and can be erased and reprogrammed on a word-by-word basis. Flash devices are noted for their fast write and erase times, which exceed those of EEPROM devices.

Flash memories are becoming very popular as mass-storage devices. They are found in digital cameras, where a high-capacity flash memory card is inserted directly into a digital camera and can store hundreds or thousands of high-resolution images. They are also used in digital music players, cellular phones, tablets, and so on.

Microcontrollers often include flash memory to contain their program.

Serial Access Memory

So far, we have seen only memories that incorporated parallel access. These devices sit directly on the address and data buses, making it easy for processors to quickly access the memory. Serial access memory is easy to use in principle; however, since all their address lines are typically tied to an address bus within a microprocessor-based system, it is not uncommon for the data to be inadvertently destroyed when the processor runs amuck (issues an undesired write).

Another type of memory that can "hide" the memory from the processor, as well as reduce the total number of pins, uses a serial access format. To move data to and from memory and the processor, a serial link is used. This serial link imposes a strict protocol on data transfers that practically eliminates the possibility that the processor can destroy data accidentally.

Figure 12.147 shows a few serial EPROM and EEPROM devices from Microchip. The SDA pin found in the EEPROM devices acts as a bidirection data lead used to transfer address and data information into the memory IC, as well as transfer data out to the processor. The SCL pin is the serial clock input used to synchronize the data transfer from and to the device. The 24xx64 and 24LC01B/02B EEPROMs also come with special device address inputs A₀, A₁, and A₂, which are used for multiple device operation. WP is used to enable normal memory operation (read/write entire memory) or inhibit write operations.

Controlling a serial memory device is a bit complex, due to the serial protocol and variations in protocol from IC to IC. If you want to learn more about these serial memories (and you should—they are very handy in microcontroller applications for logging data and storing programs and similar tasks), check out the various manufacturers' websites and read through their data sheets.

Very Simple SRAM

Figure 12.148 shows a very elementary SRAM that is set up with a 4096 (4 K) × 1-bit matrix. It uses 12 address lines to address 4096 different memory locations; each location contains a flip-flop. The memory matrix is set up as a 64 × 64 array, with A₀ to A₅ identifying the row and A₆ to A₁₁ identifying the column to pinpoint the specific location to be used. The box labeled "Row Select" is a 6-to-64 decoder for identifying the appropriate 1-of-64 row. The box labeled "Column Select" is also a 6-to-64 decoder for identifying the appropriate 1-of-64 column.

To write a new bit of data to memory, the bit is applied to D_IN, the address lines are set, the Chip Select input ( ) is set low (to enable the chip), and the Write Enable input ( ) is set low (to enable the D_IN buffer). To read a bit of data from memory, the address lines are set, is set low, and is set high (to enable the D_OUT buffer). See the timing waveforms in Fig. 12.148.

By combining eight 4 K × 1 SRAM ICs together, as shown in the lower circuit in Fig. 12.148, the memory can be expanded to form a 4 K × 8 configuration, which is useful in simple 8-bit microprocessor systems. When an address is applied to the address bus, the same address locations within each memory IC are accessed at the same time. Therefore, each data bit of an 8-bit word applied to the data bus is stored in the same corresponding address locations within the memory ICs.

There are other SRAM ICs that come with configurations larger than n × 1. For example, they may come in, say, an n × 4 or n × 8 configuration. As with the n × 1 devices, these SRAMs can be expanded (two n × 8 devices could be combined to form an n × 16 expanded memory, four n × 8 devices could be combined to form an n × 32 expanded memory, and so on).

Serial SRAM with a similar interface to serial EEPROM is also available. For an example of the types of serial SRAM available see http://ww1.microchip.com/downloads/en/DeviceDoc/22127a.pdf.

Note on Nonvolatile SRAMs

In many applications, it would be ideal to have a memory device that combines both the speed and cycle endurance of an SRAM with the nonvolatile characteristics of ROM devices. To solve this problem, manufacturers have created what are called nonvolatile SRAMs. One such device incorporates a low-power CMOS SRAM together with a lithium battery and power-sensory circuitry. When the power is removed from the chip, the battery kicks in, providing the flip-flops with sufficient voltage to keep them set (or reset). SRAMs with battery backup, however, have limited lifetimes due to the life expectancies of the lithium batteries—around ten years.

Another nonvolatile SRAM that requires no battery backup is referred to as nonvolatile RAM (NOVRAM). These chips incorporate a backup EEPROM memory array in parallel with an ordinary SRAM array. During normal operation, the SRAM array is written to and read from just like an ordinary SRAM. When the power supply voltage drops, an onboard circuit automatically senses the drop and performs a store operation that causes all data within the volatile SRAM array to be copied to the nonvolatile EEPROM array. When power to the chip is turned on, the NOVRAM automatically performs a recall operation that copies all the data from the EEPROM array back into the SRAM array. A NOVRAM has essentially unlimited read/write endurance, like a conventional SRAM, but has a limited number of store-to-EEPROM cycles—around 10,000.

DRAM

Figure 12.149 shows a very basic 16 K × 1 DRAM. Normally, to access all 16,384 memory locations (capacitors) would require 14 address lines. However, in this DRAM (as within most large-scale DRAMs), the number of address lines is cut in half by multiplexing.

To address a given memory location is a two-step process. First, a 7-bit row address is applied to A₀–A₆, and then Row Address Strobe is sent low. Second, a 7-bit column address is applied to A₀–A₆, and then Column Address Strobe is sent low. At this point the memory location is latched and can now be read or written to by using the input. When is low, data is written to the RAM via D_in. When is high, data is read from the RAM via D_out. See the timing waveforms in Fig. 12.149.

Simple DRAM devices like this must be refreshed every 2 ms or sooner to replenish the charge on the internal capacitors. For our simple device, there are three ways to refresh the cells: use a Read cycle, use a Write cycle, or use an -only cycle. Unless you are reading or writing to and from all 128 rows every 2 ms, the -only cycle is the preferred technique. To perform this cycle, is set high, A₀–A₆ are set up with the row address 000 0000, is pulsed low, the row address is then incremented by 1, and the last two steps are repeated until all 128 rows have been accessed.

As you can see, needing to come up with the timing waveforms to refresh the memory is a real pain. For this reason, manufacturers produce DRAM controllers or actually incorporate automatic refreshing circuitry within the DRAM IC. In other words, today's DRAMs have all the "housekeeping" functions built in. Practically speaking, this makes the DRAM appear static to the user.

DRAM technology is changing very rapidly. Today, there are a number of DRAM-like devices that go by such names as ECC DRAM, EDO DRAM, SDRAM, SDRAM II, RDRAM, and SLDRAM (we will discuss some of these at the end of this chapter).

Computer Memory

As mentioned, you typically do not need to worry about RAM. (The only real exception would be NOVRAM that is used in many EEPROM-like applications.) RAM is usually either already integrated into a chip, such as a microcontroller, or is placed in reduced pin devices like single in-line memory modules (SIMMs) or dual in-line memory modules (DIMMs) that slide (snap) into a computer's memory bank sockets. In both cases, not much thought is needed—assuming you are not trying to design a microcontroller or computer from scratch. The main concern nowadays is figuring out what kind of RAM module to buy for your computer.

Within computers, RAM is used to hold temporary instructions and data needed to complete tasks. This enables the computer's CPU to access instructions and stored data in memory very quickly. For example, when the CPU loads an application, such as a word processor or page layout program, into memory, the CPU can quickly find what it needs, instead of needing to search for bits and pieces from, say, the hard drive or external drive. For RAM to be quick, it must be in direct communication with the computer's CPU. Early on, memory was soldered directly onto the computer's system board (motherboard). However, over time, as memory requirements increased, having fixed memory onboard became impractical. Today, computers house expansion slots arranged in memory banks. The number of memory banks and the specific configuration vary, depending of the computer's CPU and how the CPU receives information.

Historically, computers initially used either SIMM or DIMM memory modules. Both types of modules use dynamic RAM ICs as the core element. The actual SIMM or DIMM module resembles a PCB and houses a number of RAM ICs that are expanded onboard to provide the necessary bit width required by the CPU using the module. To install a SIMM or DIMM module, simply insert the module into one of the computer memory banks sockets found on the motherboard. Many computer systems use 168-pin DIMMs. Older Pentium and later 486 PCs commonly use 72-pin SIMMs, while still older 486 PCs commonly use 30-pin SIMMs.

A variation on standard sizes of DIMM memory is the SODIMM. SODIMM (Small Outline DIMM) are electrically the same as standard DIMMs but smaller in size and intended for use in laptop computers.

DIMMs

DIMMs have opposing pins electrically isolated to form two separate contacts. DIMMs are often used in computer configurations that support a 64-bit or wider memory bus.

Each new generation of memory brings with it new formats of DIMM, with strategically placed slots to prevent accidental insertion of the wrong type of memory.

DDR3 memory comes in 240-pin DIMMs. Figure 12.150 shows a somewhat simpler sample package from an old 16 M × 64-bit synchronous DRAM that comes in a 168-pin DIMM package.

DRAM Technology Used in Computer Memories

A number of DRAM technologies are incorporated into computer memory modules these days. Extended data out (EDO) memory is a technology that allows the CPU (ones that support EDO) to access memory 10 to 20 percent faster than standard DRAM chips.

Another variation of DRAM is the synchronous DRAM (SDRAM), which uses a clock to synchronize signals input and output on a memory chip. The clock is coordinated with the CPU clock so the timing of the memory chips and the timing of the CPU are in synch. Synchronous DRAMs save time in executing commands and transmitting data, thereby increasing the overall performance of the computer. SDRAM allows the CPU to access memory approximately 25 percent faster than EDO memory.

Double-data-rate SRAM (DDR or SDRAMM II) is a faster version of SDRAM that is able to read data on both the rising and falling edges of the system clock, thus doubling the data rate of the memory chip. Rambus DRAM (RDRAM) is an extremely fast DRAM technology that uses a high-bandwidth "channel" to transmit data at speeds about ten times faster than a standard DRAM.