Set-up is the initial selection and determination of materials, processes, and requirements. It is the one process that does not deal with the physical board but rather determines what materials are used, how many materials are used, in what order they are placed, and so on.

Specify the Core Material Type

Most materials stocked by manufacturers are up to IPC standards. (Check with IPC 4101 for materials.) The thickness tolerance for this material should be no more than +/-.002″[.0508]. The core material is a fiberglass dielectric that is copper clad (Figure 2-1). It is important not to specify the copper or the dielectric thickness at this point. A design may be composed of several combinations of core material separated by pre-impregnated fiberglass, as shown in Figure 2-2.

Figure 2-1. Core material.

Figure 2-2. Pre-preg material.

Note

Dielectric is material that is placed between conductors that acts as an insulator. Core and Pre-Preg are both dielectrics.

Define: IPC material is defined by Tg rating and various other attributes. Check IPC-4101 for the material for the necessary type.

Sample Note: Core Material In Accordance With IPC-4101/21, Laminated Sheet, Copper-Clad, Type GF Glass Cloth Base, Flame Resistant. See Table (Layer Stack-Up) For Recommended Core Thickness, Layer Stack-Up, And Overall Board Thickness (Including Foil And Plating).

Specify the Pre-Preg

Pre-preg is a fiberglass-type material that is pre-impregnated with an adhesive used to adhere to the core material and to provide an insulator between the copper layers. (Check with IPC 4101 for materials.) The tolerance for this material should be no more than +/-.001″[.0254]. Pre-preg comes in sheets in the thickness of .002″[.0508] each. The pre-preg is stacked to create the desired thickness, therefore the material tolerance is additive.

Figures 2-3 and 2-4 show pre-preg before and after pressing. Pre-preg comes in individual sheets and are stacked together as necessary to produce the desired thickness.

Figure 2-3. Pre-preg material after pressing.

Figure 2-4. Core stack-up cross section.

Define: This is the same as the core material. The core and pre-preg material can be incorporated in one single note.

Sample Note: Pre-Preg Material In Accordance With IPC-4101/21; See Table (Layer Stack-Up) For Recommended Core Thickness, Layer Stack-Up, And Overall Board Thickness (Including Foil And Plating).

Note

Do not hold the manufacturer to the minimum core/pre-preg thickness tolerance, unless thickness is critical in cases such as controlled impedance boards.

Define Layer Stack-Up

There are two types of PCBs: single/double sided boards, and multilayer boards. Materials usually come in a sandwich style, which is perfect for core material. There are separate materials for both core material and multi-layer material because of the way they are measured. Core material is measured by the overall thickness of the material. The multi-layer materials are measured by core dielectric and the copper separately.

As material becomes scarce, more and more manufacturers are using only multi-layer material. When discussing multi-layer material, “1/1–30” or “1 over 1 with a 30 core” is used to identify the material. This breaks down to 1 oz copper, sandwiching a .030″[.762mm] core material.

Note

A common difficulty in the PCB industry is the different forms of measurements used. 1 oz is equivalent to .0014″[.0360]. 1 mil is equivalent to .001″[.0254].

Multilayer material also comes in more variations than does core material. Determining which type and thickness to use will be discussed in Chapter 5, “Designing a PCB.”

Note

To reduce materials stocked and cost, many manufacturers are using only multi-layer materials.

For multi-layers, the choice is between core stack-up and foil stack-up. Core stack-up is an older-style stack-up that utilizes the core material on the external layers of the board, as shown in Figure 2-4.

Foil stack-up (Figure 2-5) is the newer generation stack-up that allows less restriction. For example, with a core stack-up on a four-layer board, two core materials are required and only one layer of pre-preg. This usually forces the manufacturer to take the overall board thickness, subtract the four layers of copper, divide the remainder by three and attempt to use the same thickness material for the two core materials (or a close value), and then make up the remainder with dielectric material. With the foil stack-up, a majority of the board is made up with a core material and the remainder is divided between the two dielectric materials. This allows for maximum flexibility.

Figure 2-5. Foil multi-layer cross section.

There are several combinations of information and values that need to be conveyed to the manufacturer in several different ways. A graphical representation of the board cross section is the clearest fashion and provides a quick and easy reference. This, in combination with specific manufacturing notes, proves to be the chosen combination. Here are the most common pieces of information to provide with the graphical cross section:

• Layer number—. Number the copper sheet using L1, L2, and so on. Also use type descriptors for the other layers, such as TS for top silk screen, BS for bottom silk screen, TM for top solder mask, and BM for bottom solder mask (Figure 2-6), or a more descriptive table may be used.

  

  Figure 2-6. Stack-up table of the board cross section.

• Layer type—. Describe the layer/material type dielectric/core/pre-preg for the dielectric material and for the copper layers, Cu signal/Cu plane/Cu plating. (Cu is the elemental representation for copper.)

• Material weight and/or thickness—. A combination of weight and thickness provides a good reference for both the designer and the manufacturer.

• Overall thickness.

• Overall tolerance.

Any other elements necessary that are layer-specific should also be added to the stack-up table, including controlled impedance and minimum trace width by layer. Usually a simple minimum trace note will suffice, but when the trace width values are at the minimum value for the technology, a layer-specific detail may be necessary to avoid confusion.

Define the Material Type

Specifying either copper or dielectric material is not an option, but the specific dielectric material is an option. If a designer is using common materials thickness, the specific dielectric type may be excluded (Figure 2-6). A note should be used to clarify to the manufacturer that this is the designer's option; otherwise display the specific materials used (Figure 2-7).

Figure 2-7. Specifying the materials.

Note

Use of dielectric material is at the discretion of the manufacturer.

Define the Copper Thickness

Copper thickness should be specified in the graphic as shown in Figure 2-8 and then the tolerance for all copper thickness placed in a note.

Figure 2-8. Specifying the copper thickness.

Define: The copper thickness tolerance should be specified if not specified by an IPC specification.

Sample Note: Copper thickness tolerance shall be +/- .002″[.0508] for all layers.

Note

Since copper is in a small range of thickness, this note will usually be on all drawings.

Define the Material Tolerance

If IPC material is not specified, the material tolerance will need to be noted. Make sure that if IPC material is specified, the material tolerance is not specified or verify what the material tolerance is, and ensure that the tolerance specified is the same. Conflicting values will result in delays.

Define: Material tolerances are layer specific or in a +/- value. It should be displayed in the graphic table to explain clearly which layer is which, as shown in Figure 2-9. If the value is common to all dielectric or copper layers, then a single +/- value or % may be used in a note.

Figure 2-9. Material tolerance specified.

Sample Note: Dielectric material tolerance for all layers is +/-.005.

Set-up is the portion of the fabrication process in which all the information is gathered, sorted, and defined and a determination of manufacturability is made.

The imaging process transfers the image of a single layer of Gerber information to etch resist (a protective coating) adhered to the copper, by directly imaging the information to the etch resist or by copying from a film that has the image of the Gerber layer drawn on the film.

This is the point where the information from the Gerber files is phototransmitted onto an etch-resist film that is placed on copper-clad material (Figures 2-10 and 2-11).

Figure 2-10. Direct imaging.

Figure 2-11. Indirect imaging.

Etching is the process in which a chemical is applied and the copper and unprotected areas are removed (Figure 2-12), leaving the intended circuit. Other emerging processes, such as plasma etch, may be used to accomplish the same task.

Figure 2-12. Board ready for etching.

Using the conventional chemical etch process, the unprotected area is etched away (or removed), similar to digging a ditch, in an effective but inefficient process (Figure 2-13). Using the conventional etch process the edge of a trace (and pads) is malformed. For each .001″[.0254] of raise, there is an amount of slope. Trace clearance is measured from the closest point of each perpendicular trace to provide sufficient spacing. This requires more time during etch per ounce of copper to create a larger gap at the opening of the trace, as shown in Figures 2-14 and 2-15. This is known as an etch factor. It is important to know what the manufacturer's etch factor is to calculate the minimum capable per ounce in the event the manufacturer doesn't provide a clear table of minimum clearances per ounce of copper. Table 2-2 shows the amount of width added per ounce of copper to account for the etch factor. Table 2-3 is a quick reference table that shows the minimum amount of clearance, per ounce of copper, to be used to account for the increase in trace width. The “real” minimum clearance is actually smaller than the values quoted, or listed in most tables, capability charts are in reference to 1/2 oz (.0007″[.0178]) copper. This is the designer's minimum clearance, thus avoiding confusion.

Figure 2-13. Chemical etch process.

Figure 2-14. Starting and finished trace and space.

Figure 2-15. Etching errors.

The etch factor also affects the manufacturer's annular ring. Conventional AR is .003″[.0762] for imaging + .003″[.0762] for drill + .003″[.0762] for stack-up, creating .009″[.2286] overall. Etch or the etch factor is one of the four main controlling items that define the technology.

Conventional etching dictates that the starting traces may be no closer than .005″[.127] because of resist fallout, spacing requirements for the etch chemical to work, and so on. In addition, because of the “etch-back” or undercutting that occurs during the etch process, the trace widths must be increased to account for the etch-back. This value is determined by the thickness of copper. The thicker the copper, the longer the etch takes to eat away the copper between the traces and under the etch resist.

Two values that must be accounted for in the chemical etch processes are

The conventional etch factor (Table 2-2) is about .0007″[.0118] per size or .0014″[.0356] for the overall trace width per ounce. This means that for each ounce of copper the trace width must be increased by .0014″[.0356].

These values are for the manufacturer to increase the trace width in the artwork/film.

For clearance/spacing requirements, this value is added in addition to the minimum Etch clearance/space, to form the minimum clearance/space per ounce, as listed in Table 2-3.

The manufacturer's etch factor (Table 2-2) and the copper thickness determine the manufacturer's minimum trace width (Table 2-3) (per ounce). A 6/6 value usually refers to the minimums or .006″[.1524] Trace/.006″[.1524] space on a 1/2 ounce starting copper.

A new process creating new standards and the demise of the chemical process is plasma etch. In addition to no etch-back, this process also eliminates imaging, or film error using a direct imaging process, which transfers the layer image directly to the material. This eliminates the etch factor, reduces the minimum trace and space, eliminates the imaging error factor, and reduces the manufacturer annular ring. Compare the conventional MFG. AR (.009″[.2286]) to the leading-edge MFG. AR (.001–.002″[.0254–.0508]). This is a reduction of .007″[.1178], which is the main factor in the reduction of vias and all other nonsoldered plated thru-holes. An .008″[.2032] via, which conventionally requires an .030″[.762] pad, would only require a .012″[.3048] pad using leading-edge manufacturing, reducing the pad by .018″[.4572]. Other methods, such as laser drilling, can reduce the hole diameter resulting in an even smaller pad.

Smaller trace widths are more difficult to etch repeatedly; thus manufacturers have a limit to how small a trace they can and will repeatedly process. Because of the etch factor and etch-back, manufacturers will increase the trace width and pad diameters on the image/film so the board will finish at the required width (Figure 2-16). The increase is built into the minimum spacing requirements, and if the clearance requirements are followed, the minimum trace width remains the same regardless of copper thickness.

Figure 2-16. Trace width tolerance.

A design that has oversized traces, to account for etch-back, will be limited to that technology since different manufacturers use different technologies with different etch-back allowances.

Multilayer pressing is the process in which several copper-clad layers are aligned and adhesive insulate material is placed between the layers (Figure 2-17), which are pressed under high pressure and heat, forming a solid board (Figure 2-18). Figure 2-19 displays a board with one layer off center, which is still useable because of the manufacturer's annular ring requirements.

Figure 2-17. Multilayer before pressing.

Figure 2-18. Multilayer during pressing.

Figure 2-19. Layer off center.

Drilling occurs when several boards are stacked and placed side by side and drilled simultaneously .005″[.127] to .006″[.1524] over the “finished” hole size. The .005″[.127] (depending on plating requirements, detailed in the “Plating/Hole Plating” section) over the finished hole size is to account for the amount of plating that will go into the hole. Holes that are to be drilled through copper but are not plated are drilled at a later time (detailed in the “Second Drill” section).

The manufacturer has limits of how small a drill may be used per board thickness. The rule is, the thinner the board the smaller the drill bit able to be used. This value is the aspect ratio (see Table 2-4). There is the starting aspect ratio and the finished aspect ratio. The starting aspect ratio is the size the hole is actually drilled with, and the finished aspect ratio includes the standard plating. The manufacturer refers to the actual drilled size, and a designer deals with finished hole size. The designer must be very sure what value is being referred to here. The aspect ratio is limited to the minimum drill, so no matter how small the calculation of the aspect ratio comes out, it may be no smaller than the finished minimum drill. The terms starting and finished should always be used when discussing drilled size and aspect ratios for clarity. Aspect ratio is also in reference to the board before plating.

This is the point at which both the board and the PLTH (plated thru-hole) are plated with copper (Figure 2-20). The boards are placed in an electrically charged bath of copper that plates all of the copper surface areas (normally .0014″[.035] or 1oz) and is drawn into thru-holes located in copper, such as a pad. (This explains why unplated holes that are drilled through copper are drilled later.)

Figure 2-20. Hole cross section showing annular ring.

Hole plating is controlled by external copper plating thickness. The hole plating will actually be a little less (roughly .0004″–.0005″) than the external plating. This is critical when determining the current carrying capacity of a plated thru-hole.

As noted in the “Board Finish” section, the board is coated with about .0010″[.025] of solder, making the total thickness of the hole wall .0020 (leaving .0005″ of tolerance). This is a total of .0025″[.0635] on the hole wall and .005″[.127] overall. This forces the drilled hole to be .005″[.127] over the “finished” hole.

The plating or hole-plating note may be skipped if the plating thickness is adequately noted in the material stack-up table.

Boards with blind and buried vias go through this process several times and are treated as several different boards. They are finally pressed together, then drilled and plated.

Figure 2-21 shows the effects of drilling off center to the limits. A drill that is offset should be offset on both sides of the board.

Figure 2-21. Drill off center.

Second drill is required when holes are placed in a copper area and the hole should not be plated. Pads around a hole with no plating are known as unsupported pads; they must be larger than pads with plating in the hole for several reasons. The plating keeps the pad from twisting off, dissipates heat, and keeps the pad from lifting from the material when soldered. Such holes add this process, which increases overall cost. If any hole is plated, then all holes should be plated or there should be clear areas around holes in copper areas to eliminate a second drill.

A protective mask (if specified) is placed on the board for the following reasons (Figure 2-22):

Figure 2-22. Masked board.

The mask may be placed on the bare copper (SMOBC recommended) or over a thin film of solder.

This is the point in the process after the solder mask has been placed on the board and only copper pads remain. To protect the copper area as well as prepare the area for soldering, the pad is coated with a thin layer of solder. This is usually done with a hot air solder leveler (HASL) (Figure 2-23). It is not necessary to specify the process.

Figure 2-23. HASL after masking.

At this point the markings for reference designation and component outline are taken from the design and copied to the board.

Routing removes multiple boards from a panel while cutting the board to the desired size. Most slots and notches are cut out at this point. Contact your manufacturer about standard holes that can be placed in the boards to help them route the board (tooling holes). All edges and corners are cut with a round bit, so any internal corner must be a radius. If a true 90 is required, contact your manufacturer for the “how-to” information.

The overall board dimension tolerance may be up to +/-.005″. This is the reason behind the clearance necessary on all board edges. Copper-to-edge clearance for board edge, slots, and cutouts is .010″–.020″ + the required voltage isolation clearance.

The outline of the board and all slots should be drawn with a line twice the width of the clearance for “copper to board edge.” Note that all cuts shall be made to the center of the line.

Slots that will be plated should be noted and have adequate annular ring (similar to the pad annular ring) along with adequate clearance on all layers/inner layers. It is not desired that copper (especially on inner layers) come in contact with the router bit. (This topic will be explored further in Chapter 5.)

The board outline and the lines drawn for slots/cutouts should be copied to all inner-plane layers to create copper to edge clearance.

Quality control (QC) is the point at which the board is checked against the designer's specification and the manufacturer's tolerances.

When a multilayer board is complete, hole wall quality is a great concern because of the additional factors not found in a SS/DS board. Ask if the manufacturer does a cross section or a cross-section coupon for its multilayer boards. If it does not, request that it be done unless the manufacturer has another process that allows it to inspect the quality of the hole wall that is less invasive.

Electrical tests may be used to check for continuity and shorts and compare against the original data files. The original data files are the Gerbers, which may or may not match the original design. There are alternatives, such as database transfer formats, that provide a better method of data transfer.