Index

  1. abstraction level
  2. active
  3. active byte
  4. active byte with respect to the difference
  5. addition chain
  6. additive inverse
  7. AddRoundKey
  8. AES
  9. AES-128
  10. AES-192
  11. AES-256
  12. AES-comp
  13. AES-pprm1
  14. algorithmic noise
  15. all property
  16. AND
  17. arithmetic logic unit
  18. asynchronous-style design flow
  19. attack complexity
  20. attack model
  21.  
  22. balanced property
  23. basic impossible characteristic
  24. binary field
  25. block
  26. block cipher
  27. Boolean domain
  28. Boolean functions
  29. Boolean masking
  30. burst access mode
  31.  
  32. carry-select adder
  33. ciphertext
  34. clock
  35. clock edge
  36. clock jitter
  37. clock period
  38. clock signal
  39. clock skew
  40. clockwise collision
  41. clockwise collision analysis
  42. codebook
  43. combinatorial logics
  44. complementary metal-oxide-semiconductor (CMOS)
  45. constant property
  46. controller
  47. correlation power analysis (CPA)
  48. correlation-enhanced power analysis collision attack
  49. counter mode
  50. countermeasures
  51. critical fault injection intensity
  52. critical path delay
  53. cryptology
  54. cryptosystems
  55. CTR mode
  56.  
  57. data
  58. data signals
  59. datapath
  60. decryption oracle
  61. delay flip flop (DFF)
  62. design automation (DA)
  63. determining bit
  64. diagonal
  65. dictionary attack
  66. difference
  67. difference of means (DoM)
  68. differential characteristic
  69. differential distribution table (DDT)
  70. differential fault analysis (DFA)
  71. differential power analysis (DPA)
  72. distinguishing attack
  73. divide-and-conquer
  74. dynamic timing analysis (DTA)
  75.  
  76. encryption
  77. encryption oracle
  78. equivalent transformation of the subkey addition
  79. evaluation function
  80. evaluation phase
  81. exhaustive search
  82. extended binary field
  83.  
  84. false path
  85. fault attack (FA)
  86. fault model
  87. fault sensitivity (FS)
  88. fault sensitivity analysis (FSA)
  89. filtering
  90. filtering power
  91. finite filed
  92. finite state machine (FSM)
  93. full adder (FA)
  94.  
  95. Galois field
  96. gate equivalent
  97.  
  98. Hamming distance (HD) model
  99. Hamming weight (HW) model
  100. hiding logics
  101. higher-order integral cryptanalysis
  102. hold buffer
  103. hold time
  104.  
  105. implementation attacks
  106. impossible differential cryptanalysis
  107. indistinguishability
  108. input difference
  109. INV
  110. inverse diagonal
  111. inversion
  112. involution
  113. irreducible polynomial
  114.  
  115. key lifetime
  116. key recovery resistance
  117. key schedule function (KSF)
  118. key space
  119.  
  120. latency
  121. layout
  122. leakage model
  123. least significant bit (LSB)
  124. linear functions
  125. logic synthesis
  126. logical gates
  127. loop architecture
  128. loop-unrolled
  129.  
  130. mask
  131. masked AND
  132. masking countermeasures
  133. masking logics
  134. maximum distance separable
  135. memory
  136. message
  137. MixColumns
  138. mode of operation
  139. module
  140. most significant bit (MSB)
  141. multiple impossible differential characteristics
  142. multiplicative inverse
  143.  
  144. negative edge
  145. negative logic
  146. netlist
  147. non-profiling analysis
  148. nonlinear functions
  149. normal basis
  150.  
  151. OR
  152. oracle
  153. output difference
  154.  
  155. parallel architecture
  156. path delay
  157. physical attacks
  158. pipeline architecture
  159. pipeline stall
  160. plaintext
  161. plaintext recovery resistance
  162. polynomial basis
  163. positive edge
  164. positive logic
  165. precharge phase
  166. precharge value
  167. profiling analysis
  168. pseudo-Random Permutation
  169.  
  170. queries
  171.  
  172. random switching logic (RSL)
  173. ranking test
  174. reduced instruction set computer (RISC)
  175. register file
  176. register transfer level (RTL)
  177. reset
  178. reset signal
  179. right pairs
  180. ripple-carry adder
  181. round function
  182. round operation
  183.  
  184. S-box
  185. scalability
  186. selection function
  187. sequential logics
  188. setup time
  189. shares
  190. ShiftRows
  191. side-channel attack (SCA)
  192. side-channel information
  193. signal toggles
  194. signal-to-noise ratio
  195. simple power analysis (SPA)
  196. spatial duplication
  197. state
  198. static random access memory (SRAM)
  199. static timing analysis (STA)
  200. structure
  201. SubBytes
  202. subkey space
  203. subkeys
  204. substitution table
  205. substitution-permutation network (SPN)
  206. synchronous design
  207.  
  208. tamper-proofed device
  209. temporal duplication
  210. threshold implementation (TI)
  211. throughput
  212. time
  213. traces
  214. transfer gate (TG)
  215. true paths
  216. truth table
  217.  
  218. Verilog HDL
  219. Vernam cipher
  220.  
  221. wave dynamic differential logic (WDDL)
  222. whitening
  223. wide trail strategy
  224. wires
  225. write enable signal
  226. wrong pairs
  227.  
  228. XOR
  229.  
  230. zero-value analysis
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