- Cover
- Title Page
- Copyright
- Acknowledgments
- Chapter 1: Basic Memory Device Trends Toward the Vertical
- Chapter 2: 3D Memory Using Double-Gate, Folded, TFT, and Stacked Crystal Silicon
- 2.1 Introduction
- 2.2 FinFET—Early Vertical Memories
- 2.3 Double-Gate and Tri-Gate Flash
- 2.4 Thin-Film Transistor (TFT) Nonvolatile Memory with Polysilicon Channels
- 2.5 Double-Gate Vertical Channel Flash Memory with Engineered Tunnel Layer
- 2.6 Stacked Gated Twin-Bit (SGTB) CT Flash
- 2.7 Crystalline Silicon and Epitaxial Stacked Layers
- References
- Chapter 3: Gate-All-Around (GAA) Nanowire for Vertical Memory
- 3.1 Overview of GAA Nanowire Memories
- 3.2 Single-Crystal Silicon GAA Nanowire CT Memories
- 3.3 Polysilicon GAA Nanowire CT Memories
- 3.4 Junctionless GAA CT Nanowire Memories
- 3.5 3D Stacked Horizontal Nanowire Single-Crystal Silicon Memory
- 3.6 Vertical Single-Crystal GAA CT Nanowire Flash Technology
- 3.7 Vertical Channel Polysilicon GAA CT Memory
- 3.8 Graphene Channel Nonvolatile Memory with Al2O3–HfOx–Al2O3 Storage Layer
- 3.9 Cost Analysis for 3D GAA NAND Flash Considering Channel Slope
- References
- Chapter 4: Vertical NAND Flash
- Chapter 5: 3D Cross-Point Array Memory
- 5.1 Overview of Cross-Point Array Memory
- 5.2 A Brief Background of Cross-Point Array Memories
- 5.3 Low-Resistance Interconnects for Cross-Point Arrays
- 5.4 Cross-Point Array Memories Without Cell Selectors
- 5.5 Examples of Selectorless Cross-Point Arrays
- 5.6 Unipolar Resistance RAMs with Diode Selectors in Cross-Point Arrays
- 5.7 Unipolar PCM with Two-Terminal Diodes for Cross-Point Array
- 5.8 Bipolar Resistance RAMS With Selector Devices in Cross-Point Arrays
- 5.9 Complementary Switching Devices and Arrays
- 5.10 Toward Manufacturable ReRAM Cells and Cross-point Arrays
- 5.11 STT Magnetic Tunnel Junction Resistance Switches in Cross-Point Array Architecture
- References
- Chapter 6: 3D Stacking of RAM–Processor Chips Using TSV
- 6.1 Overview of 3D Stacking of RAM–Processor Chips with TSV
- 6.2 Architecture and Design of TSV RAM–Processor Chips
- 6.3 Process and Fabrication of Vertical TSV for Memory and Logic
- 6.4 Process and Fabrication Issues of TSV 3D Stacking Technology
- 6.5 Fabrication of TSVs
- 6.6 Energy Efficiency Considerations of 3D Stacked Memory–Logic Chip Systems
- 6.7 Thermal Characterization Analysis and Modeling of RAM–Logic Stacks
- 6.8 Testing of 3D Stacked TSV System Chips
- 6.9 Reliability Considerations with 3D TSV RAM–Processor Chips
- 6.10 Reconfiguring Stacked TSV Memory Architectures for Improved Performance
- 6.11 Stacking Memories Using Noncontact Connections with Inductive Coupling
- References
- Index
- End User License Agreement
Vertical 3D Memory Technologies
Betty Prince
CEO, Memory Strategies International, Texas, USA
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