10.2.1 Load or store single structure using one lane

These instructions are used to load and store structured data across multiple registers:

ld<n> Load Structured Data, and

st<n> Store Structured Data.

They can be used for interleaving or deinterleaving the data as it is loaded or stored, as shown in Fig. 10.3.

10.2.1.1 Syntax

• •   must be either or .
• •   must be one of , , , or .
• •   specifies the list of registers. There are four list formats:
  1. 1.  {Vt.T}
  2. 2.  {Vt.T, V(t+1).T} or {Vt.T-V(t+1).T}
  3. 3.  {Vt.T, V(t+1).T, V(t+2).T} or {Vt.T-V(t+2).T}
  4. 4.  {Vt.T, V(t+1).T, V(t+2).T, V(t+3).T} or {Vt.T-V(t+3).T}
  The registers must be consecutive. Register 0 is consecutive to register 31.
• •   must be b, h, s, or d.
• •  The immediate specifies which element of each register is to be used, and must be appropriate for the data size specified by . The same element will be used for all registers.
• •   is the AARCH64 register containing the base address.
• •   is the AARCH64 register containing an offset.
• •  If a register or immediate offset is given, then the base register, , will be post-incremented.
• •  The post-increment immediate offset, if present, must be 8, 16, 24, 32, 48, or 64, depending on the number of elements transferred and the size specified by .

10.2.1.2 Operations

10.2.1.3 Examples

10.2.2 Load or store multiple structures

These instructions are used to load and store multiple data structures across multiple registers with interleaving or deinterleaving:

ld<n> Load Multiple Structured Data, and

st<n> Store Multiple Structured Data.

10.2.2.1 Syntax

• •   must be either or .
• •   must be one of , , , or .
• •   specifies the list of registers. There are four list formats:
  1. 1.  {Vt.T}
  2. 2.  {Vt.T, V(t+1).T} or {Vt.T-V(t+1).T}
  3. 3.  {Vt.T, V(t+1).T, V(t+2).T} or {Vt.T-V(t+2).T}
  4. 4.  {Vt.T, V(t+1).T, V(t+2).T, V(t+3).T} or {Vt.T-V(t+3).T}
  The registers must be consecutive. Register 0 is consecutive to register 31.
• •   must be 16b, 8b, 8h, 4h, 4s, 2s, or 2d. If is 1, then can be 1d.
• •   is the AARCH64 register containing the base address.
• •   is the AARCH64 register containing an offset.
• •  If a register or immediate offset is given, then the base register, , will be post-incremented.
• •  The post-increment immediate offset, if present, must be 8, 16, 24, 32, 48, or 64, depending on the number of elements transferred and the size specified by .

10.2.2.2 Operations

10.2.2.3 Examples

10.2.3 Load copies of a structure to all lanes

This instruction is used to load multiple copies of structured data across multiple registers:

ld<n>r Load Copies of Structured Data.

The data is copied to all lanes. This instruction is useful for initializing vectors for use in later instructions.

10.2.3.1 Syntax

• •   must be one of , , , or .
• •   specifies the list of registers. There are four list formats:
  1. 1.  {Vt.T}
  2. 2.  {Vt.T, V(t+1).T} or {Vt.T-V(t+1).T}
  3. 3.  {Vt.T, V(t+1).T, V(t+2).T} or {Vt.T-V(t+2).T}
  4. 4.  {Vt.T, V(t+1).T, V(t+2).T, V(t+3).T} or {Vt.T-V(t+3).T}
  The registers must be consecutive. Register 0 is consecutive to register 31.
• •   must be 16b, 8b, 8h, 4h, 4s, 2s, or 2d. If is 1, then can be 1d.
• •   is the AARCH64 register containing the base address.
• •   is the AARCH64 register containing an offset.
• •  If a register or immediate offset is given, then the base register, , will be post-incremented.
• •  The post-increment immediate offset, if present, must be 1, 2, 3, 4, 6, 8, 12, 16, 24, or 32, depending on the number of elements transferred and the size specified by .

10.2.3.2 Operations

10.2.3.3 Examples

10.3.1 Duplicate scalar

The duplicate instruction copies a scalar into every element of the destination vector. The scalar can be in an Advanced SIMD register or an AARCH64 integer register. The instruction is:

dup Duplicate Scalar.

10.3.1.1 Syntax

• •  Td1 may be 8b, 16b, 4h, 8h, 2s, or 4s. The lowest n bits of Wn will be used, where n is the number of bits specified by Td1.
• •  Td2 may be 8b, 16b, 4h, 8h, 2s, 4s, or 2d.
• •  Ts can be one of b, h, s, or d, and must match Td2.
• •  Fd may be any of the FP/NEON register names used in Chapter 9.
• •  Td3 may be b, h, s, or d, and must match Fd.
• •  The immediate index must be valid for the type of vector element specified.
• •  MOV Fd Vn.Td[index] is an alias for DUP Fd,Vn.Td[index].
• •  The MOV Fd,Fn instruction, which was introduced in Chapter 9, is an alias for .

10.3.1.2 Operations

10.3.1.3 Examples

10.3.2 Move vector element

These instructions copy one element into a vector:

mov Copy element into vector,

umov Copy unsigned integer element from vector to AARCH64 register, and

smov Copy signed integer element from vector to AARCH64 register.

10.3.2.1 Syntax

• •  T may be 8b, 16b, 4h, 8h, 2s, or 4s.
• •  The lowest n bits of Wn will be used, where n is the number of bits specified by T.
• •  The type T2 may be b, h, s, or d.
• •  The type T3 may be b or h.
• •  Ts may be 8b, 16b, 4h, 8h, 2s, or 4s.
• •  T4 may be b, h, or s.
• •  Both immediates, index and index2, must be valid for the type of vector element specified.
• •  INS Vd.T[index],Wn is an alias for MOV Vd.T[index],Wn.
• •  INS Vd.D[index],Xn is an alias for MOV Vd.2d[index],Xn.
• •  INS Vd.T[index],Vn.T[index2] in an alias for MOV Vd.T[index], Vn.T[index2].

10.3.2.2 Operations

10.3.2.3 Examples

10.3.3 Move immediate

These instructions are used to load immediate data into the vector registers:

movi Vector Move Immediate,

mvni Vector Move NOT Immediate, and

fmov Vector Floating Point Move Immediate.

10.3.3.1 Syntax

• •  sop may be lsl or msl, where msl is a left shift which fills the low order bits with ones instead of zeros.
• •  If sop is not present, then the shift is assumed to be an lsl with shift amount of zero. The valid combinations of T and shift are given by the following table:

sop	T	shift	Description
lsl	4h or 8h	0 or 8	Replicate LSL(uimm8,shift) into each 16-bit element.
lsl	2s or 4s	0, 8, 16, or 24	Replicate LSL(uimm8,shift) into each 32-bit element.
msl	2s or 4s	8 or 16	Replicate MSL(uimm8,shift) into each 32-bit element.

• •  For , if sop is not present, then T may be 8b or 16b, in addition to the values shown in the previous table.
• •  uimm64 may be either 0 or 0xFFFFFFFFFFFFFFFF.
• •  Td may be 2s, 4s, or 2d.
• •  fpimm may be specified either in decimal notation or in hexadecimal using its IEEE754 encoding. The value must be the expressable as $\pm n÷16\times 2^r$, where n and r are integers such that $16\le n\le 31$ and $-3\le r\le 4$. It is encoded as a normalized binary floating point number with sign, 4 bits of fraction, and a 3-bit exponent.

10.3.3.2 Operations

10.3.3.3 Examples

10.3.4 Transpose matrix

Advanced SIMD provides two versions of the transpose instruction that can be used together for transposing $2\times 2$ matrices. Fig. 10.4 shows two examples of this instruction. The instruction is:

trn Transpose Matrix.

10.3.4.1 Syntax

• •  T must be 8b, 16b, 4h, 8h, 2s, 4s, or 2d.
• •  Larger matrices can be transposed using a divide-and-conquer approach.

10.3.4.2 Operation

10.3.4.3 Examples

Fig. 10.5 shows how the instruction can be used to transpose a $3\times 3$ matrix.

10.3.5 Vector permute

These instructions are used to interleave or deinterleave the data from two vectors, or to extract bits from a vector:

zip Zip Vectors,

uzp Unzip Vectors, and

ext Byte Extract.

Fig. 10.6 gives an example of the instruction. The instruction performs the inverse operation.

10.3.5.1 Syntax

• •  T is 8b, 16b, 4h, 8h, 2s, 4s, or 2d.
• •  For and :
  1. –  If 1 is present, use lower half of source registers.
  2. –  If 2 is present, use upper half of source registers.
• •  Ta is either 8b (use only 64 bits of each register) or 16b (use all 128 bits of each register).
• •  index is an immediate value in the range 0 to $nelem(\mathtt{\text{T}})-1$.

10.3.5.2 Operations

10.3.5.3 Examples

10.3.6 Table lookup

The table lookup instructions use indices held in one vector to lookup values from a table held in one or more other vectors. The resulting values are stored in the destination vector. The table lookup instructions are:

tbl Table Lookup, and

tbx Table Lookup with Extend.

10.3.6.1 Syntax

• •   is one of or .
• •  T may be 8b or 16b.
• •   specifies the list of registers. There are five list formats:
  1. 1.  {Vn.16b},
  2. 2.  {Vn.16b, V(n+1).16b},
  3. 3.  {Vn.16b, V(n+1).16b, V(n+2).16b}, or
  4. 4.  {Vn.16b, V(n+1).16b, V(n+2).16b, V(n+3).16b}.
• •  A dash “-” can be used to specify a range of registers, as shown in the examples below.
• •   is the register holding the indices.
• •  The table can contain up to 64 bytes.

10.3.6.2 Operations

10.3.6.3 Examples

10.4.1 Convert between integer or fixed point and floating point

These instructions can be used to perform data conversion between floating point and fixed point (or integer) on each element in a vector:

fcvt Vector convert floating point to integer or fixed point, and

cvtf Vector convert integer or fixed point to floating point.

The elements in the result vector must be the same size as the elements in the source vector. An out of range integer or fixed-point result will be saturated to the destination size.

Fixed point (or integer) arithmetic operations are up to twice as fast as floating point operations. In some cases it is much more efficient to make this conversion, perform the calculations, then convert the results back to floating point.

10.4.1.1 Syntax

• •   is a single character which specifies the rounding mode:

  N: round to nearest with ties to even,

  A: round to nearest with ties away from zero,

  P: round towards +∞,

  M: round towards −∞, or

  Z: round towards zero.

• •  T may be either 2s, 4s, or 2d.
• •   must be either or .
• •   specifies the number of fraction bits for a fixed point number, and must be between 1 and the number of bits specified by T. If it is omitted, then it is assumed to be zero.

10.4.1.3 Examples

10.4.2 Convert between half, single, and double precision

The following instructions can be used to convert between floating point formats:

fcvtl Vector convert from half to single precision,

fcvtn Vector convert from single to half precision, and

fcvtxn Vector convert from double to single precision.

These instructions operate on vectors. There are additional conversion instructions available, but they only operate on scalar values.

10.4.2.1 Syntax

• •  If 2 is present, then the upper 64 bits of the register containing the smaller elements will be used. Otherwise, the lower 64 bits are used.
• •  Td /Ts may be 4s /4h or 2d /2s.
• •  Td2/Ts2 may be 4s /8h or 2d /4s.
• •  Td3/Ts3 may be 4h /4s or 2s /2d.
• •  Td4/Ts4 may be 8h /4s or 4s /2d.

10.4.2.3 Examples

10.4.3 Round floating point to integer

The following instruction can be used to round a vector of floating point values to integers:

frint Round Floating Point to Integer.

10.4.3.1 Syntax

• •  T is 2s, 4s, or 2d.
• •  <x> selects the rounding mode. It may be one of the following:

  N: round to nearest with ties to even,

  A: round to nearest with ties away from zero,

  P: round towards +∞,

  M: round towards −∞,

  Z: round towards zero,

  I: round using FPCR rounding mode, and

  X: round using FPCR rounding mode with exactness test.

10.4.3.3 Examples

10.5.1 Vector logical operations

The bitwise logical operations are:

and Vector bitwise AND,

orr Vector bitwise OR,

orn Vector bitwise NOR,

eor Vector bitwise Exclusive-OR,

bic Vector bit clear,

bif Vector insert if false,

bit Vector insert if true, and

bsl Vector bitwise select.

10.5.1.1 Syntax

• •   must be one of , , , , , , , or .
• •  T is 8b or 16b (though an assembler should accept any other equivalent format).

10.5.1.2 Operations

10.5.1.3 Examples

10.5.2 Bitwise logical operations with immediate data

Advanced SIMD provides vector versions of the logical OR and bit clear instructions:

orr Vector bitwise OR immediate, and

bic Vector Bit clear immediate.

10.5.2.1 Syntax

• •   must be either , or .
• •  T may be either 2s, 4s, 4h, or 8h.
• •  If T is 2s or 4s, then shift may be 0, 8, 16, or 24.
• •  If T is 4h or 8h, then shift may be 0 or 8.
• •  If shift is not specified, then it is assumed to be zero.
• •   is an 8-bit unsigned immediate value, which is shifted left by shift bits to create the desired pattern for the , or operation on each vector element.

10.5.2.3 Examples

10.6.1 Vector add and subtract

The and instructions add corresponding elements in two vectors and store the results in the corresponding elements of the destination register. The and instructions subtract elements in one vector from corresponding elements in another vector and store the results in the corresponding elements of the destination register. Other versions of the add and subtract instructions allow mismatched operand and destination sizes, and the saturating versions prevent overflow by limiting the range of the results. The following instructions perform vector addition and subtraction:

add Vector integer add,

fadd Vector floating point add,

qadd Vector saturating add,

addl Vector add long,

addw Vector add wide,

sub Vector integer subtract,

fsub Vector floating point subtract,

qsub Vector saturating subtract,

subl Vector subtract long, and

subw Vector subtract wide.

10.6.1.1 Syntax

• •  <op> can be add or sub.
• •  If double word registers are specified (Dd, Dn, Dm ) then the operation is a simple add or subtract of scalar 64-bit integer values, and not a vector operation.
• •  The valid choices for T are given in the following table:

Opcode	Valid Values for T
<op>	8b, 16b, 4h, 8h, 2s, 4s, or 2d
f<op>	2s, 4s, 2d
(s|u)q<op>	8b, 16b, 4h, 8h, 2s, 4s, 2d

• •  <sop> can be uadd, sadd, usub, or ssub.
• •  If the modifier 2 is present, then the operation is performed using the upper 64 bits of the registers holding the narrower elements.
• •  The valid choices for Td /Ts are given in the following table:

Opcode	Valid Values for Td /Ts
<sop>l	8h /8b, 4s /4h, 2d /2s
<sop>l2	8h /16b, 4s /8h, 2d /4s
<sop>w	8h /8b, 4s /4h, 2d /2s
<sop>w2	8h /16b, 4s /8h, 2d /4s

10.6.1.2 Operations

10.6.1.3 Examples

10.6.2 Vector add and subtract with narrowing

These instructions add or subtract the corresponding elements of two vectors and narrow the resulting elements by taking the upper (most significant) half:

addhn Vector add and narrow,

raddhn Vector add, round, and narrow,

subhn Vector subtract and narrow, and

rsubhn Vector subtract, round, and narrow.

The results are stored in the corresponding elements of the destination register. Results can be optionally rounded instead of truncated.

10.6.2.1 Syntax

• •   is either or .
• •  If is present, then the result is rounded instead of truncated.
• •  If is present, then the upper 64 bits of the destination vector are used.
• •  The valid choices for Td /Ts are given in the following table:

Opcode	Valid Values for Td /Ts
r<op>hn	8b /8h, 4h /4s, 2s /2d
r<op>hn2	16b /8h, 8h /4s, 4s /2d

10.6.2.2 Operations

10.6.2.3 Examples

10.6.3 Add or subtract and divide by two

These instructions add or subtract corresponding integer elements from two vectors, then shift the result right by one bit:

hadd Vector halving add,

rhadd Vector halving add and round, and

hsub Vector halving subtract.

The results are stored in corresponding elements of the destination vector.

10.6.3.1 Syntax

• •  If is specified, then the result is rounded instead of truncated.
• •  T must be 8b, 16b, 4h, 8h, 2s, or 4s.

10.6.3.2 Operations

10.6.3.3 Examples

10.6.4 Add elements pairwise

These instructions add vector elements pairwise:

addp Vector add pairwise,

addlp Vector add long pairwise, and

adalp Vector add and accumulate long pairwise.

The long versions can be used to prevent overflow.

10.6.4.1 Syntax

• •  T must be 8b, 16b, 4h, 8h, 2s, 4s, or 2d.
• •  Tf must be 2s, 4s, or 2d.
• •  Td /Ts must be 4h /8b, 8h /16b, 2s /4h, 4s /8h, 1d /2s, or 2d /4s.

10.6.4.2 Operations

10.6.4.3 Examples

10.6.5 Absolute difference

These instructions subtract the elements of one vector from another and store or accumulate the absolute value of the results:

abd Vector integer absolute difference,

fabd Vector floating point absolute difference,

aba Vector integer absolute difference and accumulate,

faba Vector floating point absolute difference and accumulate,

abal Vector absolute difference and accumulate long, and

abdl Vector absolute difference long.

The long versions can be used to prevent overflow.

10.6.5.1 Syntax

• •   is either or .
• •  When a scalar register is specified (F is S or D), a scalar operation is performed instead of a vector operation.
• •  If is present, then the upper 64 bits of the source registers are used.
• •  T must be 8b, 16b, 4h, 8h, 2s, or 4s.
• •  Tf must be 2s, 4s, or 2d.
• •  Td /Ts must be one of 4s /8h, 8h /16b, or 2d /4s.
• •  The valid choices for Td /Ts are given in the following table:

Opcode	Valid Types for Td /Ts
(s|u)<op>l	8h /8b, 4s /4h, 2d /2s
(s|u)<op>l2	8h /16b, 4s /8h, 2d /4s

10.6.5.2 Operations

10.6.5.3 Examples

10.6.6 Absolute value and negate

These operations compute the absolute value or negate each element in a vector:

abs Vector absolute value,

neg Vector negate,

fabs Vector floating point absolute value, and

fneg Vector floating point negate,

The saturating versions can be used to prevent overflow.

10.6.6.1 Syntax

• •   is either or .
• •  T may be 8b, 16b, 4h, 8h, 2s, 4s, or 2d.
• •  Tf may be 2s, 4s, or 2d.

10.6.6.2 Operations

10.6.6.3 Examples

10.6.7 Get maximum or minimum elements

The following four instructions select the maximum or minimum elements and store the results in the destination vector:

max Vector integer maximum,

min Vector integer minimum,

fmax Vector floating point maximum,

fmin Vector floating point minimum,

maxp Vector integer pairwise maximum,

minp Vector integer pairwise minimum,

fmaxp Vector floating point pairwise maximum,

fminp Vector floating point pairwise minimum,

fmaxnm Vector floating point maxnum,

fminnm Vector floating point minnum,

fmaxnmp Vector floating point pairwise maxnum, and

fminnmp Vector floating point pairwise minnum.

10.6.7.1 Syntax

• •   is either or .
• •  T must be 8b, 16b, 4h, 8h, 2s, or 4s.
• •  Tf must be 2s, 4s, or 2d.
• •  If nm is present, then the result is as described in Chapter 9, Section 9.7.5, on page 311.

10.6.7.2 Operations

10.6.7.3 Examples

10.6.8 Count bits

These instructions can be used to count leading sign bits or zeros, or to count the number of bits that are set, for each element in a vector:

cls Vector count leading sign bits,

clz Vector count leading zero bits, and

cnt Vector count set bits.

10.6.8.1 Syntax

• •  T must be 8b, 16b, 4h, 8h, 2s, or 4s.
• •  Tn must be 8b or 16b.

10.6.8.2 Operations

10.6.8.3 Examples

10.6.9 Scalar saturating operations

The following instructions perform basic saturating operations on scalars:

qadd Scalar saturating add,

qsub Scalar saturating subtract,

qdmulh Scalar saturating multiply (high half), and

qshl Scalar saturating shift left.

10.6.9.1 Syntax

• •  F is b, h, s d.
• •  <Fx> is h or s.

10.6.9.2 Operations

10.6.9.3 Examples

10.7.1 Vector multiply and divide

These instructions are used to multiply the corresponding elements from two vectors:

mul Vector integer multiply,

mla Vector integer multiply accumulate,

mls Vector integer multiply subtract,

fmul Vector floating point multiply,

fdiv Vector floating point divide,

fmla Vector floating point multiply accumulate,

fmls Vector floating point multiply subtract,

mull Vector multiply long,

mlal Vector multiply accumulate long,

mlsl Vector multiply subtract long,

pmul Vector polynomial multiply, and

pmull Vector polynomial multiply long.

10.7.1.1 Syntax

• •  T may be 8b, 16b, 4h, 8h, 2s, or 4s.
• •  Tf may be 2s, 4s, or 2d.
• •  T2 may be 8b or 16b.
• •  If x is present, then $0\times \pm \infty \to \pm 2$ (vector).
• •  If 2 is present, then
  1. –  Td /Ts may be 8h /16b, 4s /8h, or 2d /4s.
  2. –  the upper 64 bits of the source vectors are used.
• •  If 2 is not present, then Td /Ts may be 8h /8b, 4s /4h, or 2d /2s.

10.7.1.2 Operations

10.7.1.3 Examples

10.7.2 Multiply vector by element

These instructions are used to multiply each element in a vector by a scalar:

mul Vector by scalar integer multiply,

mla Vector by scalar integer multiply accumulate,

mls Vector by scalar integer multiply subtract,

fmul Vector by scalar floating point multiply,

fmla Vector by scalar floating point multiply accumulate,

fmls Vector by scalar floating point multiply subtract,

mull Vector by scalar multiply long,

mlal Vector by scalar multiply accumulate long, and

mlsl Vector by scalar multiply subtract long.

10.7.2.1 Syntax

• •  <op> is either mul, mla, or mls.
• •  T /Ts must be 4h /h, 8h /h, 2s /s, or 4s /s.
• •  Tf /Ts2 must be 2s /s, 4s /s, or 2d /d.
• •  If x is present, then $0\times \pm \infty \to \pm 2$ (vector).
• •  If 2 is present, then
  1. –  Ta/Tb/Tc is 4s /8h /h or 2d /4s /s.
  2. –  the upper 64 bits of the source vectors are used.
• •  If 2 is not present, then Ta/Tb/Tc is 4s /4h /h or 2d /2s /s.

10.7.2.2 Operations

10.7.2.3 Examples

10.7.3 Saturating vector multiply and double

These instructions perform multiplication, double the results, and perform saturation:

sqdmull Saturating Multiply Double,

sqdmlal Saturating Multiply Double Accumulate, and

sqdmlsl Saturating Multiply Double Subtract.

10.7.3.1 Syntax

• •   is either , , or .
• •  If 2 is present, then Td /Ts is 4s /8h or 2d /4s and the upper half of Vn and Vm are used. Otherwise, Td /Ts is 4s /4h or 2d /2s and the lower half of Vn and Vm are used.
• •  If 2 is present, then Td /Ta /Tb is 4s /8h /h or 2d /4s /s, and the upper half of Vn is used. Otherwise Td /Ta /Tb is 4s /4h /h or 2d /4s /s, and the lower half of Vn is used.
• •  If the third operand is a scalar ( is specified) and Tb is h, then Vm must be in the range .

10.7.3.2 Operations

10.7.3.3 Examples

10.7.4 Saturating multiply and double (high)

These instructions perform multiplication, double the results, perform saturation, and store the high half of the results:

sqdmulh Saturating Multiply Double (High), and

sqrdmulh Saturating Multiply Double and Round (High).

10.7.4.1 Syntax

• •  T must be 4h, 8h, 2s, or 4s.
• •  Td /Ts must be 4h /h, 8h /h, 2s /s, or 4s /s.
• •  If Ts is h, then Vm must be in the range .

10.7.4.2 Operations

10.7.4.3 Examples

10.7.5 Estimate reciprocals

In general, multiplication is faster than division. In many cases of vector arithmetic, it is faster to calculate reciprocals and use multiplication. These instructions perform the initial estimates of the reciprocal values:

recpe Reciprocal Estimate, and

rsqrte Reciprocal Square Root Estimate.

These work on floating point and unsigned fixed point vectors. The estimates from this instruction are accurate to within about eight bits. If higher accuracy is desired, then the Newton-Raphson method can be used to improve the initial estimates. For more information, see the Reciprocal Step instructions on page 369.

10.7.5.1 Syntax

• •   is either or .
• •  Ta must be 2s or 4s.
• •  Tb must be 2s, 4s, or 2d.

10.7.5.2 Operations

10.7.5.3 Examples

10.7.6 Reciprocal step

These instructions are used to perform one Newton-Raphson step for improving the reciprocal estimates:

frecps Reciprocal Step, and

frsqrts Reciprocal Square Root Step.

For each element in the vector, the following equation can be used to improve the estimates of the reciprocals:

$x_{n+1}=x_n(2-d{x}_n).$

Where $x_n$ is the estimated reciprocal from the previous step, and d is the number for which the reciprocal is desired. This equation converges to $\frac{1}{d}$ if $x_0$ is obtained using on d. The instruction computes

$x_{n+1}^{\prime }=2-d{x}_n,$

so one additional multiplication is required to complete the update step. The initial estimate $x_0$ must be obtained using the instruction.

For each element in the vector, the following equation can be used to improve the estimates of the reciprocals of the square roots:

$x_{n+1}=x_n\frac{3-d{x}_n^2}{2}.$

Where $x_n$ is the estimated reciprocal from the previous step, and d is the number for which the reciprocal is desired. This equation converges to $\frac{1}{\sqrt{d}}$ if $x_0$ is obtained using on d. The instruction computes

$x_{n+1}^{\prime }=\frac{3-d{x}_n}{2},$

so two additional multiplications are required to complete the update step. The initial estimate $x_0$ must be obtained using the instruction.

10.7.6.1 Syntax

• •   is either or .
• •  T must be 2s, 4s, or 2d.
• •  F is s or d.

10.7.6.2 Operations

10.7.6.3 Examples

10.7.7 Multiply scalar by element

These instructions are used to multiply each element in a vector by a scalar:

fmul Vector by scalar floating point multiply,

fmla Vector by scalar floating point multiply accumulate,

fmls Vector by scalar floating point multiply subtract.

10.7.7.1 Syntax

• •  Ts must be s or d.
• •  If Ts is s, then Vm must be in the range s0 to s15.
• •  If x is present, then $0\times \pm \infty \to \pm 2$ (vector).

10.7.7.2 Operations

10.7.7.3 Examples

10.7.8 Saturating multiply scalar by element and double

These instructions perform multiplication, double the results, and perform saturation:

sqdmull Saturating Multiply Scalar by Element and Double,

sqdmlal Saturating Multiply Scalar by Element, Double, and Accumulate, and

sqdmlsl Saturating Multiply Scalar by Element, Double, and Subtract.

10.7.8.1 Syntax

• •   is either , , or .
• •  Fd /Fn /Ts must be s /h /h or d /s /s.
• •  If Ts is h, then Vm must be in the range .
• •  F /Tc must be h /h or s /s.
• •  If Tc is h, then Vc must be in the range .

10.7.8.2 Operations

10.7.8.3 Examples

10.8.1 Vector shift left by immediate

These instructions shift each element in a vector left by an immediate value:

shl Unsigned Shift Left Immediate,

qshl Saturating Signed or Unsigned Shift Left Immediate,

sqshlu Saturating Signed Shift Left Immediate Unsigned, and

shll Signed or Unsigned Shift Left Immediate Long.

Overflow conditions can be avoided by using the saturating version, or by using the long version, in which case the destination is twice the size of the source.

10.8.1.1 Syntax

• •   is an alias for .
• •   is an alias for .
• •   is an alias for .
• •   is an alias for .
• •  T is 8b, 16b, 4h, 8h, 2s, 4s, or 2d.
• •  If 2 is present, then Td /Ts is 8h /16b, 4s /8h, or 2d /4s.
• •  If 2 is not present, then Td /Ts is 8h /8b, 4s /4h, or 2d /2s.
• •  shift is in the range 0 to $size(\mathtt{\text{T}})-1$.
• •  If the instruction begins with , then the elements are treated as unsigned integers.
• •  If is present, then the elements are treated as signed integers.

10.8.1.2 Operations

10.8.1.3 Examples

10.8.2 Vector shift right by immediate

These instructions shift each element in a vector right by an immediate value:

shr Shift Right Immediate,

rshr Shift Right Immediate and Round,

shrn Shift Right Immediate and Narrow,

rshrn Shift Right Immediate Round and Narrow,

sra Shift Right and Accumulate Immediate, and

rsra Shift Right Round and Accumulate Immediate.

10.8.2.1 Syntax

• •  T is 8b, 16b, 4h, 8h, 2s, 4s, or 2d.
• •  If 2 is present, then Td /Ts is 16b /8h, 8h /4s, or 4s /2d.
• •  If 2 is not present, then Td /Ts is 8h /8b, 4s /4h, or 2d /2s.
• •  shift is in the range 0 to $size(\mathtt{\text{T}})-1$ (or $size(\mathtt{\text{Td}})-1$).

10.8.2.2 Operations

10.8.2.3 Examples

10.8.3 Vector saturating shift right by immediate

These instructions shift each element in a quad word vector right by an immediate value:

qshrn Saturating Shift Right Narrow,

qrshrn Saturating Rounding Shift Right Narrow,

sqshrun Signed Saturating Shift Right Unsigned Narrow, and

sqrshrun Signed Saturating Rounding Shift Right Unsigned Immediate.

10.8.3.1 Syntax

• •  If is present, the Td /Ts is 16b /8h, 8h /4s, or 4s /2d
• •  If is not present, the Td /Ts is 8b /8h, 4h /4s, or 2s /2d to elsize(Td ).
• •  shift is in the range 1 to $size(\mathtt{\text{Td}})$.

10.8.3.2 Operations

10.8.3.3 Examples

10.8.4 Shift left or right by variable

These instructions shift each element in a vector left or right, using the least significant byte of the corresponding element of a second vector as the shift amount:

shl Shift Left or Right by Variable,

rshl Shift Left or Right by Variable and Round,

qshl Saturating Shift Left or Right by Variable, and

qrshl Saturating Shift Left or Right by Variable and Round.

10.8.4.1 Syntax

• •  T is 8b, 16b, 4h, 8h, 2s, 4s, or 2d.
• •  If double precision register s are specified (Dd, Dn, Dm ), then the operation is a scalar operation instead of a vector operation.
• •  If the shift value is positive, the operation is a left shift.
• •  If shift value is negative, then it is a right shift.
• •  A shift value of zero is equivalent to a move.
• •  If the operation is a right shift, and is specified, then the result is rounded rather than truncated.
• •  Results are saturated if is specified.
• •  If is present, then the results are saturated.
• •  If is present, then right shifted values are rounded rather than truncated.

10.8.4.2 Operations

10.8.4.3 Examples

10.8.5 Shift and insert

These instructions perform bitwise shifting of each element in a vector, then combine bits from the source with bits from the destination. Fig. 10.7 provides an example. The instructions are:

sli Shift Left and Insert, and

sri Shift Right and Insert.

10.8.5.1 Syntax

• •  T is 8b, 16b, 4h, 8h, 2s, 4s, or 2d.
• •   must be l for a left shift, or r for a right shift.
• •   is the amount that elements are to be shifted, and must be between zero and $size(\mathtt{\text{T}})-1$ for , or between one and $size(\mathtt{\text{T}})$ for .

10.8.5.2 Operations

10.8.5.3 Examples

10.8.6 Scalar shift left by immediate

These instructions shift each element in a vector left by an immediate value:

shl Unsigned Shift Left Immediate,

qshl Saturating Signed or Unsigned Shift Left Immediate,

sqshlu Saturating Signed Shift Left Immediate Unsigned, and

shll Signed or Unsigned Shift Left Immediate Long.

Overflow conditions can be avoided by using the saturating version, or by using the long version, in which case the destination is twice the size of the source.

10.8.6.1 Syntax

• •  F may be b, h, s, or d.
• •  If the instruction begins with , then the scalars are treated as unsigned integers.
• •  If is present, then the scalars are treated as signed integers.

10.8.6.2 Operations

10.8.6.3 Examples

10.8.7 Scalar shift right by immediate

These instructions shift each element in a vector right by an immediate value:

shr Shift Right Immediate,

rshr Shift Right Immediate and Round,

sra Shift Right and Accumulate Immediate, and

rsra Shift Right Round and Accumulate Immediate.

10.8.7.1 Syntax

• •  shift is in the range 0 to $size(\mathtt{\text{T}})-1$ (or $size(\mathtt{\text{Td}})-1$).

10.8.7.2 Operations

10.8.7.3 Examples

10.8.8 Scalar saturating shift right by immediate

These instructions shift each element in a quad word vector right by an immediate value:

qshrn Saturating Shift Right Narrow,

qrshrn Saturating Rounding Shift Right Narrow,

sqshrun Signed Saturating Shift Right Unsigned Narrow, and

sqrshrun Signed Saturating Rounding Shift Right Unsigned Immediate.

10.8.8.1 Syntax

• •  <Fd>/<Fn> must be b /h, h /s, or s /d.

10.8.8.2 Operations

10.8.8.3 Examples

10.9.1 Vector unary arithmetic

not Vector 1's Complement,

qadd Vector Saturating Accumulate,

fsqrt Vector Floating Point Square Root,

rbit Vector bit reverse,

rev Reverse Elements.

10.9.1.1 Syntax

• •  T is 8b or 16b.
• •  Ta is 8b, 16b, 4h, 8h, 2s, 4s, or 2d.
• •  Tb is 2s, 4s, or 2d.
• •  Tc is 8b, 16b, 4h, or 8h.
• •  Td is 8b, 16b, 4h, 8h, 2s, or 4s.

10.9.1.2 Operations

10.9.1.3 Examples

Fig. 10.8 provides some illustrated examples of the instructions.

10.9.2 Scalar unary arithmetic

abs Integer absolute value,

neg Integer absolute value,

qadd Vector Saturating Accumulate,

fsqrt Vector Floating Point Square Root,

rbit Vector bit reverse, and

rev Reverse Elements.

10.9.2.1 Syntax

• •  F is b, h, s, or d.

10.9.2.2 Operations

10.9.2.3 Examples

10.10.1 Reduce across lanes

Advanced SIMD provides instructions for summing the elements in a vector, and for getting the maximum or minimum value from a vector. These instructions are:

addv Integer Sum Elements to Scalar,

maxv Integer Maximum Element to Scalar,

minv Integer Minimum Element to Scalar,

fmaxv Floating Point Maximum Element to Scalar, and

fminv Floating Point Minimum Element to Scalar.

There are long versions of the instruction which will prevent overflow.

10.10.1.1 Syntax

• •  F /T may be b /8b, b /16b, h /4h, h /8h, s /2s, or s /4s.
• •  Fa /Tn may be h /8b, h /16b, s /4h, s /8h, d /2s, or d /4s.
• •  If nm is present, then comparison between a nan and a numerical value will return the numerical value.

10.10.1.2 Operations

10.10.1.3 Examples

10.10.2 Reduce pairwise

The pairwise instructions are similar to the vector reduce instructions, but always operate on two elements of the source vector. These instructions are:

addp Integer Sum Elements to Scalar,

faddp Integer Maximum Element to Scalar,

fmaxp Floating Point Maximum Element to Scalar, and

fminp Floating Point Minimum Element to Scalar.

There are long versions of the instruction which will prevent overflow.

10.10.2.1 Syntax

• •  F /T must be either s /2s or d /2d.
• •  If nm is present, then comparison between a nan and a numerical value will return the numerical value.

10.10.2.2 Operations

10.10.2.3 Examples

10.11.1 Vector compare mask

The following instructions perform comparisons of all of the corresponding elements of two vectors in parallel:

cm Vector integer compare mask, and

fcm Vector floating point compare mask.

10.11.1.1 Syntax

• •  <op> is one of eq, hs, ge, hi, gt, ls, le, lo, or lt.
• •  <op2> is one of eq, ge, gt, le, or lt.
• •  T is 8b, 16b, 4h, 8h, 2s, 4s, or 2d.
• •  Tf is 2s, 4s, or 2d.
• •  If the third operand is , then it is treated as a vector of the correct size in which every element is zero.
• •   can be or .

10.11.1.2 Operations

10.11.1.3 Examples

10.11.2 Vector absolute compare mask

The following instruction performs comparisons between the absolute values of all of the corresponding elements of two vectors in parallel:

fac Vector floating point absolute compare mask.

10.11.2.1 Syntax

• •  <op> is one of ge, gt, le, or lt.
• •  T is 2s, 4s, or 2d.

10.11.2.2 Operations

10.11.2.3 Examples

10.11.3 Vector test bits mask

Advanced SIMD provides the following vector version of the ARM instruction:

cmtst Vector test bits compare mask.

10.11.3.1 Syntax

• •  T is 8b, 16b, 4h, 8h, 2s, 4s, or 2d.

10.11.3.2 Operations

10.11.3.3 Examples

10.11.4 Scalar compare mask

The following instructions perform comparisons of the specified scalar registers:

cm Scalar integer compare mask, and

fcm Scalar floating point compare mask,

If the comparison is true, then all bits in the destination register are set to one. Otherwise, all bits in the destination register are set to zero.

10.11.4.1 Syntax

• •  The integer comparison can only operate on 64-bit integers.
• •  F can be either s for single precision, or d for double precision floating point.
• •  <op> is one of eq, hs, ge, hi, gt, ls, le, lo, or lt.
• •  <op2> is one of eq, ge, gt, le, or lt.

10.11.4.2 Operations

10.11.4.3 Examples

10.11.5 Scalar absolute compare mask

The following instruction performs comparisons between the absolute values of two scalars:

fac Scalar floating point absolute compare mask.

10.11.5.1 Syntax

• •  <op> is one of ge, gt, le, or lt.
• •  T is 2s, 4s, or 2d.

10.11.5.2 Operations

10.11.5.3 Examples

10.11.6 Scalar test bits mask

The scalar test bits instruction performs a logical AND operation between two source registers. If the result is not zero, then every bit in the result register is set to one. Otherwise, every bit in the result register is set to zero. The instruction is:

cmtst Scalar test bits compare mask.

10.11.6.1 Syntax

• •  Only 64-bit comparisons can be performed.

10.11.6.2 Operations

10.11.6.3 Examples

10.12.1 Single precision

Listing 10.1 shows a single precision floating point implementation of the sine function, using Advanced SIMD vector instructions. It performs the same operations as the previous implementations of the sine function, but performs many of the calculations in parallel. This implementation is slightly faster than the previous version. In addition to being faster, it also uses nine terms of the Taylor series, so it should be more accurate as well.

10.12.2 Double precision

Listing 10.2 shows a double precision floating point implementation of the sine function. It also uses Advanced SIMD vector instructions. Both of the implementations in this chapter are faster than the corresponding implementations in Chapter 9 because they use a large number of registers, do not contain loops, and are written carefully to use vector instructions, ordered so that multiple instructions can be at different stages in the pipeline at the same time. This technique of gaining performance is known as loop unrolling. In addition to being faster, the vector implementations use more terms of the Taylor series, so they may also be more accurate.

10.12.3 Performance comparison

Table 10.1 compares the implementations from Listing 10.1 and Listing 10.2 with the FP/NEON implementations from Chapter 9 and the sine function provided by GCC. When compiler optimization is not used, the single precision scalar FP/NEON implementation achieves a speedup of about 3.41, and the Advanced SIMD implementation achieves a speedup of about 4.21 compared to the GCC implementation. The double precision scalar FP/NEON implementation achieves a speedup of about 2.22, and the Advanced SIMD achieves a speedup of about 2.41 compared to the GCC implementation.

When the compiler optimization is used (-Ofast), the single precision scalar FP/NEON implementation achieves a speedup of about 3.04, and the Advanced SIMD implementation achieves a speedup of about 3.86 compared to the GCC implementation. The double precision scalar FP/NEON implementation achieves a speedup of about 2.70, and the Advanced SIMD implementation achieves a speedup of about 2.97 compared to the GCC implementation. The single precision Advanced SIMD version was 1.27 times as fast as the FP/NEON scalar version, and the double precision Advanced SIMD implementation was 1.10 times as fast as the FP/NEON scalar implementation.

Although the FP/NEON versions of the sine functions were already much faster than the C standard library, re-writing them using Advanced SIMD resulted in further performance improvement. The take-away lesson is that a programmer can improve performance by writing some functions in assembly that are specifically targeted to run on a specific platform. To achieve optimal or near-optimal performance, it is important for the programmer to be aware of advanced features available on the hardware platform that is being used.