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by Ronald W. Mehler
Digital Integrated Circuit Design Using Verilog and Systemverilog
Cover
Title page
Table of Contents
Copyright Page
About the author
Preface
Acknowledgments
Chapter 1: Introduction
Abstract
Who should read this book
Hardware description languages and methodology
What this book covers
Historical perspective
Verilog and Systemverilog
Book organization
Chapter 2: Bottom-up design
Abstract
Primitive instantiation
Designing with primitives
Identifiers and escaped identifiers
Bus declarations
Design hierarchy and test fixtures
Port association
Timescales
Summary
Chapter 3: Behavioral coding part I: blocks, variables, and operators
Abstract
Top-down design
Synthesizable and nonsynthesizable code
Register Transfer Level (RTL)
Continuous assignments
Implicit continuous assignments
Functional blocks: always and initial
Named blocks
Sensitivity lists
Splitting assignments
Variables
Operators
Summary
Chapter 4: Behavioral coding part II: defines, parameters, enumerated types, and packages
Abstract
Global definitions
Parameters
Overriding default values
Local parameters
Specify parameters
Enumerated types
Constants
Packages
Filling a scalable variable with all ones
Summary
Chapter 5: Behavioral coding part III: loops and branches
Abstract
Loops
Case statements
Latch generation
Unique and priority
Summary
Chapter 6: Subroutines and interfaces
Abstract
Subroutines
Tasks
Functions
Parameters in subroutines
Managing subroutines
Interfaces
Interface modports
Summary
Chapter 7: Synchronization
Abstract
Latch instability
Flipflops, latches, and violations
Asynchronous assert, synchronous deassert
Slow-speed single-bit clocked asynchronous interfaces
High-speed single-bit clocked asynchronous interfaces
Multiple high-speed single-bit clocked asynchronous interfaces
Asynchronous parallel buses
High-speed asynchronous serial links
Summary
Chapter 8: Simulation, timing, and race conditions
Abstract
Simulation queues
Race conditions
Derived clocks and delta time
Assertions
Summary
Chapter 9: Architectural choices
Abstract
FPGA versus ASIC
Design reuse
Partitioning
Area and speed optimization
Power optimization
Summary
Chapter 10: Design for testability
Abstract
Yield, testing, and defect level
Fault modeling
Activation and sensitization
Logic scan
Boundary scan
Built in self-test
Parametric testing
Summary
Chapter 11: Library modeling
Abstract
Component libraries
Cell models
User-defined primitives
Combinational cells
Sequential cells
Model performance
Summary
Chapter 12: Design examples
Abstract
State machine
FIR filters
FIFO
DMX receiver
Appendix A: SystemVerilog keywords
Appendix B: Standard combinational and sequential functions
Appendix C: Number systems
Index
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