IBM Integrated Accelerator for zEnterprise Data Compression
This appendix describes the new IBM Integrated Accelerator for z Enterprise Data Compression (zEDC) that is implemented in IBM z15 hardware.
The appendix includes the following topics:
Client value of Z compression
The amount of data that is captured, transferred, and stored continues to grow. Software-based compression algorithms can be costly in terms of processor resources, storage costs, and network bandwidth.
An optional feature that is available for z14, z13, and z13s servers, zEDC Express addressed customer requirements by providing hardware-based acceleration for data compression and decompression. zEDC provided data compression with lower CPU consumption than compression technology that was available on the IBM Z server.
Existing clients deployed zEDC compression to deliver the following types of compression:
•Storage
•Data transfer
•Database
•In-application
Data compression delivers the following benefits:
•Disk space savings
•Improved elapse times
•Reduced CPU consumption
•Reduced network bandwidth requirements and transfer times
Many clients are increasing their zEDC footprint to 8GBps with up to 16 features per z14 system at 1 GBps throughput per feature (redundancy reduces total throughput to 8 GBps).
The z15 further addresses the growth of data compression requirements with the integrated on-chip compression unit (implemented in processor Nest, one per PU chip) that significantly increases compression throughput and speed compared to zEDC deployments.
z15 IBM Integrated Accelerator for zEDC
z15 on-chip compression provides value for existing and new compression users by bringing the compression facility into the PU chip, which is tied in L3 cache.
The z15 Integrated Accelerator for zEDC delivers industry-leading throughput and replaces the zEDC Express PCIe adapter that is available on the IBM z14 and earlier servers.
z15 compression/decompression is implemented in the Nest Accelerator Unit (NXU, see Figure 3-10 on page 106) on each processor chip and replaces the existing zEDC Express adapter in the PCIe+ I/O drawer.
One Nest Accelerator Unit is available per processor chip, which is shared by all cores on the chip and features the following benefits:
•New concept of sharing and operating an accelerator function in the nest
•Supports DEFLATE compliant compression/decompression and GZIP CRC/ZLIB Adler
•Low latency
•High bandwidth
•Problem state execution
•Hardware and firmware interlocks to ensure system responsiveness
•Designed instruction
•Run in millicode
Based on IBM benchmarks, the throughput for each On-Chip Compression unit is 12 GBps, which equates to 48 GBps per drawer or 240 GBps for a fully populated five-drawer z15.
On-Chip Compression provides an up to 5% improvement in compression ratios for BSAM/VSAM datasets over zEDC while maintaining full compatibility.
Eliminating adapter sharing by using Nest Compression Accelerator
Sharing of zEDC cards is limited to 15 LPAR guests per adaptor. The Nest Compression Accelerator removes this virtualization constraint because it is shared by all PUs on the processor chip and therefore is available to all LPARs and guests.
Moving the compression function from the (PCIe) I/O drawer to the processor chip means that compression can operate directly in L3 cache and data does not need to be passed by using I/O operations.
Compression modes
Compression is run in one of the following modes:
•Synchronous
Execution occurs in problem state where the user application starts the instruction in its virtual address space.
•Asynchronous
Execution is optimized for Large Operations under z/OS for authorized applications (for example, BSAM) and issues I/O by using EADMF for asynchronous execution.
This type of execution maintains the current user experience and provides a transparent implementation for authorized users of zEDC.
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Note: The zEDC Express feature does not carry forward to z15.
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z15 migration considerations
The IBM Integrated Accelerator for zEDC is fully compatible with zEDC. Data compressed by zEDC can be read by z15 (the on-chip) nest accelerator unit and vice versa.
All z/OS configuration stay the same
No changes are required when moving from earlier systems using zEDC to z15.
The IFAPRDxx feature is still required for authorized services. For problem state services, such as zlib usage of Java, it is not required.
Consider fail-over and DR sizing
The order of magnitude throughput increase on z15 means that the throughput requirements need to be considered whether failing over to earlier systems with zEDC.
Performance metrics
On-chip compression introduces the following system reporting changes:
•No RMF PCIE reporting for zEDC
•Synchronous executions are not recorded (just an instruction invocation)
•Asynchronous executions are recorded:
– SMF30 information is captured for asynchronous usage
– RMF EADM reporting is enhanced (RMF 74.10)
– SAP utilization is updated to include time spent compressing and decompressing
zEDC to z15 zlib Program Flow for z/OS
The z/OS provided zlib library is statically linked into many IBM and ISV products and remains functional. However, to get the best optimization for z15, some minor changes are made to zlib.
The current zlib and the new zlib function on z14 and earlier servers and z15 hardware. It functions with or without the z15 z/OS PTFs on z14 and earlier servers.
Software support
Support of the On-Chip Compression function is compatible with zEDC support and is available in z/OS V2R1 or later for data compression and decompression. Support for data recovery (decompression) in the case that zEDC or On-Chip Compression not available; however, it is provided through software in z/OS V2R2, and V2R1 with the appropriate program temporary fixes (PTFs).
Software decompression is slow and can involve considerable processor resources. Therefore, it is not recommended for production environments.
A specific fix category that is named IBM.Function.zEDC identifies the fixes that enable or use the zEDC and On-Chip Compression function.
z/OS guests that run under z/VM V6.4 with PTFs and later can use the zEDC Express feature and z15 On-Chip Compression.
For more information, see the Enhancements to z/VM 6.4 page of the IBM Systems website.
IBM 31-bit and 64-bit SDK for z/OS Java Technology Edition, Version 7 Release 1 (5655-W43 and 5655-W44) (IBM SDK 7 for z/OS Java) now provides use of the zEDC Express feature and Shared Memory Communications-Remote Direct Memory Access (SMC-R), which is used by the 10GbE RoCE Express feature.
For more information about how to implement and use the IBM Z compression features, see Reduce Storage Occupancy and Increase Operations Efficiency with IBM zEnterprise Data Compression, SG24-8259.
C.0.1 IBM Z Batch Network Analyzer
IBM Z Batch Network Analyzer (zBNA) is a no-charge, “as is” tool. It is available to clients, IBM Business Partners, and IBM employees.
zBNA is based on Microsoft Windows, and provides graphical and text reports, including Gantt charts, and support for alternative processors.
zBNA can be used to analyze client-provided System Management Facilities (SMF) records to identify jobs and data sets that are candidates for zEDC and z15 On-Chip Compression across a specified time window (often a batch window).
zBNA can generate lists of data sets by the following jobs:
•Jobs that perform hardware compression and might be candidates for On-Chip Compression.
•Jobs that might be On-Chip Compression candidates, but are not in extended format.
Therefore, zBNA can help you estimate the use of On-Chip Compression features and help identify savings. The following resources are available:
•IBM Employees can obtain zBNA and other CPS tools at the IBM Z Batch Network Analyzer (zBNA) Tool page of the IBM Techdoc website.
•IBM Business Partners can obtain zBNA and other CPS tools at the IBM PartnerWorld website (log in required).
•IBM clients can obtain zBNA and other CPS tools at the IBM Z Batch Network Analyzer (zBNA) Tool page of the IBM Techdoc Library website.
Compression acceleration and Linux on Z
The zEDC I/O adapter use is limited in many Linux on Z environments because SR-IOV does not provide a high degree of virtualization; therefore, the user must pick and choose which guests are granted access to the accelerator.
The z15 On-Chip Compression accelerator solves these virtualization limitations because the function is no longer an I/O device and is available as a problem state instruction to all Linux on Z guests without constraints.
This feature enables pervasive usage in highly virtualized environments.
z15 On-Chip Compression is available to open source applications by way of zlib.
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