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IBM z15 (8561) Technical Guide
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IBM z15 (8561) Technical Guide
by Bo XU, Hervey Kamga, Anna Shugol, Kazuhiro Nakajima, Paul Schouten, Frank Packhe
IBM z15 (8561) Technical Guide
Front cover
Notices
Trademarks
Preface
Authors
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Chapter 1. Introduction
1.1 Design considerations for the IBM z15
1.1.1 Complementing and augmenting cloud solutions
1.1.2 Compliance, resiliency, and performance
1.1.3 Pervasive encryption
1.1.4 IBM Z Data Privacy Passports
1.1.5 Blending open source with IBM Z state-of-the-art technologies
1.2 z15 server highlights
1.2.1 Processor and memory
1.2.2 Capacity and performance
1.2.3 Virtualization
1.2.4 I/O subsystem and I/O features
1.2.5 Reliability, availability, and serviceability design
1.3 z15 server technical overview
1.3.1 Model and features
1.3.2 Model upgrade paths
1.3.3 Frames
1.3.4 CPC drawer
1.3.5 I/O connectivity: PCIe+ Generation 3
1.3.6 I/O subsystem
1.3.7 I/O and special purpose features in the PCIe I/O drawer
1.3.8 Storage connectivity
1.3.9 Network connectivity
1.3.10 Coupling and Server Time Protocol connectivity
1.3.11 Cryptography
1.4 Reliability, availability, and serviceability
1.5 Hardware Management Consoles and Support Elements
1.6 Operating systems
1.6.1 Supported operating systems
1.6.2 IBM compilers
Chapter 2. Central processor complex hardware components
2.1 Frames and configurations
2.1.1 z15 cover (door) design
2.1.2 Top exit I/O and cabling
2.2 CPC drawer
2.2.1 CPC drawer interconnect topology
2.2.2 Oscillator
2.2.3 System control
2.2.4 CPC drawer power
2.3 Single chip modules
2.3.1 Processor unit chip
2.3.2 Processor unit (core)
2.3.3 PU characterization
2.3.4 System Controller chip
2.3.5 Cache level structure
2.4 PCIe+ I/O drawer
2.5 Memory
2.5.1 Memory subsystem topology
2.5.2 Redundant array of independent memory
2.5.3 Memory configurations
2.5.4 Memory upgrades
2.5.5 Drawer replacement and memory
2.5.6 Virtual Flash Memory
2.5.7 Flexible Memory Option
2.6 Reliability, availability, and serviceability
2.6.1 RAS in the CPC memory subsystem
2.6.2 General z15 RAS features
2.7 Connectivity
2.7.1 Redundant I/O interconnect
2.7.2 Enhanced drawer availability (EDA)
2.7.3 CPC drawer upgrade
2.8 Model configurations
2.8.1 Upgrades
2.8.2 Model capacity identifier
2.9 Power and cooling
2.9.1 PDU-based configurations
2.9.2 BPA-based configurations
2.9.3 Internal Battery Feature
2.9.4 Power estimation tool
2.9.5 Cooling
2.9.6 Radiator Cooling Unit
2.9.7 Water-cooling unit
2.10 Summary
Chapter 3. Central processor complex design
3.1 Overview
3.2 Design highlights
3.3 CPC drawer design
3.3.1 Cache levels and memory structure
3.3.2 CPC drawer interconnect topology
3.4 Processor unit design
3.4.1 Simultaneous multithreading
3.4.2 Single-instruction multiple-data
3.4.3 Out-of-Order execution
3.4.4 Superscalar processor
3.4.5 Compression and cryptography accelerators on a chip
3.4.6 Decimal floating point accelerator
3.4.7 IEEE floating point
3.4.8 Processor error detection and recovery
3.4.9 Branch prediction
3.4.10 Wild branch
3.4.11 Translation lookaside buffer
3.4.12 Instruction fetching, decoding, and grouping
3.4.13 Extended Translation Facility
3.4.14 Instruction set extensions
3.4.15 Transactional Execution
3.4.16 Runtime Instrumentation
3.5 Processor unit functions
3.5.1 Overview
3.5.2 Central processors
3.5.3 Integrated Facility for Linux (FC 1945)
3.5.4 Internal Coupling Facility (FC 1946)
3.5.5 IBM Z Integrated Information Processor (FC 1947)
3.5.6 System assist processors
3.5.7 Reserved processors
3.5.8 Integrated firmware processor
3.5.9 Processor unit assignment
3.5.10 Sparing rules
3.5.11 CPC drawer numbering
3.6 Memory design
3.6.1 Overview
3.6.2 Main storage
3.6.3 Hardware system area
3.6.4 Virtual Flash Memory (FC 0643)
3.7 Logical partitioning
3.7.1 Overview
3.7.2 Storage operations
3.7.3 Reserved storage
3.7.4 Logical partition storage granularity
3.7.5 LPAR dynamic storage reconfiguration
3.8 Intelligent Resource Director
3.9 Clustering technology
3.9.1 CF Control Code
3.9.2 Coupling Thin Interrupts
3.9.3 Dynamic CF dispatching
3.10 Virtual Flash Memory
3.10.1 IBM Z Virtual Flash Memory overview
3.10.2 VFM feature
3.10.3 VFM administration
3.11 Secure Service Container
Chapter 4. Central processor complex I/O structure
4.1 Introduction to I/O infrastructure
4.1.1 I/O infrastructure
4.1.2 PCIe Generation 3
4.2 I/O system overview
4.2.1 Characteristics
4.2.2 Supported I/O features
4.3 PCIe+ I/O drawer
4.3.1 PCIe+ I/O drawer offerings
4.4 CPC drawer fanouts
4.4.1 PCIe+ Generation 3 fanout (FC 0175)
4.4.2 Integrated Coupling Adapter (FC 0172 and 0176)
4.4.3 Fanout considerations
4.5 I/O features
4.5.1 I/O feature card ordering information
4.5.2 Physical channel ID report
4.6 Connectivity
4.6.1 I/O feature support and configuration rules
4.6.2 Storage connectivity
4.6.3 Network connectivity
4.6.4 Parallel Sysplex connectivity
4.7 Cryptographic functions
4.7.1 CPACF functions (FC 3863)
4.7.2 Crypto Express7S feature (FC 0898 and FC 0899)
4.7.3 Crypto Express6S feature (FC 0893) as carry forward only
4.7.4 Crypto Express5S feature (FC 0890) as carry forward only
4.8 Integrated Firmware Processor
Chapter 5. Central processor complex channel subsystem
5.1 Channel subsystem
5.1.1 Multiple logical channel subsystems
5.1.2 Multiple subchannel sets
5.1.3 Channel path spanning
5.2 I/O configuration management
5.3 Channel subsystem summary
Chapter 6. Cryptographic features
6.1 Cryptography enhancements on IBM z15
6.2 Cryptography overview
6.2.1 Modern cryptography
6.2.2 Kerckhoffs’ principle
6.2.3 Keys
6.2.4 Algorithms
6.3 Cryptography on IBM z15
6.4 CP Assist for Cryptographic Functions
6.4.1 Cryptographic synchronous functions
6.4.2 CPACF protected key
6.5 Crypto Express7S
6.5.1 Cryptographic asynchronous functions
6.5.2 Crypto Express7S as a CCA coprocessor
6.5.3 Crypto Express7S as an EP11 coprocessor
6.5.4 Crypto Express7S as an accelerator
6.5.5 Managing Crypto Express7S
6.6 Trusted Key Entry workstation
6.6.1 Logical partition, TKE host, and TKE target
6.6.2 Optional smart card reader
6.6.3 TKE hardware support and migration information
6.7 Cryptographic functions comparison
6.8 Cryptographic operating system support for z15
6.8.1 Crypto Express7S Toleration
6.8.2 Crypto Express7S support of VFPE
6.8.3 Crypto Express7S support of greater than 16 domains
Chapter 7. Operating system support
7.1 Operating systems summary
7.2 Support by operating system
7.2.1 z/OS
7.2.2 z/VM
7.2.3 z/VSE
7.2.4 z/TPF
7.2.5 Linux on IBM Z (Linux on Z)
7.2.6 KVM hypervisor
7.3 z15 features and function support overview
7.3.1 Supported CPC functions
7.3.2 Coupling and clustering
7.3.3 Network connectivity
7.3.4 Cryptographic functions
7.4 Support by features and functions
7.4.1 LPAR Configuration and Management
7.4.2 Base CPC features and functions
7.4.3 Coupling and clustering features and functions
7.4.4 Storage connectivity-related features and functions
7.4.5 Networking features and functions
7.4.6 Cryptography Features and Functions Support
7.5 z/OS migration considerations
7.5.1 General guidelines
7.5.2 Hardware Fix Categories (FIXCATs)
7.5.3 Coupling links
7.5.4 z/OS XL C/C++ considerations
7.5.5 z/OS V2.3
7.5.6 z/OS V2.4
7.6 z/VM migration considerations
7.6.1 z/VM 7.1
7.6.2 z/VM V6.4
7.6.3 ESA/390-compatibility mode for guests
7.6.4 Capacity
7.7 z/VSE migration considerations
7.8 Software licensing
7.9 References
Chapter 8. System upgrades
8.1 Permanent and Temporary Upgrades
8.1.1 Overview
8.1.2 CoD for z15 systems-related terminology
8.1.3 Concurrent and nondisruptive upgrades
8.1.4 Permanent upgrades
8.1.5 Temporary upgrades
8.2 Concurrent upgrades
8.2.1 PU Capacity feature upgrades
8.2.2 Customer Initiated Upgrade facility
8.2.3 Concurrent upgrade functions summary
8.3 Miscellaneous equipment specification upgrades
8.3.1 MES upgrade for processors
8.3.2 MES upgrades for memory
8.3.3 MES upgrades for I/O
8.3.4 Feature on Demand
8.3.5 Summary of plan-ahead feature
8.4 Permanent upgrade by using the CIU facility
8.4.1 Ordering
8.4.2 Retrieval and activation
8.5 On/Off Capacity on Demand
8.5.1 Overview
8.5.2 Capacity Provisioning Manager
8.5.3 Ordering
8.5.4 On/Off CoD testing
8.5.5 Activation and deactivation
8.5.6 Termination
8.6 z/OS Capacity Provisioning
8.7 System Recovery Boost Upgrade
8.8 Capacity for Planned Event
8.9 Capacity Backup
8.9.1 Ordering
8.9.2 CBU activation and deactivation
8.9.3 Automatic CBU enablement for GDPS
8.10 Planning for nondisruptive upgrades
8.10.1 Components
8.10.2 Concurrent upgrade considerations
8.11 Summary of Capacity on-Demand offerings
Chapter 9. Reliability, availability, and serviceability
9.1 RAS strategy
9.2 Technology
9.2.1 Processor Unit chip
9.2.2 System Controller and main memory
9.2.3 I/O and service
9.3 Structure
9.4 Reducing complexity
9.5 Reducing touches
9.6 z15 availability characteristics
9.7 z15 RAS functions
9.7.1 Scheduled outages
9.7.2 Unscheduled outages
9.8 z15 enhanced drawer availability
9.8.1 EDA planning considerations
9.8.2 Enhanced drawer availability processing
9.9 z15 Enhanced Driver Maintenance
9.9.1 Resource Group and native PCIe features MCLs
9.10 RAS capability for the HMC and SE
Chapter 10. Hardware Management Console and Support Element
10.1 HMC and SE introduction
10.1.1 Dynamic Partition Manager support
10.2 HMC and SE changes and new features
10.2.1 Driver Level 41 HMC and SE new features
10.2.2 New Rack-mounted HMC and Tower HMC
10.2.3 New Support Element
10.2.4 New service and functional operations for HMCs and SEs
10.2.5 SE driver support with the HMC driver
10.2.6 HMC feature codes
10.2.7 User interface
10.2.8 Customize Product Engineering Access: Best practice
10.3 HMC and SE connectivity
10.3.1 Standard HMC connectivity
10.3.2 Hardware Management Appliance
10.3.3 Network planning for the HMC and SE
10.3.4 Hardware considerations
10.3.5 TCP/IP Version 6 on the HMC and SE
10.3.6 OSA Support Facility
10.3.7 Assigning addresses to the HMC and SE
10.3.8 HMC Multi-factor authentication
10.4 Remote Support Facility
10.4.1 Security characteristics
10.4.2 RSF connections to IBM and Enhanced IBM Service Support System
10.4.3 HMC and SE remote operations
10.5 HMC and SE capabilities
10.5.1 Central processor complex management
10.5.2 LPAR management
10.5.3 Operating system communication
10.5.4 HMC and SE microcode
10.5.5 Monitoring
10.5.6 Capacity on-demand support
10.5.7 Server Time Protocol support
10.5.8 CTN Split and Merge
10.5.9 NTP client and server support on the HMC
10.5.10 Security and user ID management
10.5.11 System Input/Output Configuration Analyzer on the SE and HMC
10.5.12 Automated operations
10.5.13 Cryptographic support
10.5.14 Installation support for z/VM that uses the HMC
10.5.15 Dynamic Partition Manager
Chapter 11. Environmentals
11.1 Power and Cooling
11.1.1 Intelligent Power Distribution Unit (iPDU)
11.1.2 Bulk Power assembly (BPA)
11.1.3 Cooling requirements
11.1.4 Internal Battery Feature
11.2 Physical specifications
11.3 Physical planning
11.3.1 Raised floor or non-raised floor
11.3.2 Top Exit cabling feature (optional)
11.3.3 Top or bottom exit cables
11.3.4 Bottom Exit cabling feature
11.3.5 Frame Bolt-down kit
11.3.6 Service clearance areas
11.4 Energy management
11.4.1 Environmental monitoring
Chapter 12. Performance
12.1 IBM z15 performance characteristics
12.1.1 z15 single-thread capacity
12.1.2 z15 SMT capacity
12.1.3 IBM Integrated Accelerator for zEnterprise Data Compression
12.1.4 Primary performance improvement drivers with z15
12.2 z15 Large System Performance Reference ratio
12.2.1 LSPR workload suite
12.3 Fundamental components of workload performance
12.3.1 Instruction path length
12.3.2 Instruction complexity
12.3.3 Memory hierarchy and memory nest
12.4 Relative Nest Intensity
12.5 LSPR workload categories based on RNI
12.6 Relating production workloads to LSPR workloads
12.7 CPU MF counter data and LSPR workload type
12.8 Workload performance variation
12.9 Capacity planning consideration for z15
12.9.1 Collect CPU MF counter data
12.9.2 Creating EDF file with CP3KEXTR
12.9.3 Loading EDF file to the capacity planning tool
12.9.4 Tips to maximize z15 server capacity
Appendix A. Channel options
Appendix B. System Recovery Boost
B.1 Overview
B.2 Functions
B.3 Delivering extra capacity
B.4 Setting up the System Recovery Boost
B.5 Monitoring System Recovery Boost
B.6 Automation
B.7 Pricing
B.8 Software support
Appendix C. IBM Integrated Accelerator for zEnterprise Data Compression
Client value of Z compression
z15 IBM Integrated Accelerator for zEDC
z15 migration considerations
Software support
Compression acceleration and Linux on Z
Appendix D. Frame configurations
Power Distribution Unit configurations
Bulk Power Assembly configurations
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