APPENDIX B

Acronyms

1-D One-dimensional
2-D Two-dimensional
3-D Three-dimensional
AM Active Messages
API Application programming interface
ATM Asynchronous transfer mode
BFS Breadth-first spanning tree
BMIN Bidirectional multistage interconnection network
BNF Burton normal form
BRCP Base routing conformed path
BWS Buffered wormhole switching
CAD Computer-aided design
CIBU Control input buffer
CMOS Complementary metal oxide semiconductor
CMU Carnegie Mellon University
CNF Chaos normal form
COBU Control output buffer
CPU Central processing unit
CRC Cyclic redundancy check
CSMA/CD Carrier-sense multiple access with collision detection
CWG Channel wait-for graph
DASH Directory architecture for shared memory
DCM Direct connect module
DCSH Distributed Crossbar Switch Hypermesh
DEC Digital Equipment Corporation
DIBU Data input buffer
DMA Direct memory access
DMIN Dilated multistage interconnection network
DOBU Data output buffer
DP Duato’s protocol (Duato’s routing algorithm)
DR Dimension reversal
DSM Distributed shared-memory multiprocessor
DTB Data translation buffer
ECL Emitter-coupled logic
EMB Exhaustive misrouting backtracking
EOH End-of-header
EPB Exhaustive profitable backtracking
FDDI Fiber Distributed Data Interface
FIFO First in, first out
FM Fast Messages
GID Group ID
HL Hierarchical leader-based
HP Hewlett-Packard
HPF High Performance Fortran
IBM International Business Machines
I/O Input/output
IP Internet Protocol
ISI Information Sciences Institute
KSR Kendall Square Research
LAN Local area network
LC Link controller
LCU Link control unit
LD Label-based dual-path
LEN Lan, Esfahanian, and Ni
MAGIC Memory and general interconnect controller
MB-m Misrouting backtracking protocol with m misroutes
MCM Multichip module
MCP Myrinet control program
MIMD Multiple-instruction multiple-data
MIN Multistage interconnection network
MIT Massachusetts Institute of Technology
MPI Message Passing Interface
MST Minimal Steiner tree
MTBF Mean time between failures
MTTR Mean time to repair
NEC Nippon Electric Company
NI Network interface
NOW Network of workstations
NP Nonpolynomial
NPB NAS Parallel Benchmarks
NUMA Nonuniform memory access
OMC Optimal multicast cycle
OMP Optimal multicast path
OMT Optimal multicast tree
PAR Planar-adaptive routing
PC Personal computer
PCI Peripheral component interconnect
PCS Pipelined circuit switching
PE Processing element
PVM Parallel virtual machine
RAID Redundant arrays of inexpensive disks
RCU Router control unit
RHS Right-hand side
RMA Remote memory access
RST Rectilinear Steiner tree
SAF Store-and-forward
SAN System area network
SCHL Source-centered hierarchical leader
SCI Scalable coherent interface
SGI Silicon Graphics Inc.
SHRIMP Scalable high-performance really inexpensive multiprocessor
SIMD Single-instruction multiple-data
SPASM Simulator for parallel architectural scalability measurements
SPIDER Scalable pipelined interconnect for distributed endpoint routing
SPMD Single-program multiple-data
SPUmesh Source partitioned U-mesh
SQHL Source quadrant-based hierarchical leader
SWM Shallow water modeling
TMC Thinking Machines Corporation
TMIN Traditional multistage interconnection network
TP Two-phase routing algorithm
TPB-u Two-phase backtracking
UMA Uniform memory access
USC University of Southern California
VC Virtual channel or virtual channel controller
VCC Virtual circuit caching
VCT Virtual cut-through
VLSI Very large-scale integration
VRAM Video random-access memory
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