Makers are well-used to the benefits of free and
open-source hardware, from being able to study
and iterate on designs by others, to the promise
that if a design goes out of production you can
always make replacements yourself.
Open-source silicon, though, is not so well
understood — but thanks to the success of the
RISC-V (“risk five”) project, that’s changing.
The idea of an open processor, designed
around the concept of reduced instruction set
computing (RISC), from which others could
learn isn’t new: The Berkeley RISC project,
which launched in 1981, famously published its
research papers for all to read, providing a direct
inspiration for Sophie Wilson and Steve Furber
to create the Arm architecture that so many
chipmakers pay to license today.
ARM ALTERNATIVE
The Berkeley RISC project inspired numerous
processor projects, some open and others closed,
but it was the launch of the RISC-V project in 2010
that truly lit a spark.
Born at the same university as the original,
RISC-V is Berkeley’s fifth-generation RISC
architecture — and by far its most successful.
Originally pitched by Krste Asanović as a “short,
three-month project” aimed at graduate students
before attracting Berkeley RISC alum David
Patterson, RISC-V has leapfrogged its forebears
to become the most successful free and open-
source architecture in history.
FREEDOM IN SILICO
There’s an important distinction to note: “free”
as well as “open source.” Sun’s microSPARC
processor was open source, but not free:
Anyone wishing to make modifications needed
a commercial license. RISC-V, by contrast, is
free-as-in-speech: Anyone can implement
RISC-V either as-written or with as many tweaks,
modifications, and extensions as they desire
— and never have to pay a cent in royalties or
license fees.
What began as a 3-month university project
now ships millions of cores a year: RISC-V
implementations are found in commercial
products including smartwatches, fitness bands,
storage products, and graphics cards, where the
(Figure
A
).
allure of true freedom — plus a bundle saved on
license fees — has won out against the desire to
keep proprietary IP suppliers on-side.
Unsurprisingly, RISC-V has also been making
inroads into the maker sector — slowly at first,
but gaining momentum with each passing year.
Low-power microcontroller parts came first, with
application processors soon following. Server-
class hardware, including proposed 128-bit chips
designed to accompany existing 32- and 64-bit
parts, is right around the corner.
FROM FPGAS TO CHIPS
At first, experimentation was a challenge. Few
RISC-V designs had been committed to silicon,
as the specification had yet to be ratified, so if you
wanted to develop for RISC-V you needed to use
field-programmable gate array (FPGA) hardware
to run soft-core implementations — or even
emulate RISC-V in software on a mainstream
Arm or x86 chip.
SiFive, co-founded by Asanović himself, was
ARM IN ARM: Inspired by Berkeley’s 1981 RISC project,
Sophie Wilson (far left) and Steve Furber (third left)
created the Arm microprocessor architecture that’s
now ubiquitous.
RISC REWARD RATIO: SiFive, co-founded by RISC-V
project leader Krste Asanović, was first to market with
RISC-V chips and Arduino-compatible boards in 2016,
and Linux boards in 2018. Today they’re designing
a 12-core CPU for NASA’s new High-Performance
Spaceflight Computing (HPSC) processor.
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