5.2.1 Metal Oxide Resistive RAM (MO‐RRAMs) as Synapses

Metal oxide RRAM cells consist of a metal–insulator–metal (MIM) structure where the insulator can undergo abrupt switching into a conductive state and gradual switching into a nonconductive state. This resistive switching is related to the reversible formation and disruption of a conductive filament (CF), which provides a shunt for the top and bottom electrodes through the insulating layer. The CF formation and dissolution can be related to the displacement of oxygen atoms.

In June of 2014, Arizona State University discussed using a metal oxide RRAM (MO‐RRAM) as a synaptic device for a hardware implementation of neuromorphic computing [1]. The gradual resistance modulation capability in RRAM can emulate analog synapses and the stochastic switching behavior of the RRAM could emulate binary synapses. Neuromorphic computing is of interest since it uses massive parallelism from distributed computing and localized storage in neural networks. Its error tolerance is interesting for use in vision and speech recognition. Neuromorphic computing can be run in a conventional digital computer enabled by software. Two terminal RRAMs can be used as artificial synapses. Metal oxide RRAM is interesting for neuromorphic systems due to low energy consumption, compatibility with CMOS technology, and potential for Gbit density through 3D integration.

A hybrid neuromorphic system with CMOS neurons and RRAM synapses was demonstrated. During RESET a conductive filament (CF) is ruptured and a variable tunnel gap forms between an electrode and the residual filament. The variation in tunnel gap results in multilevel resistance states. The SET is abrupt. Resistance versus number of voltage pulses is shown Figure 5.1 for (a) an abrupt SET and (b) a gradual RESET.

The RRAM can function as the analog synapse using the gradual RESET and the binary synapse using the stochastic SET for competitive learning. A simulation of a winner‐take‐all network for an orientation classification function was discussed. Comparable system performance was shown between the analog synapse and the binary synapse.

Any resistive memory with multilevel characteristics can be used as a synaptic device in a neuromorphic computing system. In 2016 POSTECH [2] investigated abruptly formed filaments and found this abrupt formation degrades analog switching behavior during potentiation. By using a balanced SET/RESET pulse operation and modulating the switching gap to control the filament growth, the conductance behavior could be gradually changed.

An HfO₂‐based RRAM array with multilevel states under a constant pulse was shown to have a controlled filament. The RRAM cell had a TiN/HfO₂/Ti/TiN stack made on top of a transistor in an 8 inch wafer process. An I–V curve under 100 μA with 1.2 V was found. A conductive filament (CF) of oxygen vacancies (ions) was formed under positive bias and gradually dissolved with negative bias. This resulted in a switching gap between the CF and the bottom electrode.

Synaptic behavior was evaluated by applying successive identical pulses. The multilevel states of conductance were observed in depression and a binary state was shown during potentiation. Synaptic behavior was demonstrated. A schematic illustration of a plausible mechanism is shown in Figure 5.2. Figure 5.2 (a) shows the initial filament (SET) while Figure 5.2 (b) shows a RESET with a partially ruptured conductive filament. Figure 5.2 (c) represents the second SET showing a thicker conductive filament.

In August of 2016, POSTECH discussed improving synaptic behavior of a neuromorphic system using identical pulses on a filamentary AlO _x /HfO₂ bilayer RRAM array to emulate the synaptic function [3]. It was found that the multilevel states of conductance were attained by varying measurement conditions for the formation and rupture of a conductive filament.

A TiN/HfO₂/Ti/TiN stack was used for the RRAM. Multiple current states were found by either varying the RESET voltage from –0.7 to –1.9 V with a step voltage of –0.05 V negatively or varying the gate voltage from 0.6 to 1.2 V with a step voltage of 0.05 V positively.

Abrupt switching was found to lead to an unchanged conductance state causing degradation in the accuracy of pattern recognition. A linear potentiation or depression behavior of conductance was shown by applying identical pulses using the effect of a barrier layer on switching. This was done by making an RRAM on top of an Al electrode. It was found that when the range of conductance was symmetrically controlled at both polarities improved accuracy was achieved for pattern recognition using a neural network.

An optimized programming method for linear potentiation in a filamentary HfO₂ RRAM synapse intended for use in a neuromorphic system was discussed by POSTECH in December of 2016 [4]. Various programming methods were used to linearly change the resistance state with either SET voltage/pulse ramping or Gate voltage ramping. The results showed that the multilevel cell (MLC) was related to the size of the conductive filament where the oxygen vacancies moved under the influence of applied pulses. By optimizing the pulse for a given condition, such as identical pulses, it was possible to linearly increase the MLC behavior, which enabled pattern recognition accuracy in neuromorphic systems.

For proper operation of an RRAM synaptic device, a monotonic increase or decrease of the MLC characteristics should be expected. Recent studies have, however, focused on the use of gradually transited MLC in depression with abrupt formation of conductive filament in potentiation. This asymmetric MLC behavior tends to lead to a degradation of pattern recognition accuracy. A possible solution is two identical synaptic devices serving as a single synapse, but this consumes a large amount of power per area.

An alternative solution is linearly increased MLC behavior in potentiation and in depression. This was achieved by using different pulse methods for potentiation and for depression. A CMOS compatible TiN/HfO₂/Ti/TiN RRAM structure was used with a 0.35 µm transistor for a 1T1R configuration in a 200 mm wafer process. During potentiation, the gate voltage is ramped at a fixed set voltage. The increased currents are proportional to the large gate voltage due to the thickness of the filament formation. Ramping the gate voltage at a fixed SET voltage results in an MLC operation during potentiation due to thickening of the filament.

For depression, an optimized RESET pulse can lead to dissolving the conductive filament with a particular switching gap, which enables intermediate states as a result of varying partially dissolved conductive filament gaps. As a result, MLC operation with varied programming schemes during potentiation resulted in MLC states during potentiation and depression, which improved the accuracy for pattern recognition applications in neuromorphic systems.

5.2.2 Conductive Bridge RRAM (CB‐RRAM) as Synapses

In the case of conductive bridge RRAMs (CB‐RAM) cells, the CF formation and dissolution is related to metal ions. Both CB‐RAMs and MO‐RRAM cells have low operating voltages, fast programming, nanoseconds of read time, low power consumption, scalability, and endurance that is higher than conventional Flash memory.

Various trade‐offs exist between the memory window and endurance and the memory window and switching time. The low resistance state (LRS) when the CF is fully formed is modulated by the compliance current, which is applied so the higher the programming current the thicker the CF and the lower the resistance state. In 2015, CEA LETI described an example of an MO RRAM and a CB‐RAM for use as synapses [5]. The MO RRAM was formed by two electrodes, in this case, one Ti and one TiN with an HfO₂ insulating layer between them. The CB‐RAM was formed with a W/HfO₂ electrode and an Ag or Cu electrode with a GeS₂ electrolyte between them. In the case of the CB‐RAM, the CF will be formed of Ag or Cu atoms. Schematic cross‐sections of the MO RRAM and a CBRAM are shown in Figure 5.3.

The multilevel capability of a solid electrolyte RRAM, a form of conductive bridge RAM (CB‐RAM), was explored for use as a synapse device by several Chinese and Taiwanese Universities in August of 2015 [6]. The device used a Pt/GeSO/TiN structure. The cut‐off voltage was varied during the I–V cycles, resulting in continuous multilevel conductance states. It was also possible to vary the AC pulse programming and voltage amplitudes to obtain multilevel states. It was noted that arithmetic operations based on analog memories may also be an interesting computational paradigm to complement digital von Neumann systems. An electronic synapse device was made with a Pt/GeSO/TiN thin film stack. The 16 nm thick switching layer was RF magnetron sputtered on to a TiN/Ti/SiO₂/Si substrate. The multilevel bipolar resistance switching I–V curves of the Pt/GeSO/TiN device are shown in the diagram in Figure 5.4.

A series of gradually increasing set pulse voltages and pulse widths were applied to the Pt/GeSO/TiN device and the conductance gradually increased with increasing pulse voltage and pulse width. The multiple levels are shown as nearly continuous. This multilevel effect can be useful in systems emulating biological synapses.

Certain characteristics are important when investigating the capability of the device to emulate adaptive learning in biological synapses. In a biological synapse, when the pre‐spike signal precedes the post‐spike signal, the strength of the synapse undergoes long term potentiation (LTP) or increase; otherwise it undergoes long term depression (LTD) or decrease. Closer timing spikes lead to a larger change of feedback. This is called the spike timing‐dependent plasticity (STDP) learning rule, which has been shown in various brain circuits for many species of creature. STDP learning was confirmed in this CBRAM device.

5.2.3 Phase Change Memory (PCM) as Synapses

Technologies for brain‐type computing intended to overcome implementation issues for neural networks can also use resistive memory such as phase change memory (PCM). These programmable resistive RAMs were used in March of 2014 by CEA‐LETI, CEA‐LIST, and InRIA to obtain low area synapses [7]. PCM are made of chalcogenide glass material, which can be either in an amorphous or a crystalline state depending on the rate of heating and cooling of the material. The crystalline phase has a lower resistivity than the amorphous phase, which results in a resistive RAM with multiple states that can be used as variable state synapses.

Through‐silicon‐vias (TSV) were used with the PCM in this demonstration to improve analog neuron connections, reduce their area, and improve connectivity. The conductance of the PCM is modulated by the heat from the current flowing through the PCM devices. These devices were used to produce arrays of artificial synapses.

A 2‐PCM synapse was discussed that emulated synaptic functions in large scale neural networks. The two PCM devices had opposite contributions to the neuron integration. Partial crystallization of the phase change material of one PCM was used to increase the equivalent weight of the synapse and partial crystallization of the other to decrease it.

5.2.4 PCMO RRAM as Synapses

A Pr0.7Ca0.3MnO3 (PCMO) RRAM‐based synaptic device for neuromorphic computing was developed in 2014 by Pohang University of Science and Technology (POSTECH) and the Gwangju Institute of Science and Technology [8]. Thin film elements of PCMO can be made with thicknesses down to a few tens of nanometers. A wafer scale device was made and showed good switching uniformity and analog memory behavior. Figure 5.5 shows bipolar I–V curves at different sweep voltages, illustrating the possibility of analog memory behavior.

The PCMO‐RRAM was used to implement analog artificial synapse characteristics in neuromorphic systems. A face recognition function was used to show varying potentiation and depression characteristics of the RRAM synapse. Figure 5.6 shows potentiation and depression curves. Potentiation voltage is –3 V and depression voltage is +3 V.

Simulations were performed for time series prediction and face recognition applications based on a proposed RRAM synaptic device model. A multilayer neuromorphic architecture was designed. The architecture consisted of 408 CMOS neurons and 83 200 RRAM synapses. For negative synaptic weight implementation, two RRAM synaptic devices were used as one synapse.

In May of 2015, POSTECH, Gwangju Institute of S&T, and IBM discussed the optimization of conductance change behavior in analog resistive memory synaptic devices based on PrCaMnO₃ (PCMO) [9]. In this study, resistive memory based on PCMO is applied in a neural network application, which is classification of the MNIST handwritten digits using a multilayer perceptron trained with back propagation under a variety of simulated conductance change behaviors. Linear and symmetric conductance changes during increasing and decreasing device conductance are shown to offer the highest classification accuracies. Additional improvements could be obtained using nonidentical training pulses at the cost of requiring measurement of individual conductance during training. Using PCMO‐based synaptic devices, a generalization accuracy on a previously unseen test set was 90.55%.

PCMO RRAM memory arrays of 1‐Kbit were made to evaluate synaptic devices. The device stack had a 50 nm thick Pt bottom electrode, with 30 nm deposited polycrystalline PCMO film patterned with conventional lithography and reactive ion etching (RIE), followed by an 80 nm thick SiN _x layer. The switching behavior of an RRAM based on this PCMO stack was determined and neural network simulations were done using its conductance change behavior. Handwriting digit classification accuracies were found to be high for RRAM‐based synaptic devices with symmetric switching behavior. They are maximized when that response is linear.

In August of 2016, POSTECH, Gwangju Institute of S&T, and IMEC discussed an analog synapse PCMO‐based interface switching device with varying electrode materials [10]. It was compared with a filamentary switching device having 1‐bit storage and variability issues. The interface switching devices showed good electrical properties, which included 5‐bit (32 level) multilevel cell characteristics along with wafer scale switching uniformity and scalability of switching energy with device area. An Mo electrode was proposed to improve data retention of the interface switching device. The Mo electrode increased the oxidation barrier height to 0.4 eV, which improved the retention time and pattern classification accuracy of the neural networks.

A 10 nm thick polycrystalline PCMO film was deposited on a Pt/Ti/SiO₂/Si wafer using RF sputtering. A 100 nm SiN_x vertical side wall was deposited by plasma‐enhanced CVD and then dry etched using RIE with a 150 nm via‐hole structure. Various top electrodes were used including: Al, Ti, Ta, and Mo. The data retention characteristics and switching uniformity of the basic interface RRAM were studied with varying electrode materials for synapse applications. Using neural network simulations it was confirmed that data retention characteristics were critical to guarantee the pattern classification accuracy.

An Mo/PCMO synapse device was reported with good wafer scale switching uniformity, multilevel data storage capability, and good retention characteristics. The improved LRS retention characteristics were explained by the high activation energy of the oxidation process and high electronegativity of the Mo electrode. It was confirmed that an improvement in data retention directly affected the pattern classification accuracy of the neural network.

5.2.5 RRAM with Simultaneous Potentiation and Depression

A homogeneous barrier modulation (HBM) RRAM that was capable of a simultaneous potentiation (P) and depression (D) was described in October of 2015 by National Chiao Tung University [11]. A simulation of pattern learning algorithm was performed based on the winner‐take‐all rule and on experimental synaptic characteristics. A circuit diagram of the simulated neuromorphic system and applied signal waveforms is shown Figure 5.7.

The winner‐take‐all learning rule was applied to update the synaptic weight of each synapse through training. This clock‐synchronized system included two phases: (1) training during which one set of training voltage patterns was sent into the synapse array by pre‐neurons (column) while post‐neurons (row) sum up the current through the synaptic cells in every column and (2) fireback during which voltage patterns of pre‐neurons were inverted and only the post‐neuron that sums the largest amount of current during (1) fired a large but shorter pulse back into the same column. The combinational effects are designed to potentiate or depress synaptic weights of the cells on the fired column toward lower or higher resistance according to the 1/0 of the training patterns.

The potentiation plus depression (P + D) method improved the contrast development of pattern learning and immunity to input noise compared with the P‐only method. The recent fast development of RRAMs has inspired several attempts to use them as the high density electronic synapses in artificial neuromorphic systems. This study reported on a homogeneous barrier modulation (HBM) RRAM that was capable of a simultaneous P and D operational scheme. The RRAM stack was SiO₂/Ti/TiO₂(30 nm)/TaO₂(10 nm)/Ta/BE.

5.2.6 Other Nonvolatile Memories with Analog Properties

An example of potentiation and depression in a memory using a measurement of capacitance rather than resistance was illustrated in February of 2015 by Seoul National University and Samsung [12]. A silicon‐based charge trap memory with an Al/HfO₂/Al₂O₃/Si₂N₄/Si stack was used, which emulated that memory function of a biological synapse. The quantity of the trapped charge in the proposed Al₂O₃/HfO₂/Si₃N₄ stack was estimated by measuring the capacitance over time with different repeated input pulses, which are similar to the behavior of a biological synapse and were regarded as representing synaptic weight changes. By applying repeated voltage pulses at periodic intervals at different times, reliable short term plasticity and long term potentiation properties were found along with their transition behavior. This architecture was found to be compatible with a CMOS process and had promise of being possible to implement in an electrical neuromorphic system.

The fabricated device consisted of an Al gate electrode and an Al₂O₃/HfO₂/Si₃N₄ gate stack formed on a p‐type silicon (100) wafer. Initially an n⁺ region was formed with As⁺ ions and annealed to supply electrons to the gate stack during programming. Then HfO₂ layers and Al₂O₃ layers were formed by ALD at 350 °C. An Al layer was then deposited and patterned to form the top electrode. The area of the Al electrode is about 100 × 100 µm². Programming was done at 7 V for 1 ms and erased at –7 V for 1 ms. An energy band diagram of an Si/Si₃N₄/HfO₂/Al₂O₃/Al cell is shown in the diagram in Figure 5.8. CV measurements were used in an effort to imitate synaptic plasticity. The competing effect of memory loss and memory strengthening was observed in repeated simulations.

An amorphous silicon‐based metal–semiconductor–metal (MSM) device can be used as a resistive switching device or a neuron in a neuromorphic computing system. In 2015 Carnegie Mellon University showed that CMOS compatible Pt/a‐Si/Cu stacks show negative differential resistance (NDR) that enables their operation as oscillatory elements and nonlinear threshold switches [13]. To demonstrate oscillations in amorphous silicon (a‐Si), this study showed frequency tunability from 5 kHz to 80 MHz by modulating the series ballast and changing the source voltage. The devices showed <1.2 V and <100 μW operation. As threshold switches, these devices showed an ON/OFF resistance >800 with a peak current density of > 0.3 MA cm² at 1 V. The change in modes of operation of the device was studied as a threshold switch and an oscillator.

5.3.1 Neuromorphic Architectures as Dense TSV 3D Structures

Neuromorphic architectures are 3D structures with massive parallelism. They exhibit a high level of connectivity. Deep computation and cognitive functions reach thousands of neurons and millions of synapses. It is assumed, therefore, that the neural network must be multilayer and densely connected using point‐to‐point connectivity. 3D architectures are therefore expected to reduce routing congestion, reduce critical path length, and save area and power.

The network studied by CEA and associated labs in 2014 was a neural processor with two layers of densely connected networks using through silicon via (TSV) intended to recognize objects appearing in a 1000 frame/s video stream [7]. The target operation was executing complex tasks. Two separate circuits were designed for face‐to‐face connections. Short TSVs could be used to bond the last metal layers of both circuits and longer TSVs could be used that cross all metal layers. In 3D monolithic integration, transistor layers are made one on top of the other on the same die. An example of transistor level monolithic 3D integration is shown in Figure 5.9.

Another dense 3D synaptic architecture using a self‐rectifying bipolar Ta/TaO_x /TiO₂/Ti RRAM stack was described in December of 2014 by NCTU [14]. This RRAM device showed good analog synaptic features. Ultralow energy consumption was shown, which was comparable to that of a biological synapse at <10 fJ/spike. Several synaptic features were demonstrated using a Ta/TaO_x /TiO₂/Ti RRAM synaptic element. The analog synaptic characteristics were modeled using physical and compact models. SET controlled and RESET controlled multilevel cell (MLC) operations for the 2D Ta/TaO_x /TiO₂/Ti RRAM device were shown. By varying V _set or V _reset, multiple resistance states could be read out at –2 V. A very low current was found at a positive voltage bias.

5.3.2 3D Vertical RRAMs as Synapses Connecting Neurons

A number of vertical 3D RRAM arrays have been described for use in neuromorphic applications. The RRAM element that exhibits analog conductance behavior acts as a synapse connecting parallel input and output neurons. In July of 2014, the University of Michigan discussed a 3D vertical two‐layer RRAM with well characterized analog switching characteristics for use in neuromorphic computing applications [15]. The dual‐layer RRAMs had a WO_x switching layer, which was formed at the sidewall of horizontal electrodes. The devices showed well characterized analog switching characteristics and a very small mismatch in electrical characteristics between devices formed in the two layers, as shown in Figure 5.10, which is a schematic of current output versus time for the upper and lower device.

The 3D vertical device structure allowed higher storage density and bigger connectivity for use in neuromorphic computing. The vertical devices were shown to have potentiation and depression characteristics similar to planar RRAMs. The two layers could be programmed independently with no crosstalk seen between the layers.

The devices could be programmed with <10% mismatch. The architecture was considered scalable and suitable for development of analog memory and neuromorphic systems. During write and erase a V/2 method could be used to avoid disturbing unselected bit‐lines and word‐lines. During READ, grounding methods could be used to avoid sneak path currents. The I–V characteristic was nonlinear, which was expected to improve the read margin as the array size scaled. The conductance change ratio and switching speed may be improved further by optimizing the various process steps.

In December of 2015 various French labs investigated the vertical pillar RRAM (VRRAM) concept for use in neuromorphic applications [16]. In this case, one synapse was emulated by one VRRAM pillar. The basic functionality of the HfO₂‐based MO‐VRRAM was given as 20 ns switching time, up to 10⁷ cycles with stable 200 °C data retention. Specific analyses were made of the resistance and switching voltage variability to conveniently address the various potentiation applications. A correlation effect was found to exist between adjacent cycles. This was taken to mean that the conductive filament keeps a memory of its shape in the previous state, which leads to reduced cycle‐to‐cycle variability in a sufficiently short cycle range. A compact model and circuit simulations were used to propose the VRRAM for convolutional neural network applications. Reliability was good and of lesser circuit complexity than planar approaches.

The VRRAM device used a TiN/SiO₂ double layer deposited on a vertical W plug. The TiN thickness was 10 nm. The cylinder was formed using a plasma etch to pattern it. An nMOS transistor was used as the selector for the memory. An analog‐like conductance behavior was due to the variability of an oxide‐based RRAM. A model was used to simulate a synapse composed of stacked VRRAMs with from 2 to 24 levels. The VRRAMs were addressed simultaneously and the output signal corresponded to the sum of all the VRRAMs in parallel. A simulated neuromorphic array is shown in Figure 5.11. A synapse is composed of “N” VRRAM cells in a vertical pillar, which are addressed in parallel. The output neuron collects the contributions of all the synapses.

The vertical pillar RRAM used for neuromorphic applications was shown again in 2016 by CEA and various associated labs [17]. An Al₂O₃/Cu CB‐RAM was used in a vertical configuration for neuromorphic applications. Each cell constituted a vertical synapse. A selector and array configuration was tuned to reduce the variability of voltage seen by each cell. A circuit was designed to implement a neuromorphic system. The neural circuit scheme is shown in Figure 5.12, where vertical‐CBRAM pillars have m levels. All levels share a common transistor. Each pillar has a transistor with an n × wider channel compared to plane select transistors.

The synapses are emulated by 1TnR VRRAM pillars, which share a transistor per level. One transistor per pillar is used to select the pillar itself and no back‐end selector is required. In a worst case, a given CBRAM on a selected pillar has to be SET while all the other CBRAM on the selected pillar are LRS. All other pillars are left floating to cancel any sneak path current on other CBRAMs so their influences can be neglected. The main issue is the voltage difference V _te–V _be seen by the V‐CBRAM in the LRS state serially connected to the line access transistor on an m‐levels selected pillar. The SET condition can be studied as a function of the number m of VRRAM on a pillar and the oversize factor n of the access transistor.

The actual implementation in silicon of such a vertical pillar structure was shown in 2016 by Stanford University, NNDL, and Narlabs, who discussed a four‐layer 3D vertical RRAM integrated with a FinFET [18]. A schematic cross‐section of the 3D RRAM is shown Figure 5.13.

The 3D architecture was intended for dense neuron‐in‐memory computing and implemented 10¹¹ address and read cycles on 3D RRAM. The RRAM stack was used as a 3D neuromorphic vision system based on a 32 × 32 × 4 3D array. The input and output neurons were connected by the 3D RRAMs acting as 3D variable resistance synapses. A winner‐take‐all network with a stochastic learning rule was simulated for orientation detection. Four‐layer synapses were self‐organized into distinct resistance maps. The balanced array configuration and unique common pillar structure made this vertical 3D RRAM an energy efficient versatile computing unit.

A manufacturable two‐layer 3D implementation of a metal oxide RRAM crossbar array circuit was described in 2016 by the University of California, Santa Barbara, which could be used for both high density nonvolatile memory applications and also for neuromorphic implementations [19]. Analog timing of the memory state combined with high integration density of resistive RAM was required for compact implementation of a synapse. These are the most frequently encountered devices in artificial neural networks and would be essential for low energy implementations of large scale neuromorphic circuits. One method of increasing the effective RRAM density is by vertical monolithic integration of RRAM crossbar circuits. A bilayer stacked metal oxide RRAM crossbar circuit was fabricated and characterized.

These stacked crossbar arrays can be made using 1T1R configurations, but these three terminal devices have low scalability. The alternative is to use RRAMs without a selector device, which have highly nonlinear I–V characteristics to avoid sneak paths and half select issues. Experimental results showed good uniformity for the RRAMs in both crossbar layers. The process flow used was low temperature and CMOS compatible and could be extended to multilayer stacking.

Another issue is thermal crosstalk, which determines the high maximum temperature of switching. This was estimated to be >700 K for MO‐RRAMs. This means the switching in the bottom device could cause disturbances in the devices stacked above. More needs to be understood about device behavior through the entire crossbar system to know if successful analog computing applications are feasible.

The 3D configuration used in this device monolithically integrated two TiO_x ‐based passive crossbar arrays. The fabrication method required no high temperature processing, showed no thermal crosstalk, and could be repeated with additional layers. In this process, two fully passive TiO 10 × 10 RRAM crossbars were monolithically integrated using an in‐situ low temperature reactive sputtering deposition followed by a planarization step. The middle electrodes were shared between the bottom and top layers, as shown in the cross‐section of the process in Figure 5.14. The metal layers were deposited as a blanket using reactive sputtering along with highly selective hard masks such as Al₂O₃. The hard mask was patterned and the metal etched using an Ar ion beam. The metal feature shape was controlled using tilted etching. Chemical mechanical polishing and etch‐back was used. The maximum temperature during fabrication was 175 °C during sacrificial SiO₂ deposition, which permits this crossbar array to be made in the back‐end‐of‐the line (BEOL) over a conventional CMOS process.

Electrical characterization showed good uniformity and analog programmability for the 3D crossbar circuits. The devices were formed using a floating biasing configuration and quasi‐DC current ramps without external or internal compliance. The devices were formed one by one and then immediately switched to the low conductive state. The bottom devices were done first followed by the top layer devices. Bottom devices have an average forming voltage of 2.5 V and top devices 2 V. No thermal crosstalk was seen during forming. Good similarity in device behavior between bottom and top devices was observed.

An ON/OFF current ratio of 10 was observed with a RESET voltage of –1.8 V and SET current of 300 μA. At a RESET voltage of –2.4 V the ON/OFF ratio was about 100. A 74% planarization yield was achieved across the wafer. This work was expected to be a key step toward multilayer RRAM crossbars integrated on CMOS for neuromorphic applications.

5.5.1 Introduction to Spiking Neural Networks

Neuromorphic computing can be achieved using variable resistance memories as synapses in spiking neural networks. Each synapse can have its own conductance profile and these profiles can be altered during evolution of the system. A synaptic array can be configured using self‐rectifying multivalued RRAMs. It can also be configured as a hybrid CMOS/RRAM array using diodes or transistors to eliminate sneak current with multivalued RRAM.

5.5.2 Hybrid RRAM/CMOS STDP Neuromorphic Systems

Resistive memory devices can be used as synapses in neuromorphic cognitive systems. Hybrid MO‐RRAM/CMOS synapses can be based on resistive RAM and transistor circuit design and operation. Real time spike‐based learning and recognition of visual patterns was demonstrated in 2016 by the Politecnico di Milano and IU.NET [22]. The learning accuracy and power consumption of the synapse blocks was discussed. Resistive memories have high speed and small cell size due to the two‐terminal structure and they have high endurance. Hybrid RRAM/CMOS synapses for neuromorphic circuits were shown capable of on‐line pattern learning and recognition. Synaptic schemes can be based on 2T1R and 1T1R structures. The spike‐timing dependent plasticity (STDP) characteristics of the 1T1R synapse with bipolar RRAM was shown along with unsupervised learning with a fully connected neuromorphic network using simulations. Learning efficiency and power consumption of the synaptic blocks was shown.

Hybrid RRAM/CMOS synapses were used in the circuit design, operation, and demonstration of real time spike‐based learning and recognition of visual patterns. The learning accuracy and power consumption of the synapse blocks was discussed. A main requirement of synaptic circuits is being able to tune their resistance in response to incoming neuron spikes according to the STDP protocol, which has been observed in biological systems. Circuit diagrams of a 2T1R synapse and a 1T1R synapse are shown in Figure 5.18.

In both of these circuits, the connections with the PRE and POST permit overlaps between spikes, which enable STDP. The resistive element (circle) can be any two‐terminal memory including a unipolar or bipolar RRAM or phase change memory (PCM).

In the 1T1R design, the BE terminal is connected to the POST to sustain both communication and STDP functionalities. A PRE synapse–POST circuit for a 1T1R synapse is shown in Figure 5.19. The PRE spike applied to V _g together with a constant bias sustained by the POST at V _te excites a transient current in the 1T1R synapse. Figure 5.19 shows this as the negative constant V _te, which induces a negative spiking current corresponding to the PRE spike applied to V _g. The spiking current enters the POST using the BE and is integrated, causing a staircase‐type increase in the internal potential V _int in the POST. As V _int exceeds a threshold, the POST delivers a forward spike to the next neuron layer and a backward spike to the V _te. The backward spike acts as the STDP function and may have various shapes depending on the various specific RRAM used.

Waveforms of V _g and V _te for delta t > 0 and delta t < 0 are shown in Figure 5.20 (a) and (b) respectively. The PRE circuit drives V _g, which induces a current spike in the 1T1R, which is integrated by the POST circuit. The membrane potential V _int increases by integration, eventually causing a fire event as it exceeds a threshold. At the fire event, a backward POST spike is applied to V _te to induce potentiation (depression) in case of overlap with the PRE spike with Δt > 0 (Δt < 0).

The results of the analysis supported on‐line pattern learning and recognition by STDP in RRAM‐based synapses. A critical parameter for on‐line learning and recognition is power consumption. It was found that, by reducing the compliance current with filament size, downscaling was possible and that STDP energy could be decreased by reducing the pulse width for potentiation and depression. The compliance current is set to control the resistance value of the low resistance state (LRS) during the SET operation. It was estimated that the energy per synapse during a fire event could be as small as 1 pJ. The communication energy also needed to be reduced, which involved the spike duration. It was found energy could be reduced below the fJ range.

A 1T1R (RRAM) synapse capable of spike‐timing dependent plasticity was discussed in 2016 by the Politecnico di Milano, IU.NET, and Micron. It had an area improvement over the previous 2T1R structure [23,24]. This synapse circuit used a one transistor one RRAM (1T1R) structure as a tunable connection between a presynaptic neuron (PRE) and a postsynaptic neuron (POST). The RRAM synapse passively transmitted spikes and also updated its weight according to a spike‐timing‐dependent plasticity (STDP) protocol. The STDP characteristics were characterized and modeled. A two‐layer neuromorphic network was shown with pattern learning and recognition with deterministic and stochastic switching.

The RRAM device was a silicon‐doped HfO₂ layer with a TiN bottom electrode and Ti top electrode. 1T1R devices were used for pulsed demonstration of driving the top electrode and gate nodes using a waveform generator. The RRAM device had a typical bipolar IV curve. It was demonstrated as a 1T1R synapse connected to PRE and POST as Figure 5.21 (a). Typical spike signals at V _g and V _te are shown in Figure 5.21 (b).

A V _g spike from PRE induces a current, which is integrated by POST and eventually leads the synapse to fire. At fire, V _te induces potentiation for Δt > 0 or depression for Δt < 0, resulting in STDP.

The STDP characteristics, in this case the change of conductance as a function of Δt, are illustrated in Figure 5.22 and were found from both experiments and calculations. The range of conductances are shown from 25 to 500 kohm. The change of conductance was found for increasing initial resistance R ₀.

A two‐layer neuromorphic network was demonstrated being used with a visual input pattern disturbed by a typical random noise pattern with a typical output pattern and noise sequence appearing at POST. Learning was shown after a given number of cycles.

The 1T1R RRAM synapse capable of spike‐timing‐dependent plasticity was shown to be an area improvement over the earlier 2T1R structure. STDP functionality was shown along with robust learning by deterministic and stochastic synapses. A 10³ reduction in power consumption was shown as a result of using a burst operation. The RRAM was based on a silicon‐doped HfO₂ layer with a TiN bottom electrode and Ti top electrode.

Learning and classification of handwritten digits from the MNIST database was simulated. A fully connected two‐layer perceptron network for simultaneous multipattern learning of 10 digits was used with a second layer consisting of 10 neurons interconnected by an inhibitory synapse permitting differentiating learning of multiple digits. The first layer had 784 neurons and the second had 10. The MNIST handwriting digit classification showed 86% efficiency.

An RRAM‐based neuromorphic computing device with a 1T1R crosspoint array was described in 2015 by Tsinghua University [25]. The 1T1R array is shown in Figure 5.23. The 1T1R crossbar array minimized the sneak paths of the 1R and 1R1S array and was shown to have lower power dissipation than a 1R RRAM neuromorphic computing device.

Both the two‐terminal 1R and 1S1R crossbar arrays when implemented in a synapse network have good performance but suffer from both sneak path current and program disturb. These limit the computing accuracy of the neural network and also limit the size of the array. In this study, a 1T1R cell is used as the element for an optimized synapse array for neuromorphic computing. A differential pair formed a synapse. Pattern classification was done by simulation using this architecture and the impact of RRAM cell variation on the system was analyzed.

In a column the top electrode of the RRAM is connected to the BL and the source of the transistor is connected to the SL. In a single row, all cells have their transistor gate connected to the same word‐line. This organization decreases the sneak current significantly both suppressing disturbance and decreasing power consumption.

In the proposed neural network, a single layer was used based on a 10 × 6 1T1R synapse array. An RRAM model with asymmetric bipolar switching performance was used. Six columns were divided into three classes in accordance with three output neurons. Every two columns in sequence together connect to a post‐neuron. The difference current is the current that flows to the first output neuron. The schematic of the single‐layer bipolar neuron network is shown in Figure 5.24.

A total of 30 synaptic weights is realized as two synapse cells representing a synaptic connection. The 10 × 6 1T1R synaptic array connects with three post‐neurons and 10 inputs, which include a constant bias input. Ten training patterns are input as a 3 × 3 pixel black and white image and the input signal is represented by a gate voltage of 5 or 0 V, corresponding to a black or white pixel. All the 1T1R are HRS initially (dark block). After the pattern is applied, the whole array is at read mode simultaneously. To adjust each cell’s weight a parallel programming operation strategy is used column by column where the SET and RESET process are separated. After 15 interations, the final distribution in each column, shown in Figure 5.25, is the input letters “z”, “v” and “n”.

Compared with the same function done with a 1R‐based RRAM crossbar array, the new 1T1R synapse architecture operates more easily and converges more rapidly. The 1T1R structure has low power consumption and the parallel operating mode decreases power dissipation further. The resulting power dissipation was about half that of a 1R RRAM array.

5.5.3 Memory Synapse and Neuron Systems

An oxide‐based analog synapse device and an insulator–metal transition (IMT) oscillator neuron device were described for a neuromorphic system in 2016 by POSTECH [26]. The redox reaction was controlled at the metal/PrCaMnO₃ (PCMO) interface of the synapse device in order to control synapse characteristics such as switching uniformity, disturbance, retention, and multilevel data storage under identical pulse conditions. For the neuron device, an Mo electrode was shown to have the best data retention characteristics. Using the IMT characteristics of NbO₂ film, an IMT oscillator was developed for the neuron. Accurate pattern recognition was found using the Mo/PCMO synapse array and the NbO₂ oscillator neuron.

The required parameters of the synapse device defined by the ITRS roadmap for semiconductors of 2013 included: energy consumption of <10 fJ, operating speed of > 10 Hz, endurance of 10⁹, 32 states (5‐bits), and data retention of 10 years. Also required were: analog conductance change, constant rate of change in conductance, symmetric conductance increase and decrease, and a high density 3D fabricated array.

For the Mo/PCMO device, it was found that the conductance is proportional to the device area so scaling could reduce the switching power. The potentiation and depression characteristics of the Mo/PCMO devices under identical pulse with varying voltage amplitude of pulse were shown to exhibit a gradual conductance change. The change of conductance with increasing voltage amplitude is illustrated in Figure 5.26.

The IMT oscillator neuron using NbO₂ had threshold shifting I–V characteristics as shown in the I–V curve in Figure 5.27.

When the IMT oscillator neuron was observed above the critical threshold voltage of about 1.3 V the oscillator characteristics were as shown in Figure 5.28. The pattern recognition capability of the Mo/PCMO synapse device with an NbO₂ IMT oscillator neuron was tested with a slightly noisy input pattern and the original pattern could be recovered.

Spike‐timing dependent plasticity (STDP) in conductive bridge RAM (CBRAM) devices with silicon neurons was discussed in 2016 by Arizona State University [27]. STDP is a neural process that lets biological neural networks learn by strengthening or weakening synaptic connections between neurons. This research showed the potential for using the on‐state resistance of a CBRAM according to the biological STDP rule for neuromorphic applications. The CBRAM devices were integrated with CMOS spiking neuron circuitry using back end of the line (BEOL) post‐processing. Different initial resistance values and spike durations were used.

To reduce the large power consumption and low density of traditional CMOS‐based implementations, a hybrid neuromorphic architecture was used, which consisted of analog CMOS spike‐generating circuits communicating in a massively parallel architecture using nonvolatile resistive memory devices that can mimic biological synapses. Synaptic plasticity is the ability of biological synaptic connections to be strengthened or weakened as a response to spiking activities of neurons. STDP is a neuronal learning mechanism that involves the dependence of change in synaptic connection strength based on the relative timing difference in arrival of voltage spikes generated by the neurons at the synapses.

Before CBRAMs could be used as electronic synapses, it was necessary to show that the conductance of the CBRAMs could be tuned for use with the STDP rule. On‐chip STDP behavior was shown in CBRAM devices made in the back end of the line (BEOL) on top of a chip containing a CMOS “integrate and fire” neuron circuit. Experimental evidence of true analog STDP behavior in CBRAM was shown that is similar to the biological STDP learning rule. A CBRAM compact model was used to show STDP behavior and how this behavior could be used for applications such as associative memory.

The CBRAM devices were made as a vertical stack of Ag/GeSe on top of metal pads on the chip containing the CMOS neuron circuits. Two CMOS neurons on the chip were connected using a BEOL CBRAM device. Spikes generated at the nodes of the two neurons were applied across the CBRAM device. To demonstrate STDP learning, a relative timing difference was created between the pre‐ and post‐neuron spikes. The test setup to demonstrate STDP with CMOS neurons connected using a single CBRAM synapse fabricated on chip is shown in Figure 5.29.

The chart in Figure 5.30 illustrates the experimentally measured STDP behavior with an on‐chip CBRAM device showing the change in the CBRAM conductance versus spike timing difference for different initial LRS values and a neuron spike width of 7 µs. Experimental results from the die showed an STDP‐based analog resistance change behavior in CBRAM devices that follows the biologic STDP learning function.

5.5.4 Novel RRAM Synapse Applications

The use of RRAMs in neuromorphic systems was discussed in 2014 by CEA‐LETI [5]. They showed large‐scale energy efficient neuromorphic systems based on RRAM used as stochastic binary synapses. Prototype applications were examined, such as a complex of RRAM memories in neuromorphic circuits for saving energy and increasing performance. They examined visual and auditory pattern extraction using feedforward spiking neural networks. In attempting to imitate the brain, they noted that there are 100 billion neurons in our brain and each of these neurons can have as many as 10 thousand connections to other neurons.

Various neuromorphic systems were studied. An unsupervised neuromorphic system was developed based on GeS₂/Ag CBRAM devices, which were programmed as binary synapses with a stochastic STDP learning rule optimized by a genetic evolution algorithm. Two applications were shown including: read time auditory pattern extraction and visual pattern extractions. Highly accurate audio pattern sensitivity was shown. Figure 5.31 shows the architecture for handwritten digits recognition.

A video detection rate greater than 95% and low synaptic power dissipation in the learning mode were shown. In another implementation, a spike‐based hardware convolutional neural network using HfO₂ type OxRAM was developed. Multiple binary OxRAM devices in parallel configurations were used to obtain multilevel synapses. A visual pattern recognition application, the identification of handwritten patterns as digits, was described. The architecture was inspired from the mammalian visual cortex, which is composed of two cascaded convolutional layers to associate the extracted feature maps to the 10 digit categories.

A TiO _x ‐based RRAM for neuromorphic synapse applications with 64 levels of conductance states due to an optimized interface between the metal electrodes and the TiO _x film was discussed in 2016 by POSTECH [28]. To compensate for the change in switching power with increasing pulse number, the use of fixed voltage pulses in potentiation and of fixed current pulses during depression was tried. By adopting a hybrid pulse scheme, the symmetry of conductance change was shown to be significantly improved under both potentiation and depression conditions.

The improved conductance levels and the symmetry of conductance change were directly related to enhance pattern recognition accuracy, which was confirmed by a neural network simulation. A comparison of the voltage and current pulse modes during depression and evolution of the current pulse programming power with pulse number is shown in Figure 5.32. The power increases gradually.

An Mo/TiO _x ‐based interface RRAM was developed using a hybrid pulse mode for synaptic applications. An interface switching device with 64 conductance levels was obtained by optimizing the redox reaction at the Mo/TiO _x stack. The hybrid voltage and current pulse method significantly improved the symmetry of the conductance change in both potentiation and depression, resulting in an improved pattern recognition accuracy.

Short and long term synaptic plasticity using OxRAM with noisy input data was discussed in 2016 by various French laboratories [29]. A new circuit architecture and a read/program strategy to emulate short and long term plasticity rules using OxRAM cells were discussed. The intrinsic OxRAM device switching probability at ultralow power is used to implement short term plasticity (STP) and long term plasticity (LTP) learning rules. The computational power showed that STP provided for reliable signal detection with noisy input data.

Biological synapses show both short term plasticity (STP) and long term plasticity (LTP). LTP results in stable changes of the synapses according to the timing of pre‐ and post‐synaptic spike events. STP can induce dramatic changes in synaptic weights, which enhances the discrimination ability of single neurons even though LTP characteristics have been the primary research objective of neuromorphic research. The co‐implementation of both LTP and STP with the same OxRAM technology is shown.

The emulation of LTP using Ti/HfO₂ OxRAMs cells was demonstrated. In this study, the same technology is used for emulating STP. The programming strategy is to reproduce STP using an OxRAM‐based synapse. The method involves having a synaptic weight decreased at each presynaptic spike, which periodically increased with every time interval in the absence of spikes.

The principal circuit that is used to reproduce both STP and LTP rules using nonvolatile OxRAM cells is shown in Figure 5.33. The conductance multiplication during the read operation is done using a buffer, Y(t), which modulates the read voltage for the LTP synapse Sij between the pre‐synaptic neuron (i) and the post‐synaptic neuron (j).

Long and short term plasticity learning rules are derived for reliable unsupervised learning in spiking neural networks with highly noisy input data. It was shown that the STP permits decreasing the false positives by 40% while maintaining a detection rate of 89% for a neural detection application and a low signal‐to‐noise ratio of 3.7.

5.6.1 Neural Network Circuits Using Ferroelectric Memory (FeMEM) Synapses

In June of 2013 Panasonic discussed on‐chip pattern recognition in a neural network circuit using an NVM [30]. The synapse chip of the neural network consisted of a stack of CMOS circuits and three terminal ferroelectric memristors. The analog and nonvolatile conductance range of the 3 T‐FeMEM was used as a synaptic weight to learn the matrix patterns. The original pattern can be recognized from even an incomplete pattern. A schematic cross‐section of the CMOS circuit and 3 T FeMEM is shown Figure 5.34.

Neural network circuits can effectively provide low power parallel flexible systems for learning and cognitive recognition. A synapse in which the connection weight is modified by learning controls the electrical signals between neurons. This means that continuous conductance modification is required for a biological synapse. In this case, multiple three‐terminal ferroelectric memristors are used as synapses for learning since a gate electrode can control the conductance between the other two electrodes for concurrent learning. The synaptic weight change of a 3 T‐FeMEM is shown in Figure 5.35 as a function of the relative timing of the pre‐ and post‐spikes. The spike width of V _post was 5 µs. It is similar to the synaptic weight change of a biological synapse.

5.6.2 Using the FeMEM in Neural Network Circuits

A neural network circuit was developed that included 9 neurons and 144 synapses using the CMOS circuits and 3 T‐FeMEMs. Learning and pattern recall were demonstrated on this neural network chip.

Fabrication of the 3 T‐FeMEMs was described in 2014 by Panasonic along with the procedure for integrating the 3 T‐FeMEMS into a conventional CMOS circuit [31]. The 3 T‐FeMEM circuit had a back‐gate thin film transistor structure with a stack of ZnO/Pb(Zr,Ti)O₃ (PZT)/SrRuO₃ oxide on a Pt (111) layer. The Pt layer permitted an oriented ferroelectric PZT film. PZT film polarization control was done using the gate voltage, which modulated the channel conductance nonvolatility.

The synapse function, which consisted of continuous control of the analog conductance of the memory, was done by applying pulse gate voltages. In the “integrate and fire” neuron network, the neurons communicate with each other using voltage pulses. An input voltage pulse from another neuron generates a current pulse with amplitude that is proportional to the synapse conductance. These current pulses are then integrated in a leaky integrator. When the integrated voltage reaches a threshold, the pulses are output to other neurons through their synapses and are fed back to the former synapses. All neurons operate simultaneously, resulting in parallel computation.

The two‐neuron circuit connected by a synapse composed of the 3 T‐FeMEM and a selector is shown in Figure 5.36. A neuron outputs a single rectangle pulse and a triple rectangle pulse to the following synapse. The single rectangle pulse is also fed back to the initial synapse.

Recall was demonstrated by inputting a gray pattern. The recalled pattern approached the learned pattern as the recall proceeded. It was concluded that the synapse chip with 3 T‐FeMEM is suitable for use as an artificial electronic synapse.

In August of 2014, Panasonic discussed ferroelectric artificial synapses, which were used in a spiking neural network for recognition of a multishaded image [32]. This pattern recognition is based on a spiking neural network model using 3 T‐FeMEMs as synapses. This synapse chip is formed by stacking CMOS circuits and 3 T‐FeMEMs. The conductance of the 3 T‐FeMEM is gradually changed by varying the amplitude of the applied voltage pulse. The analog and nonvolatile conductance change of the 3 T‐FeMEM is used as a synaptic weight. When an incomplete multishaded pattern is input to the neural network circuit, it automatically completes and recalls a previously learned pattern.

The 3 T‐FeRAM is used as a synapse to demonstrate on‐chip pattern recognition in a neural network circuit with multiple neurons based on a spiking neural network model. The three‐terminal structure offers the advantage of a simple learning scheme. The three‐terminal device is capable of realizing signal transmission and synapse learning concurrently in synapse connected neuron pairs.

5.6.3 Ferroelectric Tunnel Junctions in Neuromorphic Circuits

In February of 2014, a ferroelectric tunnel junction (FTJ) was used to simulate a spike‐timing dependent plasticity circuit for use in neuromorphic circuits [33]. Memristive behavior has been observed in ferroelectric tunnel junctions. In a conventional FTJ with an ultrathin ferroelectric barrier of <5 nm, tunnel resistance can be changed between ON and OFF states by switching the ferroelectric polarization. It has been shown that the change of resistance can occur continuously rather than abruptly, which defines a ferroelectric tunnel memristor (FTM). An FTM shows large OFF/ON resistance ratios and high operation speed, which is promising for use in multilevel memories and synapsis‐like circuits.

The ferroelectric tunnel memristor has resistance that can be continuously tuned by controlling the growth of domain in the ferroelectric tunnel barrier. It has an OFF/ON resistance ratio >100, high operating speed of 10 ns, multilevel storage, and neuromorphic circuits. A compact model was developed for a voltage controlled FTM based on experimental results and ferroelectric switching dynamics. Resistance measurements were taken as a function of the amplitude and duration of programming voltage pulses. Good agreement was found between simulation results and experimental measurement. An FTM‐based spike timing dependent plasticity circuit was simulated to show its use in neuromorphic circuits. If a programming voltage was applied to the ferroelectric film with a fully up‐polarized domain, the down‐polarized domains nucleate and propagate and the tunnel resistance can be calculated by the parallel resistance model.

A typical neuromorphic network for an STDP application is shown in Figure 5.37, based on a 2 × 2 crossbar. The spikes produced by neurons can tune the memristor conductance, which is the synaptic weight. The change of the weight is approximately an exponential function of the time difference between the pre‐spike and post‐spike.

For LTP, a positive voltage pulse whose width decays with the time frame is generated when the pre‐neuron spikes and a negative pulse of constant width is triggered between the top electrode and the bottom electrode when the post‐neuron spikes. For LTD, a positive voltage pulse of decaying width is produced between the top electron and the bottom electrode when the post‐neuron spikes. Meanwhile, a positive pulse of constant width occurs at the MOS gate when the pre‐neuron spikes.

A compact model of the ferroelectric tunnel memristor was based on ferroelectric switching dynamics and experimental results. The model was programmed in Verilog A language for the Cadence platform and Spectre simulator.

Synaptic plasticity can be mimicked by electronic synaptic devices. In January of 2016, ETRI discussed synaptic plasticity in ferroelectric thin film transistors where the channel conductance was gradually modulated by varying the amounts of aligned ferroelectric dipoles [34]. By using ferroelectric thin films as the gate insulator for thin film transistors (TFT), channel conductance can be defined as the synaptic plasticity, and is gradually modulated by variations in the amounts of aligned ferroelectric dipoles. Poly(vinylidene fluoride‐trifluoroethylene) [P(VDF‐TrFE)]‐poly (methyl methacrylate) (PMMA) blended films were chosen and their switching kinetics were investigated. The switching time for ferroelectric polarization was influenced by the amplitude of the applied electric field and the ratio of ferroelectric beta‐phases in P(VDF‐TrFE)‐PMMA films. The switching time of the P(VDF‐TrFE) increases when decreasing the pulse amplitude or the ratio of ferroelectric beta‐phases by including PMMA. The activation electric field was also found to increase with the blended amount of PMMA.

Synapse TFTs were made using the P(VDF‐TrFE)‐PMMA as gate insulator and In‐Ga‐Zn‐O for active channels. The drain currents of the synapse TFTs gradually increased when voltage pulse signals of a given duration were applied repeatedly. This suggested that the synaptic weights could be modulated by the number of external pulse signals and that the proposed synapse TFT could be used to mimic the operation of biosynapses.

5.8.1 Design for Synaptic Devices for Neuromorphic Computing

In June of 2014, ASU, Stanford, and the University of Pennsylvania discussed design considerations for synaptic devices for neuromorphic computing [41]. Two terminal RRAMs with electrically triggered resistance modulation were proposed as synaptic devices for neuromorphic computing. These included phase change memory (PCM), resistive RAM, and CB‐RAM. This study considered design considerations of synaptic devices for plasticity and learning. An ideal synaptic device should have characteristics like: dimension, energy consumption, operation frequency, and dynamic range that are scalable to biological systems with comparable complexity.

The HfOx RRAM is considered a good candidate for large scale integration of a neural network since synaptic devices with scalability to sub‐10 nm are preferred and an HfO _x RRAM cell has been demonstrated as 10 nm × 10 nm. The energy consumption per synaptic event is around 1–10 fJ and some HfO _x RRAM have already shown sub‐pJ energy consumption. Brain‐like systems can operate as slow as 1–10 Hz, which gives the 10 ns operating RRAM a lot of flexibility to design trade‐offs for energy consumption.

Synaptic plasticity characteristics in biological synapses show analog‐like behavior with many synaptic weight states. In general, multilevel states bring advantages to networking. The RRAM has level programmable RESET. A 10 year data retention is required along with about 10⁹ endurance cycles. A disadvantage of the RRAM and the CB‐RAM is variability in the resistance modulation, which will require further material and device engineering.

Using a RRAM crosspoint array for dictionary learning was discussed in 2014 by Arizona State University [42]. The array had a neurophysics‐inspired parallel architecture, which performed matrix product and dictionary update in a fully parallel fashion at a speed that is independent of the matrix dimension. The system was implemented in 65 nm CMOS technology using an RRAM memory cell for high speed unsupervised dictionary learning. It performed more than 3000 times faster than state‐of‐the‐art software, which enabled real‐time feature extraction on a single chip.

The resistive crosspoint array structure was used since the crosspoint mimics the structural map of a neural system. At each crosspoint, the conductance of a memory cell represents the synapse weight, as shown the graph in Figure 5.42 of conductance change versus voltage pulse width. RRAM is used due to its nonvolatility, high integration density, and low power consumption. Analogous to a synapse device, the conductance of an RRAM cell is increased (decreased) by a positive (negative) voltage pulse.

Suppressing intrinsic variations during the synaptic training process in metal‐oxide synaptic RRAMs was discussed in October of 2014 by Peking University [43]. These variations can affect the accuracy of the neuromorphic computations. The influence was investigated of resistance variations on metal‐oxide RRAM‐based neuromorphic computation systems. Atomic DMC (Dynamic Monte‐Carlo) simulations were performed to study the random migration of oxygen vacancies that are responsible for the origin of the variations. A new methodology was suggested to improve the robustness of the metal‐oxide RRAM‐based neuromorphic computation system.

Neuromorphic computing, which has features of parallelism, adaptivity to complex input information, and error tolerance, was discussed by Stanford University in 2015 [44]. The synapse in a neuromorphic system requires high integration density and low energy consumption, which are properties of oxide‐based RRAM. An optimized oxide‐based RRAM synaptic device was designed and applied to the performance of a neuromorphic visual system. The intrinsic variation of the RRAM synaptic devices was suppressed to achieve the high recognition accuracy and efficiency required in a neuromorphic visual system.

5.8.2 Using RRAMs in Various Neuromorphic Computing Applications

Neuromorphic computation is used more effectively than von Neumann systems in applications such as image and auditory processing. In December of 2015, Peking University and Sandisk discussed an optimized learning method for grayscale image recognition in an RRAM‐based analog neuromorphic system [45]. An analog neuromorphic visual system is developed using a fabricated RRAM array as a synapse network. A new training method is used to optimize the performance of the system by using segmented synaptic behavior. This segmented behavior is due to the dynamics of the conductive filament. Initially the CF thins near the top electrode and resistance increases slowly. When the CF is just ruptured the electric field intensity increases due to the small tunneling gap, which results in faster resistance change. As the gap enlarges, the resistance slowly increases with the resistance increase slowing and then finally saturating.

The experimental results using the segmented method indicated that learning accuracy was improved from 77.83 to 91.32% over a nonsegmented system, energy consumption was decreased by more than two orders of magnitude, and learning efficiency improved over traditional learning schemes.

Figure 5.43 shows a neuromorphic system consisting of CMOS neurons and RRAM synapses. In this system the RRAM devices serving as synapses connect the CMOS neurons at the different layers. The conductance of the RRAM synapse represents the strength of the connection between two neurons. This can be modified during the training process by using SET and RESET pulses to change the conductivity of the RRAM.

In December of 2016, Arizona State University and Tsinghua University discussed using a binary neural network with RRAM synaptic devices for classification and on‐line training [46]. A large scale neural network was made for use in image recognition. The goal was to find a methodology to binarize the neural network parameters with the intent to reduce the precision of weights and neurons to 1‐bit for classification and less than 8‐bit for on‐line training. An experimental binary neural network was demonstrated on Tsinghua’s 16 Mb RRAM macro chip made in 130 nm CMOS. The system performance on the MNIST handwritten digital dataset achieved 96.5% accuracy for both classification and on‐line training and nearly 97% accuracy by ideal software implementation.

5.8.3 Large RRAM Array Design for Neuromorphic Computing

Various issues with designing large RRAM arrays in neuromorphic computing applications were discussed in 2016 by IBM, POSTECH, and EPFL [47]. In these neuromorphic schemes, device conductance serves as a synaptic weight allowing the multiply‐accumulated operation in these algorithms to be performed using the weight data. An illustration of neuromorphic non‐Von Neumann computing is shown in Figure 5.44. Here neurons activate each other through networks of programmable synaptic weights, which can be implemented using dense crossbar arrays of resistive RAMS with variable resistance as 1T1R cells that emulate synapses coupling “neuron”‐controlled selector device pairs.

This paper explored the use of NVM and other analog‐type devices for artificial neural networks trained with a back‐propagation algorithm. The advantage of phase change memory synapses over the speed and power of GPU‐based training had been previously shown and this work assessed the impact of undesirable time‐varying conductance change and the trade‐offs in designing peripheral circuitry for artificial neural networks.

The benefit of performing computations at the location of the data is in both power and speed.

Another benefit is in the security of data when it does not need to be stored in the cloud but is processed locally. The computations of training using NVM‐based synapses must be competitive with that using CPUs or GPUs.

Any on‐chip accelerator should be applicable toward networks of different types, such as fully connected deep neural nets or convolutional NN or for networks of different shapes. It was shown that for speed and power of on‐chip machine learning, nonvolatile memory‐based synapses can potentially offer lower power and faster training than GPU‐based training for both large and small networks. A critical factor is the design of area‐efficient read/write circuitry so that many copies of this circuitry are able to operate in parallel.

Using 2 PCM devices per synapse, a three‐layer perceptron with 164 885 synapses was trained with back‐propagation on a subset of the MNIST database of handwritten digits using a modified weight update rule compatible with NVM + selector crossbar arrays. It was shown that this weight update modification does not degrade the high accuracies that a three‐layer network inherently delivers when trained in software. Nonlinearity and asymmetry in the PCM conductance response limited both training and test accuracy. The asymmetry between the gentle conductance increases of PCM partial SET and the abruptness of PCM RESET was lessened by an occasional RESET strategy, which could be both infrequent and inaccurate. Tolerance results showed that all NVM‐type ANN could be expected to be highly resilient to random effects such as variability, yield, and stochasticity, but very sensitive to gradient effects that act to steer all synaptic weights. These observations were extended to assess the impact of undesigned, time‐varying conductance change including drift and leakage of analog CMOS capacitors. A feature of PCM is resistance drift, which is continued relaxation of the material in the amorphous state. The drift is toward an increase in resistance. A potential solution for this issue is a periodic RESET.

PCMO is a nonfilamentary resistance change material in which conductive response was also studied. Resistive switching in PCMO devices is caused by the slow and gradual drift of oxygen ions and vacancies in the polycrystalline PCMO layer. PCMO NVMs show gradual SET and RESET characteristics, but, unlike PCM, there is no need to stop training and perform an occasional RESET operation. RRAM devices based on PCMO can be considered as potentially, providing both a gradual conductance increase and conductance decrease.

5.8.4 Advantages of RRAM over SRAM Crossbar Arrays in Matrix Multiplication

In October of 2015, Sandia National Labs discussed using RRAM crossbar arrays to process large amounts of data for brain‐type computing [48]. Analog computation on a crossbar provides fundamental energy scaling advantages over digital memories. The two key computational kernels that are more efficient on a crossbar include: performing a parallel read or a vector matrix multiply and performing a parallel write where every weight is programmed based on the outer product of the row and column inputs. These two computational kernels comprise the basis of neuromorphic algorithms.

For a parallel analog matrix multiply each column of the crossbar performs a vector dot product for a column. Inputs are represented by a voltage or length of a voltage pulse. Weights are represented by the RRAM conductances. The multiplication is done by summing currents. The minimum energy to read the crossbar is determined by the thermal noise of each RRAM.

For a larger crossbar or a higher voltage due to access devices, the energy will be capacitance limited. Even for a capacitance limited read energy, however, the device will still be more energy efficient than a matrix stored in an SRAM array since SRAMs need to be read out one row or word‐line at a time and the associated circuitry will need to be charged N times for N rows. In an analog RRAM crossbar, everything can be done in parallel so that the circuitry needs only to be charged once. The conclusion was that the energy to perform a parallel read or parallel write on an analog N × N RRAM crossbar array scales as O(N²) while a digital implementation scales as O(N³).