The MicroProcessor Unit (MPU) lies at the heart of modern digital systems. This programmable logic component executes instructions sequentially from a program stored in the main memory. The previous volume presented the hardware aspects of this component.

This fourth volume presented the software aspects of how a microprocessor operates. The programmer will refer to Instruction Set Architecture (ISA, see § V1-3.5), which specifies the type of architecture (General-Purpose Registers (GPR), stack, etc.), the memory addressing characteristics (alignment or not, storage order, access format, addressing capacity), available address modes, operand characteristics (number, type, format and representation (i.e. encoding) and, of course, instructions (family, mnemonic, syntax, semantics, authorized and encoding address modes)) and, finally, data and address path formats.

The first two chapters studied the three main characteristics of an ISA. We then presented instruction coding and format, addressing modes and the instruction set in the form of classes with, in particular, the multimedia extension to modern microprocessors.

The third chapter focused on additional concepts associated with instruction sets and execution. It first of all studied what illegal, invalid, reserved and trusted instructions were. It then presented the concepts of memory alignment, the orthogonality and symmetry of the instruction set and pure, relocatable and reentrant code. It then discussed the subjects of execution time, memory occupation, execution modes, portability and virtualization. This chapter ended with the important aspects of hardware and software compatibilities, execution performance measurement and the criteria for choosing a microprocessor.

Subroutine call mechanisms and interrupt mechanisms were then studied respectively in the last two chapters. The first made it possible to implement a function or procedure in high-level languages. The interrupt is a similar mechanism. It was originally invented to process an overflow problem. It was then used to manage Input/Output (I/O) in an optimized way by avoiding the polling technique. A classification was proposed following the original request criteria, external or internal, and the operation of these hardware and software interrupts was detailed. The interrupt mechanism is used in a generalized way in modern Operating System (OS) and embedded systems.

As we can therefore see with these last two volumes, the design of the microprocessor requires the competency of multiple domains ranging from micro-electronic technology to functional architecture via Boolean algebra and the design of logic circuits. For the software designer in relation to the hardware aspect, an equilibrium will exist between the different logical sub-sets depending on the applications targeted. For scientific calculation applications, some mathematical instructions could be used. For database applications, complex addressing modes will be used. Two trends have therefore clashed, in design and manufacturing, from the beginning of the 1980s. These are the CISC and RISC approaches (respectively Complex/Reduced Instruction Set Computer, this will be covered in a future book by the author on microprocessors). The CISC architecture favored complexity of the instruction set and therefore of the Control Unit (CU), while the RISC architecture favored registers and simplified the internal structure of the CU (Control Unit) and the Integer Unit (IU).

For more information on this component, a special set of Proceedings of the IEEE is dedicated to it (Patt 1995). See also IEEE (1996).

The following volume will present the software tools for low-level development, as well as hardware and software aspects of debugging applications. It will end with a study of the architectures of the first microcomputers.

NOTE.– The concepts presented in this book will be complemented as new ones are introduced. The second book will focus on the modern aspects of processors from 1980 to 1990, in particular virtual memory and parallelism of execution. The third book will focus on multicore parallelism.