Acronyms
This section includes all of the acronyms used in this volume. They range across chapters.
General
A
| A | Address |
| AAPCS | Procedure Call Standard for the Arm® Architecture |
| AB | Available Bus (MC6809) |
| ABI | Application Binary Interface |
| ABM | Advanced Bit Manipulation (AMD technology) |
| ABT | ABorT |
| ACU | Address Computation Unit (synonyms: AGU, DAG) |
| AES | Advanced Encryption Standard |
| AES NI | AES New Instructions |
| AGU | Address Generation Unit (synonyms: ACU, DAG) |
| ALGOL | ALGOrithmic Language |
| AP | Application Processor |
| APCS | Arm® Procedure Call Standard |
| APIC | Advanced PIC (Intel) |
| ASCII | American Standard Code for Information Interchange |
| ASIP | Application-Specific Instruction set Processor |
| ASL | Arithmetic Shift Left |
| ASP | Application-Specific Processor |
| ATPCS | Arm® TPCS |
| AVX | Advanced Vector eXtensions (Intel technology) |
| AXP | Almost eXactly PRISM |
B
| b | bit (cf.. BIT) |
| B | Byte |
| BCD | Binary-Coded Decimal |
| BE | Big Endian |
| BERT | Branch Effect Reduction Technique |
| BIOS | Basic Input/Output System |
| BIT | BInary digiT or Binary digIT |
| BMI | Bit Manipulation Instructions (Intel technology) |
| BP | Base Pointer (Intel) |
| BRAF | Block-Repeat-Active Flag |
| BRC | Block Repeat Counter |
| BS | Bus Status (MC6809) |
| BSP | BootStrap Processor |
| BSS | Block Started by Symbol (UNIX) |
| BTA | Branch Target Address |
| BTI | Branch Target Instruction |
C
| cc | condition code |
| CF | Carry Flag |
| CISC | Complex Instruction Set Computer |
| COBOL | COmmon Business Oriented Language |
| COP | Calculator-Oriented Processor (NS) |
| COPS | Controller-Oriented Processor System (NS), formerly COP |
| COSMAC | Complementary Symmetry Monolithic Array Computer |
| CPL | Current Privilege Level |
| CPSR | Current Program Status Register |
| CPU | Central Processing Unit |
| CR | Condition Register |
| CRC | Cyclic Redundancy Check |
| CS | Code Segment (Intel x86) |
| CTR | CounT Register |
| CU | Control Unit |
| CVT | ConVerT (AMD and Intel) |
D
| DAG | Data Address Generator (synonyms: ACU, AGU) |
| DFP | Decimal Floating-Point |
| DI | Destination Index (Intel x86) |
| DIF | Decimal-In-Frequency |
| DIL | Dual-In-Line |
| DIP | DIL Package |
| DISP | DISPlacement (i.e. offset) |
| DIT | Decimal-In-Time |
| DLL | Dynamic Link Library |
| DP | Direct Page |
| DRAM | Dynamic RAM |
| DXP | Decimal Fixed-Point |
| DYSEAC | Second SEAC |
E
| EA | Effective Address |
| EA | Empty Ascending |
| EBCDIC | Extended Binary-Coded Decimal Interchange Code (IBM) |
| ECC | Error Checking and Correcting/ Error-Correcting Code |
| ED | Empty Descending |
| EDC | Error-Detecting Circuit/Code |
| EDSAC | Electronic Delay Storage Automatic Calculator |
| EF | Entire Flag (MC6809) |
| EIC | External Interrupt Controller |
| EN | ENable |
| EOR | Exclusive OR (cf. EXOR and XOR) |
| EPC | Exception Program Counter (MIPS) |
| EQ | EQual |
| EXOR | EXclusive OR (cf. EOR and XOR) |
F
| FA | Full Ascending |
| FC | Function Code (MC68000) |
| FD | Full Descending |
| FFT | Fast Fourier Transform |
| FIFO | First In, First Out |
| FIQ | Fast Interrupt reQuest mode (ARM) |
| FIR | Finite Impulse Response |
| FIRQ | Fast IRQ |
| FMA | Fused Multiply-Accumulate |
| FORTRAN | FORmula TRANslation |
| FP | Floating Point |
| FPGA | Field-Programmable Gate Array |
| FPP | FP Processor |
| FPU | FP Unit |
| FW | FirmWare |
G
| GE | Greater than or Equal |
| GP FPP | General-Purpose FPP |
| GPP | General-Purpose Processor |
| GPR | General-Purpose Register |
| GT | Greater Than |
H
| HLL | High-Level (programming) Language |
| HW | HardWare |
| HWP | Heavy-Weight Process |
I
| IA | Intel Architecture |
| iAPX | Intel Advanced Performance Architecture |
| ICC | Interrupt Controller Communications |
| ID | Identification |
| IDT | Interrupt Descriptor Table (Intel) |
| IDTR | IDT Register (Intel) |
| IE | individual Interrupt Enable (PACE) |
| IF | Interrupt enable Flag |
| IIC | Internal Interrupt Controller |
| ILP | Instruction-Level Parallelism |
| INT | INTerrupt |
| INTA | INTerrupt Acknowledge |
| INTR | INTerrupt Request |
| I/O | Input/Output |
| IO | Input/Output (rarely used) |
| IOAPIC | I/O APIC |
| IOPL | I/O Privilege Level (flag) |
| IP | Instruction Pointer (Intel) (cf. PC) |
| IPL | Interrupt Priority Level (MC68000) |
| IR | Index Register |
| IRQ | Interrupt Request |
| IS | Instruction Set |
| ISA | IS Architecture |
| ISP | Instruction Set Processor |
| ISR | Interrupt Service Routine |
| ISSE | Intel SSE (AMD) |
| ISSE | Internet SSE (Intel) |
| IT | InTerruption (cf. INT) |
| IVT | Interrupt Vector Table |
J
| JTAG | Joint Test Action Group |
| JVM | Java Virtual Machine |
K
| KNI | Katmai New Instructions (Intel SSE1) |
L
| LA | end-of-Loop Address |
| LAPACK | Linear Algebra PACKage |
| LC | Loop Counter |
| LE | Less than or Equal/less or equal |
| LE | Little Endian |
| LE | Loop End |
| LED | Light-Emitting Diode |
| LEM | Lunar Excursion Module |
| LF | Loop Flag |
| LGC | LEM Guidance Computer |
| LGE | Less, Greater and Equal |
| LIFO | Last In, First Out |
| LINPACK | LINear Algebra PACKage |
| LINT | Local INT (APIC, Intel) |
| LIW | Long Instruction Word |
| LK | LinK (bit) |
| LR | Link Register (ARM) |
| LS | Loop Start |
| LSb | Least Significant bit |
| LSB | Least Significant Byte |
| LSL | Logical Shift Left |
| LSR | Logical Shift Right |
| LT | Less Than |
| LUT | LookUp Table |
| LWP | Light-Weight Process |
M
| MAC | Multiply-and-ACcumulate |
| MAX | Multimedia Acceleration eXtensions (PA-RISC 2.0) |
| MCS | Micro Computer Set (Intel) |
| MCU | MicroComputer Unit |
| MCU | MicroController Unit (preferable) |
| MDMX | MIPS Digital Media eXtensions |
| MIPS | Microprocessor without Interlocked Pipeline Stages from MIPS Technologies (then called MIPS Computer Systems) |
| MMR | Memory-Mapped Register |
| MMU | Memory Management Unit |
| MMX | MultiMedia eXtensions (Intel technology) |
| MOS | Metal-Oxide Semiconductor |
| MP | MultiProcesseur (MultiProcessor) |
| MPU | MicroProcessor Unit |
| MSb | Most Significant bit |
| MSB | Most Significant Byte |
| MSW | Machine Status Word |
| MUX | MUltipleXer |
| MVI | Motion Video Instructions (DEC Alpha) |
N
| N | Negative (flag) |
| NB | Natural Binary (cf. NBC) |
| NBC | Natural Binary Code (cf. NB) |
| NE | Not Equal |
| NI | New Instruction |
| NMI | Non-Maskable Interrupt |
| NNI | Nehalem New Instructions (Intel SSE4) |
| NOP | No Operation |
| NOS | Next-On-Stack |
O
| OF | Overflow Flag |
| OS | Operating System |
P
| PA | Physical Address |
| PA | Precision Architecture (HP) |
| PACE | Processing And Control Element (NS) |
| PA-RISC | Precision Architecture-RISC (HP) |
| PC | Personal Computer |
| PC | Program Counter (cf. IP) |
| PCR | Program Counter Register (MC6809) |
| PCS | Program Counter Stack |
| PDP | Programmable Data Processor (DEC) |
| PE | Protected Mode Enable |
| PIC | Peripheral Interface Controller (General Instrument) |
| PIC | Programmable Intelligent Computer (General Instrument) |
| PIC | Position-Independent Code |
| PIC | Programmable Interrupt Controller |
| PIE | Position-Independent Executable |
| PNI | Prescott New Instructions (Intel SSE3) |
| POWER | Performance Optimization With Enhanced RISC |
| PowerPC | POWER Performance Computing |
| PR | Predicate Register |
| PRISM | Parallel Reduced Instruction Set Machine (DEC Alpha AXP) |
| PSR | Processor Status Register |
R
| RAM | Random Access Memory |
| RC | Repeat Counter |
| RCA | Reverse-Carry Arithmetic |
| RCL | Rotate through Carry Left |
| RCR | Rotate through Carry Right |
| RE | Repeat End Address register |
| REA | Repeat End Address |
| REX | Register Extension (AMD, Intel) |
| RF | Register File |
| RGB | Red–Green–Blue |
| RIP | Instruction Pointer Register (Intel x86-64) |
| RISC | Reduced Instruction Set Computer |
| R/M | Register/Memory |
| R/M | modify Register or Memory |
| RMW | Read-Modify-Write |
| ROL | ROtate Left |
| ROLC | Rotate left through (the) carry (flag) (IEEE Std 694-1985) |
| ROM | Read-Only Memory |
| ROR | ROtate Right |
| RORC | Rotate right through (the) carry (flag) (IEEE Std 694-1985) |
| RS | Register Select |
| RS | Repeat Start Address register |
| RSA | Repeat Start Address |
| RSM | Resume from System Management Mode |
| RST | ReSeT |
S
| SAL | Shift Arithmetic Left |
| SAR | Shift Arithmetic Right |
| SEAC | Standards Electronic Automatic Computer |
| SEGT | SEGment Trap (request) |
| SHL | SHift arithmetic Left |
| SHLA | SHift Left Arithmetical (IEEE Std 694-1985) |
| SHLD | Shift Left Doublet |
| SHR | SHift logical Right |
| SHRA | SHift Right Arithmetical (IEEE Std 694-1985) |
| SHRD | Shift Right Double |
| SI | Source Index (Intel x86) |
| SIB | Scale-Index-Base |
| SIMD | Single Instruction stream/Multiple Data stream |
| SMI | System Management Interrupt |
| SMM | System Management Mode |
| SMP | Symmetric (shared memory) MultiProcessing |
| SP | Stack Pointer (x86 Intel) |
| SPARC | Scalable Processor ARChitecture |
| SR | Shift Register |
| SR | Status Register |
| SSE | Streaming SIMD Extensions (Intel) |
| SSSE3 | Supplemental SSE3 (Intel) |
| SVC | SuperVisor Call |
| SW | SoftWare |
| SWI | SoftWare Interrupt |
| SYS | SYStem |
T
| TB | Test and Branch |
| TBM | Trailing Bit Manipulation (AMD technology) |
| TF | Trap Flag |
| TLB | Translation Lookaside Buffer |
| TNI | Tejas New Instructions (SSSE3) |
| TOS | Top-Of-Stack |
| TPCS | Thumb® Procedure Call Standard |
| TSS | Task State Segment |
U
| UCS | Universal Character Set |
| UND | UNDefined |
| UNICODE | UNIversal CODE |
| UNIVAC | Universal Automatic Computer |
| URL | Uniform Resource Locator |
| USB | Universal Serial Bus |
| USR | USeR |
| UTF | Unicode (or UCS) Transformation Format |
V
| VAX | Virtual Addressed eXtended (DEC) |
| VEX | Vector EXtensions |
| VHDL | VHSIC Hardware Description Language |
| VHSIC | Very High-Speed Integrated Circuit |
| VIC | Vectored Interrupt Controller (ARM) |
| VIS | Visual Instruction Set |
| VLIW | Very LIW |
| VM | Virtual Machine |
| VM | Virtual Memory |
| VMM | Virtual Machine Monitor |
| VMX | Vector Multimedia Extension |
X
| X | eXtend bit (MC68000) |
| XOP | eXtended OPerations |
| XOR | eXclusive OR (cf. EOR and EXOR) |
Z
| ZF | Zero Flag |
Miscellaneous
| μC | Microcontroller |
| μC | Microcomputer |
| μP | Microprocessor |
| 2D or 2-D | Two-dimensional |
| 3D or 3-D | Three-dimensional |
Units of measurement or unit prefixes
| CPI | (clock) Cycles Per Instruction |
| DMIPS | Dhrystone MIPS |
| FLOPS | Floating-Point Operations Per Second |
| iCOMP | Intel COmparative Microprocessor Performance |
| IPC | Instructions Per Cycle |
| IPS | Instructions Per Second |
| k | kilo (= 1000) |
| kWIPS | kiloWhetstone Instructions Per Second |
| M | mega (= 106) |
| MACS | Multiply-and-ACcumulates per Second |
| MFLOPS | megaFLOPS = Million FLoating-point Operations Per Second |
| MIPS | Million Instructions Per Second |
| MWIPS | Millions of or Mega-Whetstone Instructions Per Second |
| SPECflop | SPEC floating point |
| SPECfpxx | System Performance Evaluation Corporation floating point, xx = year |
| SPECintxx | System Performance Evaluation Corporation integer, xx = year |
Electrical characteristics
| PD | dissipated electrical power |
Temporal characteristics
| texec | execution time |
| Tclock | clock period |
Business or body
| ACM | Association for Computing Machinery |
| AFISI | Association Française d'Ingénierie des Systèmes d'Information (French Association of Information Systems Engineering) |
| AIEE | American Institute of Electrical Engineers |
| AMD | Advanced Micro Devices, Inc. |
| ANSI | American National Standards Institute |
| ARM | Acorn RISC Machine (formerly Advanced RISC Machines) |
| AT&T | American Telephone and Telegraph Company |
| CSG | Commodore Semiconductor Group |
| DEC | Digital Equipment Corporation |
| HP | Hewlett-Packard |
| IBM | International Business Machines Corporation |
| IEC | International Electrotechnical Commission |
| IEEE | Institute of Electrical and Electronics Engineers |
| IRE | Institute of Radio Engineers |
| ISO | International Organization for Standardization |
| ISSCC | IEEE International Solid-State Circuits Conference |
| JEDEC | Joint Electron Device Engineering Council (Solid-State Technology Association) |
| MIT | Massachussets Institute of Technology |
| MPR | Microprocessor Report |
| NBS | National Bureau of Standards |
| NPL | National Physical Laboratory |
| NS | National Semiconductor |
| SGI | Silicon Graphics, Inc. |
| SPEC | Standard Performance Evaluation Corporation (formerly Cooperative) |
| TI | Texas Instruments |
| WDC | Western Digital Corporation, Western Digital Center |
| WTL | WeiTek Corporation |
Trademark (TM)
| i486 | Intel Corporation |
| Pentium | Intel Corporation |
| WeiTek | WeiTek Corporation |
Registered trademark (®)
| AMD | AMD |
| AT&T | AT&T |
| AVR | Microchip |
| Intel | Intel |
| Pentium | Intel |
| PIC | Microchip Technology |
| UNIX | AT&T |
| Xeon | Intel |
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