Home Page Icon
Home Page
Table of Contents for
Cover
Close
Cover
by Naim Dahnoun
Multicore DSP
Cover
Title Page
Preface
Acknowledgements
Foreword
About the Companion Website
1 Introduction to DSP
1.1 Introduction
1.2 Multicore processors
1.3 Key applications of high‐performance multicore devices
1.4 FPGAs, Multicore DSPs, GPUs and Multicore CPUs
1.5 Challenges faced for programming a multicore processor
1.6 Texas Instruments DSP roadmap
1.7 Conclusion
References
2 The TMS320C66x architecture overview
2.1 Overview
2.2 The CPU
2.3 Single instruction, multiple data (SIMD) instructions
2.4 The KeyStone memory
2.5 Peripherals
2.6 Conclusion
References
3 Software development tools and the TMS320C6678 EVM
3.1 Introduction
3.2 Software development tools
3.3 Hardware development tools
3.4 Laboratory experiments based on the C6678 EVM: introduction to Code Composer Studio (CCS)
3.5 Loading different applications to different cores
3.6 Conclusion
References
4 Numerical issues
4.1 Introduction
4.2 Fixed‐ and floating‐point representations
4.3 Dynamic range and accuracy
4.4 Laboratory exercise
4.5 Conclusion
References
5 Software optimisation
5.1 Introduction
5.2 Hindrance to software scalability for a multicore processor
5.3 Single‐core code optimisation procedure
5.4 Interfacing C with intrinsics, linear assembly and assembly
5.5 Assembly optimisation
5.6 Software pipelining
5.7 Linear assembly
5.8 Avoiding memory banks
5.9 Optimisation using the tools
5.10 Laboratory experiments
5.11 Conclusion
References
6 The TMS320C66x interrupts
6.1 Introduction
6.2 The interrupt controller
6.3 Laboratory experiment
6.4 Conclusion
References
7 Real‐time operating system: TI‐RTOS
7.1 Introduction
7.2 TI‐RTOS
7.3 Real‐time scheduling
7.4 Dynamic memory management
7.5 Laboratory experiments
7.6 Conclusion
References
8 Enhanced Direct Memory Access (EDMA3) controller
8.1 Introduction
8.2 Type of DMAs available
8.3 EDMA controllers architecture
8.4 Parameter RAM (PaRAM)
8.5 Transfer synchronisation dimensions
8.6 Simple EDMA transfer
8.7 Chaining EDMA transfers
8.8 Linked EDMAs
8.9 Laboratory experiments
8.10 Conclusion
References
9 Inter‐Processor Communication (IPC)
9.1 Introduction
9.2 Texas Instruments IPC
9.3 Notify module
9.4 MessageQ
9.5 ListMP module
9.6 GateMP module
9.7 Multi‐processor Memory Allocation: HeapBufMP, HeapMemMP and HeapMultiBufMP
9.8 Transport mechanisms for the IPC
9.9 Laboratory experiments with KeyStone I
9.10 Laboratory experiments with KeyStone II
9.11 Conclusion
References
10 Single and multicore debugging
10.1 Introduction
10.2 Software and hardware debugging
10.3 Debug architecture
10.4 Advanced Event Triggering
10.5 Unified Instrumentation Architecture
10.6 Debugging with the System Analyzer tools
10.7 Instrumentation with TI‐RTOS and CCS
10.8 Laboratory sessions
10.9 Conclusion
References
11 Bootloader for KeyStone I and KeyStone II
11.1 Introduction
11.2 How to start the boot process
11.3 The boot process
11.4 ROM Bootloader (RBL)
11.5 Boot process
11.6 Laboratory experiment 1
11.7 Laboratory experiment 2
11.8 TFTP boot with a host‐mounted Network File System (NFS) server – NFS booting
11.9 Conclusion
References
12 Introduction to OpenMP
12.1 Introduction to OpenMP
12.2 Directive formats
12.3 Forking region
12.4 Work‐sharing constructs
12.5 Environment variables and library functions
12.6 Synchronisation constructs
12.7 OpenMP accelerator model
12.8 Laboratory experiments
12.9 Conclusion
References
13 Introduction to OpenCL for the KeyStone II
13.1 Introduction
13.2 Operation of OpenCL
13.3 Command queue
13.4 Kernel declaration
13.5 How do the kernels access data?
13.6 OpenCL memory model for the KeyStone
13.7 Synchronisation
13.8 Basic debugging profiling
13.9 OpenMP dispatch from OpenCL
13.10 Building the OpenCL project
13.11 Laboratory experiments
13.12 Conclusion
References
14 Multicore Navigator
14.1 Introduction
14.2 Navigator architecture
14.3 Complete functionality of the Navigator
14.4 Laboratory experiment
14.5 Conclusion
References
15 FIR filter implementation
15.1 Introduction
15.2 Properties of an FIR filter
15.3 Design procedure
15.4 Laboratory experiments
15.5 Conclusion
References
16 IIR filter implementation
16.1 Introduction
16.2 Design procedure
16.3 Coefficients calculation
16.4 IIR filter implementation
16.5 Laboratory experiment
16.6 Conclusion
Reference
17 Adaptive filter implementation
17.1 Introduction
17.2 Mean square error
17.3 Least mean square
17.4 Implementation of an adaptive filter using the LMS algorithm
17.5 Implementation using linear assembly
17.6 Implementation in C language with compiler switches
17.7 Laboratory experiment
17.8 Conclusion
References
18 FFT implementation
18.1 Introduction
18.2 FFT algorithm
18.3 FFT implementation
18.4 Laboratory experiment
18.5 Conclusion
References
19 Hough transform
19.1 Introduction
19.2 Theory
19.3 Limits of r and θ and θ
19.4 Hough transform implementation
19.5 Laboratory experiment
19.6 Conclusion
References
20 Stereo vision implementation
20.1 Introduction
20.2 Algorithm for performing depth calculation
20.3 Cost functions
20.4 Implementation
20.5 Conclusion
References
Index
End User License Agreement
Search in book...
Toggle Font Controls
Playlists
Add To
Create new playlist
Name your new playlist
Playlist description (optional)
Cancel
Create playlist
Sign In
Email address
Password
Forgot Password?
Create account
Login
or
Continue with Facebook
Continue with Google
Sign Up
Full Name
Email address
Confirm Email Address
Password
Login
Create account
or
Continue with Facebook
Continue with Google
Next
Next Chapter
Table of Contents
Add Highlight
No Comment
..................Content has been hidden....................
You can't read the all page of ebook, please click
here
login for view all page.
Day Mode
Cloud Mode
Night Mode
Reset