2.2.1 Cross paths

Cross paths enable linking of one side of the CPU (e.g. data path A) to the other (e.g. data path B). These are shown in bold arrows in Figure 2.5. Although the cross paths are useful in terms of the flexibility in using units with two or multiple operands from both sides of the CPU, there are restrictions which are discussed in this section.

2.2.1.2 Address cross paths

The addresses generated by the data unit .D1 and .D2 can be sent to either the data address path DA1 or the data address path DA2, as shown in bold arrows in Figure 2.5. The advantages of using an address cross path are to be able to generate the address using one register file, and to access the data from the other register file as illustrated in Figure 2.6. Here again, there are only two cross paths for each execute packet and the following points should be observed:

• Only one address cross path per direction per execute packet is allowed.
• When an address cross path is used, the destination register for the load (LD) instructions and the source register for the store (ST) instructions should come from the opposite side of the unit (see Figure 2.6), or simply the register pointers must come from the same side of the .D unit used.
• If both .D units are to be used, then either none or both of the address cross paths should be used.

2.2.2 Register file A and file B

This processor is a reduced instruction set computer (RISC)‐like processor, and all operands are specified in registers except for the n‐bit constants. There are two register files each containing 32 32‐bit registers.

2.2.3 Functional units

The four types of units (.M, .L, .S and .D) are designed to perform different operations. However, some operations can be performed with different units; for instance, the ADD instruction can be performed by the .L units, the .S units or the .D units. The TMS320C66x DSP CPU and Instruction Set Reference Guide [5] should be consulted before using an instruction.

The assembly syntax for this DSP core is as follows:

Example:

|B0| ADD.S1 A0,A1,A2 ; comments

where:

• |B0|: If B0 is not equal to zero, then execute the instruction ‘ADD .S1 A0,A1,A2’.
• ADD .S1 A0,A1,A2: Add A0 and A1, and store the result to register A2.
• ; comments: Used for comments and therefore not assembled.

|!B0| ADD.S1 A0,A1,A2

2.2.3.3 .M units

There are two hardware multiplier units, .M1 (for data path 1) and .M2 (for data path 2), that can perform fixed‐point or floating‐point multiplications as shown in Table 2.5 and Table 2.6. The .M units support 128‐bit.

Four 32 × 32 bit multiplies (e.g. QMPY32) Four 16 × 8 bit multiplies (e.g. DDOTP4) Two 16 × 16 bit multiplies (e.g. MPY2) 16 × 32 bit multiplies (e.g. MPYHI) Four 8 × 8 bit multiplies (e.g. MPYU4) Four 8 × 8 bit multiplies with add operations (e.g. DOTPU4) Four 16 × 16 multiplies with add/subtract capabilities (e.g. DOTP4H) One 16 × 16 bit complex multiply with or without rounding (e.g. CMPY/CMPYR) A 32 × 32 bit complex multiply with rounding (e.g. CMPY32R1) Complex multiply with rounding and conjugate, signed complex 16‐bit (16‐bit real/16‐bit imaginary) (e.g. CCMPY32R1) Support for Galois field multiplication (e.g. GMPY) One multiplication of a [1 × 2] complex vector by a [2 × 2] complex matrix per cycle with or without rounding capability (e.g. CMATMPY) One multiplication of the conjugate of a [1 × 2] vector with a [2 × 2] complex matrix (e.g. CCMATMPY)

One single‐precision multiply each cycle One double‐precision multiply every four cycles One double‐precision multiply per cycle; also reduces the number of delay slots from 10 to 4 One multiplication of two single‐precision numbers, resulting in a double‐precision number One, two, or four single‐precision multiplies, or a complex single‐precision multiply in one cycle

As stated earlier, the instructions load, store, multiply and branch have different latencies and therefore complicate programming. All TMS320C66x instructions require only one cycle to execute (unit latency is one). However, some results are delayed (delay slots). When instructions are pipelined, the multiplier can issue one instruction per cycle.

Care should be taken when using the .M units to perform operations other than multiplications. Each .M unit has two 64‐bit write ports to the register file, and therefore the results of a 4‐cycle instruction and a 2‐cycle instruction operating on the same .M unit can write their results on the same instruction cycle. This is not an issue as long as the programmer is aware of this; see the example in Figure 2.7.

2.3.1 Control registers

The TMS320C66x devices have a number of registers for control purposes; see Table 2.8. Reading and writing to the control registers can be performed only via the .S2 unit. All control registers can be accessed by only the MVC (move constant) instruction.

Note: Only the .S2 unit and the MVC instruction can be used to access the control registers. However, some bit fields in some control registers can be modified by some instructions or events. For instance, when an interrupt occurs, a bit field in the Interrupt Flag Register (IFR) register will be modified.

2.4.1 Using the internal memory

When writing an application for a multicore processor, one tends to write code for one core and then run it in all cores. This simple task can be complicated to write as the local memories will have to have different addresses. For instance, the L2 SRAMs for the TMS320C6678 shown in Table 2.9 have different addresses. However, in a practical situation, each core sees its addresses differently. In the example shown in Figure 2.11, all cores use the same starting address 0 × 0080 0000 to access their local memories. For example, Core 0 can access the local memory of Core 1 by using the address 0 × 1180 0000, and Core 7 accessing the local memory L2 of Core 5 by using the address 0 × 1580 0000 and so on. In this way, a single code can be used by all cores without modifications.

2.4.2 Memory protection and extension

It has been shown that each core can use its own local memory (LL1, LL2, LS2 or LS3), and it has also been shown that cores can use the same code and the same addresses for accessing local variables. However, when data and/or code cannot fit in the internal memory, code and/or data will have to be located in the DDR memory. In this case, data and/or code located in the DDR will need to be accessed with different addresses unless they are shared. The Memory Protection and Address Extension (MPAX) unit can be used to make portions of the DDR look like local memories. For instance, if we consider the situation where Core 1 and Core 2 have the same code but different data (data 1 for Core 1 and data 2 for Core 2) and both code and data do not fit in the internal memory, one can use the MPAX registers to configure part of the DDR as a private memory to each core and part as shared memory, as shown in Figure 2.12. This has the advantage of increasing the performance, as no software is required to do the address translation and the same code is used by all cores. However, by doing so, the cache coherency must be maintained ‘manually’ by using the cache invalidate, cache writeback and cache writeback‐invalidate, since there is no coherency between the external memory and the internal memory. In addition to address extension, the MPAX can also be used for internal and external memory protection. More details covering the MPAX can be found in Refs. [6] and [7].

2.4.3 Memory throughput

Knowing where to locate the program and data is very critical for performance. In this section, the maximum data throughput is highlighted.

Consider Figure 2.13, and be aware that the DSP cores for the TMS320C6678 can be clocked at 1.0 GHz, 1.25 GHz or 1.4 GHz. Let’s assume that a core is clocked at 1.0 GHz and calculate the memory throughput.

• L1D SRAM. This operates at the same frequency as the DSP core and can access a maximum of 128‐bit data. Therefore, the throughput is 16 GB/s [(128) ^* (1.0)/8].
• L1P SRAM. This operates at the DSP clock frequency, and the CPU can fetch up to 256‐bit instructions. Therefore, the throughput is 32 GB/s [(256 ^* (1.0)/8)].
• L2 SRAM. This operates at half the frequency of the DSP core and can access a maximum of 256‐bit data. Therefore, the throughput will be half of the L1D SRAM, that is, 16 GB/s [(256 ^* (0.5)/8].
• MSMC SRAM. Operates at half the frequency of the DSP core but has four banks that can be accessed simultaneously. Therefore, the aggregate throughput will be four times that of the L2 SDRAM, which is 64 GB/s. Each KeyStone DSP core has a 256‐bit path at half the DSP clock frequency for a throughput of 16 GB/s. The KeyStone II doubles the clock speed and throughput.
• DDR3. The DDR3 has a 64‐bit interface to the MSMC and can be clocked at a maximum frequency of 1.333 GHz; therefore, the throughput is 10.666 GB/s (64 ^* 1.333)/8).

It is also important to explore and contrast the data throughput using the CPU (as shown here) and the EDMA; see Ref. [8].

For the KeyStone II device throughput, refer to Ref. [9].

2.5.1 Navigator

The Multicore Navigator, also referred to as the Navigator, provides a high‐speed packed data transfer to enhance CorePac to accelerator/peripheral data movements, core‐to‐core data movements, inter‐core communication and synchronisation without loading the CorePacs. The Navigator is covered in Chapter 14.

2.5.2 Enhanced Direct Memory Access (EDMA) Controller

The TMS320C66x on‐chip EDMA Controller allows data transfers between the internal memory and (1) external memory, (2) host port and (3) external peripherals. The EDMA data transfer is performed with zero overhead and is transparent to the CPU, which means that the EDMA and the CPU operations can be independent. Of course, if both the DMA and the CPU try to access the same memory location, arbitration will be performed by the program memory controller. The EDMA is covered in Chapter 8 and in the EDMA user guide [10].

2.5.3 Universal Asynchronous Receiver/Transmitter (UART)

The UART on the KeyStone I and II is full duplex. The UART has a programmable baud rate, and both transmit and receive sides have FIFOs (first in, first out) that can store 16 bytes to ease the pressure on the CPU. These FIFOs can be bypassed. The TMS320C6678 has one UART, and the TMS32066AK2H14/12/06 has two UARTs. An example showing how to use and program these UARTs can be found in Chapter 15. More information can be found in the UART user guide [11].

2.5.4 General purpose input–output (GPIO)

The KeyStone I and II both have several GPIO pins (the TMS320C6678 has 16 GPIO pins, and the TMS320C66AK2H14/12/06 has 32 pins) that can be configured to be inputs or outputs. To provide flexibility, each GPIO pin can be controlled independently. These pins can be programmed to generate interrupts to the CPU or the EDMAs on the rising or falling edge. Chapter 6 provides examples with GPIOs for generating interrupts. More information can be found in the ‘KeyStone Architecture General Purpose Input/Output (GPIO) User Guide’ [12].

2.5.5 Internal timers

The TMS320C6678 has 16 32‐bit timers, and the 66AK2H14/12 has 20 32‐bit programmable internal timers. Each core (DSP or ARM) has its own timer that can be configured as a general‐purpose timer or a watchdog timer, and the rest of the timers can only be configured as general‐purpose timers.

A timer is composed of one 64‐bit timer period register to host the count value specified by the user and one count‐up (timer counter) register that is incremented in every input clock. When the timer counter reaches the timer period register value, it either will trigger a timer interrupt to the CPU, trigger a timer event to the EDMA controller, set a bit in the TCR register or generate an output signal on the timer output pin.

The timers can be configured as single 64‐bit timers or dual 32‐bit timers that can operate as chained (chained mode), where one timer triggers the other which then generates the interrupt signals, or operate as unchained (unchained mode), where both timers can generate interrupts. The timers can also be configured to be used as 64‐bit watchdog timers in order to provide a control exit; see Table 2.10. More details can be found in Ref. [13]. See Chapter 7 for examples using the timers.