When working with the postmortem remains of a system, it helps to have a good understanding of the anatomy of the system in question. The more you know about the involved processor and its native instruction set, the easier your work will be.
In this section, we talk about the SPARC processor. For further information, we highly recommend the reference we used, The SPARC Architecture Manual, Version 8 from SPARC International.
Even if your system doesn’t have a SPARC processor inside it, you’ll learn something about your own processor while reading this chapter. How is that? Just as all automobile engines have similarities, so do all computer processors.
Some processors consist of dozens of large printed circuit boards, whereas other processors reside on a chip you can hold on the end of your fingertip. Yet, even the largest of processors and the tiniest have components in common, such as registers used for manipulating data and arithmetic units that perform math.
Let’s take a look at the SPARC processor now.
In very simple terms, the SPARC processor is logically divided into three major components, as illustrated below.
The Integer Unit is really the heart of the SPARC processor; the central processing unit, if you prefer. The IU controls the overall operation of the processor. It loads and controls the execution of program instructions, calculates memory addresses, and has an arithmetic and logic unit (ALU).
The IU also owns the registers we will be referencing most often during system crash dump analysis, as well as a few we may never use. All of the IU registers are 32 bits wide. Let’s discuss each of them.
According to the SPARC Version 8 specification, there may be anywhere from 40 to 520 general-purpose registers. These are also referred to as working data registers. These are the registers used to transfer data between memory and the processor or to hold results of operations performed in the IU.
SPARC general-purpose registers are viewed in groups or clusters known as windows. We’ll be discussing the concept of windows a little later in this appendix. Another discussion, in more detail, can be found in Chapter 17, “Stacks.”
The Program Counter contains the address of the instruction currently being executed by the integer unit.
As its name suggests, the nPC contains the address of the next instruction expected to be executed by the IU.
When a delayed control transfer instruction is executed, nPC will point to the target of the instruction. This might not mean much to you right now, but it will as soon as we start talking, in Appendix B, about the different instructions available on the SPARC processor.
The PSR contains useful information regarding, as the name implies, the status of the processor. Let’s look at the Processor Status Register bit by bit. We point out the nibble boundaries because you’ll be looking at this register in hexadecimal, and each hex digit represents one nibble (half a byte)
The impl and vers fields, implementation and version, are hardwired by the processor manufacture to identify the processor chip and its revision level.
The icc field, Integer Condition Codes, is used by the arithmetic logic unit to record conditions caused by the arithmetic and logic instructions whose names end in cc. There are four bits in the icc field, one for each of the following conditions:
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• Bit 23 |
Condition n, negative result occurred |
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• Bit 22 |
Condition z, result was zero |
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• Bit 21 |
Condition v, overflow occurred |
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• Bit 20 |
Condition c, bit 31 was carried or borrowed |
The EC and EF fields, Enable Coprocessor and Enable Floating-point unit, are set accordingly when these optional pieces of hardware are available for use. If a unit is not enabled and an instruction tries to access the unit, a trap will occur.
The PIL field of the Processor Status Register identifies the Processor Interrupt Level above which the processor will accept an interrupt. Interrupt level 15 is the highest possible interrupt on this architecture; thus, only 4 bits are needed for the PIL field.
The S field is set to 1 when the processor is running in Supervisor mode, 0 when running in user mode. In user mode, certain privileged instructions cannot be executed. The S bit can only be set by the hardware and is set whenever a trap occurs. Once the bit set, the operating system clears it when Supervisor mode is no longer needed. Essentially, this is done on return to a user program.
The PS field contains the value of the S bit at the time of the most recent trap — the previous S bit. Examining this flag will allow the kernel to identify when a trap was issued from a user program or from kernel code.
The ET field of the Processor Status Register is set to 1 when Traps are Enabled. When set to 0, traps are ignored.
The CWP field is the Current Window Pointer and identifies which register window is in use. This SPARC implementation allows up to 32 register windows, numbered 0 to 31, thus, only 5 bits are needed for the CWP.
The TBR contains three fields that, when concatenated, become a valid memory address pointing to where control is transferred when a trap occurs. The TBRis diagrammed below.
Here’s a rare example of when TBA does not mean “To Be Announced.” The TBA field contains the Trap Base Address. This will be the most significant 20 bits of the trap vector table address.
The 8-bit-wide tt, or trap type field, is written by the hardware when a trap occurs. It provides the offset into the trap vector table.
Bits 3:0 are zero. This means that the TBRwill always represent hexadecimal memory addresses that end in 0 (addresses that are on 4-word boundaries).
The 32-bit WIM register contains a bit for each possible window in the SPARC Version 8 implementation. The low-order bit represents window 0. The high-order bit represents window 31. One bit is normally set and marks the point at which a window overflow or underflow would occur. This could result in destruction of the register contents if not correctly handled, so a trap is issued if an instruction would result in making this window available for use.
The WIM register is used in conjunction with the CWP (Current Window Pointer) during window shifts. We will be discussing this use in more detail later on.
32-bit by 32-bit multiplication can result in up to 64-bit results. The most significant 32 bits are stored in the Y register. The Yregister is also used during division and holds the most significant word of the dividend.
The Version 7 architecture, which had no full multiply or divide, used this register as temporary storage for individual “steps” in a multiplication or division sequence.
The SPARC Version 8 Specification allows for up to 31 additional registers. Ancillary registers 1 through 15 are reserved for future use. ASRs 16 through 31 can be used as desired by each implementation.
The Solaris operating systems assume that no ASRs are available for use.
According to the SPARC Version 8 Specification, an implementation may contain zero or more deferred-trap queues on the processor. These queues would be used to implement resumable deferred-traps caused by the Integer Unit.
The Solaris operating systems assume that no DTQs are available for use.
The Floating-Point Unit is an optional part of the SPARC processor. As its name suggests, the FPU handles all floating-point operations and arithmetic. Like the Integer Unit, the FPU has a set of working data registers, a control and status register, and an optional deferred-trap queue.
Floating-point instructions and data formats, as defined by the SPARC Version 8 Specification, conform to the ANSI/IEEE Standard 754-1985. However, the SPARC specification doesn’t require that all aspects of the ANSI/IEEE standard be implemented in the SPARC hardware. In cases where the hardware implementation does not meet the ANSI/IEEE standard, an exception trap may be generated and the operating system software performs the necessary work instead.
Since the Floating-Point Unit is optional, the operating system must be able to completely and properly provide the user with precisely the exact results that the FPU would have provided, as according to the ANSI/IEEE standard. The user needn’t worry about whether an FPU exists on his system. When an FPU is available, the Integer Unit will just pass all the floating-point instructions over to it for execution. This means the FPU will be operating in parallel with the IU.
If the FPU doesn’t exist in a SPARC processor, or if the enable floating-point EF bit in the PSR is set to 0 and a floating-point instruction is executed, an fp_disabled trap will occur. Again, in this case, the operating system intervenes and performs the floating-point operation via software instead of via hardware.
As you can probably imagine, performing all floating-point operations on an FPU instead of via software can make a huge performance difference. FPU performance is often measured in units of megaflops, or millions of floating-point operations per second.
The FPU has thirty-two 32-bit floating-point working data registers, known as f registers. The f registers can be used to represent 32 single-precision, 16 double-precision, or 8 quad-precision floating-point values at a given time, or combinations of these. Unlike the windowed IU general purpose registers, all 32 f registers can be accessed by a routine at any time.
Like the IU, the FPU has a status and control register. We won’t be using this register very often during system crash dump analysis, so we will only introduce you to it. For complete technical information about the FSR and the contents of some of its fields, refer to both the SPARC Version 8 Specification and the ANSI/IEEE Standard 754-1985, preferably on nights when you can’t sleep. The register fields and their bit assignments are diagrammed below.
The RD field selects the “rounding direction” for floating-point results.
Bits 29, 28, and 12 are currently undefined in the SPARC Version 8 Specification.
The TEM field contains the Trap Enable Mask. Each bit represents a different exception type that may be generated by floating-point operations. If the bit is set, the exception will generate a trap. We will list the possible exceptions shortly.
The NS bit, when set, allows the FPU to produce nonstandard results, that is, results that may not meet the ANSI/IEEE Standard 765-1985.
Bits 21 and 20 are reserved for future use.
The ver field contains the FPU implementation version number.
The ftt field is used to identify floating-point exception trap types.
The qne bit is set if there is an optional floating-point deferred-trap queue (FQ) and it is not empty.
The fcc field is the FPU’s equivalent to the IU’s icc field in the PSR. The two bits are used to represent different floating-point relationships, which are recorded when working with two floating-point values. They are as follows:
Table A-1. FPU fcc bits
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fcc bits |
Relationship Between Two Floating-point Values | |
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Values were equal |
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f1 less than f2 |
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f1 greater than f2 |
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f1 and f2 are unordered |
The aexc and cexc fields are used to record the accumulated exceptions and the current exceptions generated by floating-point operations. The five bits of each of these fields correspond to the five bits of the TEM field. Starting with the high-order bit, they are:
NV —. Invalid operation
OF —. Overflow
UF —. Underflow
DZ —. Divide by zero
NX —. Rounded result differs from exact correct result
Like the Integer Unit, the Floating-Point Unit can optionally be implemented to include a floating-point deferred-trap queue. If a deferred-trap queue does not exist on the FPU, the FSR qne bit will be set to 0. The contents and operations of the FQ are completely implementation dependent.
The SPARC Version 8 Specification allows for a second processing unit, which is referred to as a coprocessor. Its design and use are implementation dependent.
The Solaris operating systems assume that no coprocessor unit is present.
Now that you have an idea of the SPARC processor hardware, let’s return to the Integer Unit to talk more about register windows. The concept of windowing is quite important when we discuss stacks, frame, and stack trace backs.
As you know, SPARC processors that comply with the SPARC Version 8 architecture specification can have anywhere between 40 to 520 general-purpose, 32-bit registers. At any one time, however, a routine can only access 32 of these registers, 24 of which are clustered into what is referred to as a “window.” The other 8 registers, always the same 8 and referred to as “global registers,” are visible at all times.
With up to 520 general-purpose registers available on a SPARC processor, a window provides the executing routine a limited “view” of the hardware’s full set of registers, to put it simply.
Note
From this point on, when we use the word “register,” we will be referring to a general-purpose register. When we need to refer to another register, such as a floating-point register, we will refer to it with a specific name.
When a save instruction is executed, the window, or limited view of the full set of registers, shifts to a new, adjacent window. Traps cause the same action. When a restore instruction is executed, the view of the registers shifts back to the former window. The interesting detail about these window shifts is that the new view overlaps the old view by eight registers. We’ll get back to this in a moment.
The 24 general-purpose registers within a register window view may be addressed in SPARC assembly language as registers %r8 through r31. However, they are more commonly referred to by other names, as shown below.
Table A-2. SPARC general purpose registers
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Window Register Address |
r Register Address |
Description of Registers |
|---|---|---|
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Global registers. Always available to all routines. |
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Output registers. New window’s input registers. |
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Local registers. Unique to each procedure. |
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Input registers. Old window’s output registers. |
As hinted at in the chart above, the input and output registers, or i and o registers, are the ones that overlap from window to window. The local, or lregisters, are unique to each window. Together, the i, o, and lregisters make up the 24-register window view.
Registers r0 through r7 are actually outside the register window. However, since they are available to all procedures, in addition to the 24 i, o, and l window registers, they are assigned window register address names. These 8 global registers are referred to as g0through g7.
The SPARC processor, as described in The SPARC Architecture Manual, Version 8, is the recommended description and standard by which SPARC Version 8 processor chips should be manufactured. To learn the exact details and additional enhancements of your specific SPARC processor, read the hardware specification for that chip.
Now that you’ve gotten an idea of what the SPARC processor looks like, you are better armed to learn about the SPARC instruction set, which follows.