Home Page Icon
Home Page
Table of Contents for
Section IV SDD Metrics
Close
Section IV SDD Metrics
by Krishnendu Chakrabarty, Sandeep K. Goel
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits
Cover Page
Title Page
Copy Page
Preface
About the Editors
Contributors
1 Fundamentals of Small-Delay Defect Testing
1.1 Introduction
1.2 Trends and Challenges in Semiconductor Manufacturing
1.2.1 Process Complexity
1.2.2 Process Variability
1.2.3 Random versus Systematic Defects
1.2.4 Implications of Power and Timing Optimization
1.2.5 The Interaction of Yield, Quality, and Fault Coverage
1.3 Existing Test Methods and Challenges of Smaller Geometries
1.3.1 Line Stuck-at Fault Model
1.3.2 Bridging Fault Models
1.3.3 n-Detection
1.3.4 Transition Fault Model
1.3.5 Path Delay Fault Model
1.3.6 Test Implementation and Adaptive Test
1.4 Effect of Small Delays on Transition Testing
Section I Timing-Aware ATPG
2 K Longest Paths
2.1 Introduction
2.2 Path Generation for Combinational Circuits
2.2.1 Refined Implicit False Path Elimination
2.3 Experimental Results for Combinational Circuits
2.4 Extension to Scan-Based At-Speed Testing of Sequential Circuits
2.5 Path Generation for Scan Circuits
2.5.1 Implications on Scanned Flip-Flops
2.5.2 Constraints from Nonscanned Memories
2.5.3 Final Justification
2.6 Experimental Results on Scan Circuits
2.6.1 Robust Test
2.6.2 Comparison to Transition Fault Tests
2.7 Conclusions
3 Timing-Aware ATPG
3.1 Introduction
3.2 Delay Calculation and Quality Metrics
3.2.1 Delay Calculation
3.2.2 Delay Test Quality Metrics
3.2.2.1 Delay Test Coverage
3.2.2.2 Delay Test Quality Coverage
3.2.2.3 Statistical Delay Quality Level
3.3 Deterministic Test Generation
3.3.1 Test Generation with Timing Data
3.3.2 Fault Simulation with Timing Data
3.4 Trade-off between Test Quality and Test Cost
3.4.1 Dropping Based on Slack Margin
3.4.2 Timing-Critical Faults
3.5 Experimental Results
Section II Faster-than-at-Speed
4 Faster-than-at-Speed Test for Screening Small-Delay Defects
4.1 Introduction
4.2 Design Implementation
4.3 Test Pattern Delay Analysis
4.3.1 Dynamic IR Drop Analysis at Functional Speed
4.3.2 Dynamic IR Drop Analysis for the Faster-than-at-Speed Test
4.4 IR Drop Aware Faster-than-at-Speed Test Technique
4.4.1 Pattern Grouping
4.4.2 Estimation of Performance Degradation
4.5 Experimental Results
4.6 Conclusions
5 Circuit Path Grading Considering Layout, Process Variations, and Cross Talk
5.1 Introduction
5.1.1 Commercial Methodologies for SDD Detection
5.1.2 Academic Proposals for SDD Detection
5.2 Analyzing SDDs Induced by Variations
5.2.1 Impact of Process Variations on Path Delay
5.2.2 Impact of Cross Talk on Path Delay
5.3 TDF Pattern Evaluation and Selection
5.3.1 Path PDF Analysis
5.3.2 Pattern Selection
5.4 Experimental Results and Analysis
5.4.1 Pattern Selection Efficiency Analysis
5.4.2 Pattern Set Analysis
5.4.3 Long-Path Threshold Analysis
5.4.4 CPU Run Time Analysis
5.5 Conclusion
Section III Alternative Methods
6 Output Deviations-Based SDD Testing
6.1 Introduction
6.2 The Need for Alternative Methods
6.3 Probabilistic Delay Fault Model and Output Deviations for SDDs
6.3.1 Method of Output Deviations
6.3.1.1 Gate Delay Defect Probabilities
6.3.1.2 Propagation of Signal Transition Probabilities
6.3.1.3 Implementation of Algorithm for Propagating Signal Transition Probabilities
6.3.1.4 Pattern-Selection Method
6.3.2 Practical Aspects and Adaptation to Industrial Circuits
6.3.3 Comparison to SSTA-Based Techniques
6.4 Simulation Results
6.4.1 Experimental Setup and Benchmarks
6.4.2 Simulation Results
6.4.3 Comparison of the Original Method to the Modified Method
6.5 Conclusions
7 Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects
7.1 Introduction
7.2 Fault Set for Timing-Aware ATPG
7.3 Small-Delay Defect Pattern Generation
7.3.1 Approach 1: TDF plus Top-off SDD
7.3.2 Approach 2: Top-off SDD plus Top-off TDF
7.4 Experimental Results
7.5 Conclusion
8 Circuit Topology-Based Test Pattern Generation for Small-Delay Defects
8.1 Introduction
8.2 Circuit Topology-Based Fault Selection
8.3 SDD Pattern Generation
8.4 Experimental Results and Analysis
8.4.1 Delay Test Coverage
8.4.2 Number of Unique Long Paths
8.4.3 Length of Longest Path
8.4.4 Number of Unique SDDs
8.4.5 Random Fault Injection and Detection
8.5 Conclusion
Section IV SDD Metrics
9 Small-Delay Defect Coverage Metrics
9.1 Role of Coverage Metrics
9.2 Overview of Existing Metrics
9.2.1 Delay Test Coverage Metric
9.2.1.1 Shortcomings of the DTC Metric
9.2.2 Statistical Delay Quality Level Metric
9.2.2.1 Shortcomings of the SDQL Metric
9.3 Proposed SDD Test Coverage Metric
9.3.1 Quadratic SDD Test Coverage Metric
9.3.2 Faster-than-at-Speed Testing
9.4 Experimental Results
9.4.1 Sensitivity to System Frequency
9.4.2 Sensitivity to Defect Distribution
9.4.3 Timing-Aware versus Faster-than-at-Speed
9.5 Conclusion
10 Conclusion
Index
Search in book...
Toggle Font Controls
Playlists
Add To
Create new playlist
Name your new playlist
Playlist description (optional)
Cancel
Create playlist
Sign In
Email address
Password
Forgot Password?
Create account
Login
or
Continue with Facebook
Continue with Google
Sign Up
Full Name
Email address
Confirm Email Address
Password
Login
Create account
or
Continue with Facebook
Continue with Google
Prev
Previous Chapter
8 Circuit Topology-Based Test Pattern Generation for Small-Delay Defects
Next
Next Chapter
9 Small-Delay Defect Coverage Metrics
Section IV
SDD Metrics
Add Highlight
No Comment
..................Content has been hidden....................
You can't read the all page of ebook, please click
here
login for view all page.
Day Mode
Cloud Mode
Night Mode
Reset