Title Page
by Krishnendu Chakrabarty, Sandeep K. Goel
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits
- Cover Page
- Title Page
- Copy Page
- Preface
- About the Editors
- Contributors
- 1 Fundamentals of Small-Delay Defect Testing
- Section I Timing-Aware ATPG
- 2 K Longest Paths
- 3 Timing-Aware ATPG
- Section II Faster-than-at-Speed
- 4 Faster-than-at-Speed Test for Screening Small-Delay Defects
- 5 Circuit Path Grading Considering Layout, Process Variations, and Cross Talk
- Section III Alternative Methods
- 6 Output Deviations-Based SDD Testing
- 7 Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects
- 8 Circuit Topology-Based Test Pattern Generation for Small-Delay Defects
- Section IV SDD Metrics
- Index
Testing for
Small-Delay Defects
in Nanoscale CMOS
Integrated Circuits
Edited by
Sandeep K. Goel
Krishnendu Chakrabarty
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