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3. Appendices
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3. Appendices
by Samir Palnitkar
VerilogĀ® HDL: A Guide to Digital Design and Synthesis, Second Edition
Copyright
Dedication
About the Author
List of Figures
List of Tables
List of Examples
Foreword
Preface
Who Should Use This Book
How This Book Is Organized
Conventions Used in This Book
Acknowledgments
1. Basic Verilog Topics
1. Overview of Digital Design with Verilog HDL
1.1. Evolution of Computer-Aided Digital Design
1.2. Emergence of HDLs
1.3. Typical Design Flow
1.4. Importance of HDLs
1.5. Popularity of Verilog HDL
1.6. Trends in HDLs
2. Hierarchical Modeling Concepts
2.1. Design Methodologies
2.2. 4-bit Ripple Carry Counter
2.3. Modules
2.4. Instances
2.5. Components of a Simulation
2.6. Example
2.6.1. Design Block
2.6.2. Stimulus Block
2.7. Summary
2.8. Exercises
3. Basic Concepts
3.1. Lexical Conventions
3.1.1. Whitespace
3.1.2. Comments
3.1.3. Operators
3.1.4. Number Specification
Sized numbers
Unsized numbers
X or Z values
Negative numbers
Underscore characters and question marks
3.1.5. Strings
3.1.6. Identifiers and Keywords
3.1.7. Escaped Identifiers
3.2. Data Types
3.2.1. Value Set
3.2.2. Nets
3.2.3. Registers
3.2.4. Vectors
Vector Part Select
Variable Vector Part Select
3.2.5. Integer , Real, and Time Register Data Types
Integer
Real
Time
3.2.6. Arrays
3.2.7. Memories
3.2.8. Parameters
3.2.9. Strings
3.3. System Tasks and Compiler Directives
3.3.1. System Tasks
Displaying information
Monitoring information
Stopping and finishing in a simulation
3.3.2. Compiler Directives
`define
`include
3.4. Summary
3.5. Exercises
4. Modules and Ports
4.1. Modules
4.2. Ports
4.2.1. List of Ports
4.2.2. Port Declaration
4.2.3. Port Connection Rules
Inputs
Outputs
Inouts
Width matching
Unconnected ports
Example of illegal port connection
4.2.4. Connecting Ports to External Signals
Connecting by ordered list
Connecting ports by name
4.3. Hierarchical Names
4.4. Summary
4.5. Exercises
5. Gate-Level Modeling
5.1. Gate Types
5.1.1. And/Or Gates
5.1.2. Buf/Not Gates
Bufif/notif
5.1.3. Array of Instances
5.1.4. Examples
Gate-level multiplexer
4-bit Ripple Carry Full Adder
5.2. Gate Delays
5.2.1. Rise, Fall, and Turn-off Delays
Rise delay
Fall delay
Turn-off delay
5.2.2. Min/Typ/Max Values
Min value
Typ val
Max value
5.2.3. Delay Example
5.3. Summary
5.4. Exercises
6. Dataflow Modeling
6.1. Continuous Assignments
6.1.1. Implicit Continuous Assignment
6.1.2. Implicit Net Declaration
6.2. Delays
6.2.1. Regular Assignment Delay
6.2.2. Implicit Continuous Assignment Delay
6.2.3. Net Declaration Delay
6.3. Expressions, Operators, and Operands
6.3.1. Expressions
6.3.2. Operands
6.3.3. Operators
6.4. Operator Types
6.4.1. Arithmetic Operators
Binary operators
Unary operators
6.4.2. Logical Operators
6.4.3. Relational Operators
6.4.4. Equality Operators
6.4.5. Bitwise Operators
6.4.6. Reduction Operators
6.4.7. Shift Operators
6.4.8. Concatenation Operator
6.4.9. Replication Operator
6.4.10. Conditional Operator
6.4.11. Operator Precedence
6.5. Examples
6.5.1. 4-to-1 Multiplexer
Method 1: logic equation
Method 2: conditional operator
6.5.2. 4-bit Full Adder
Method 1: dataflow operators
Method 2: full adder with carry lookahead
6.5.3. Ripple Counter
6.6. Summary
6.7. Exercises
7. Behavioral Modeling
7.1. Structured Procedures
7.1.1. initial Statement
Combined Variable Declaration and Initialization
Combined Port/Data Declaration and Initialization
Combined ANSI C Style Port Declaration and Initialization
7.1.2. always Statement
7.2. Procedural Assignments
7.2.1. Blocking Assignments
7.2.2. Nonblocking Assignments
Application of nonblocking assignments
7.3. Timing Controls
7.3.1. Delay-Based Timing Control
Regular delay control
Intra-assignment delay control
Zero delay control
7.3.2. Event-Based Timing Control
Regular event control
Named event control
Event OR Control
7.3.3. Level-Sensitive Timing Control
7.4. Conditional Statements
7.5. Multiway Branching
7.5.1. case Statement
7.5.2. casex, casez Keywords
7.6. Loops
7.6.1. While Loop
7.6.2. For Loop
7.6.3. Repeat Loop
7.6.4. Forever loop
7.7. Sequential and Parallel Blocks
7.7.1. Block Types
Sequential blocks
Parallel blocks
7.7.2. Special Features of Blocks
Nested blocks
Named blocks
Disabling named blocks
7.8. Generate Blocks
7.8.1. Generate Loop
7.8.2. Generate Conditional
7.8.3. Generate Case
7.9. Examples
7.9.1. 4-to-1 Multiplexer
7.9.2. 4-bit Counter
7.9.3. Traffic Signal Controller
Specification
Verilog description
Stimulus
7.10. Summary
7.11. Exercises
8. Tasks and Functions
8.1. Differences between Tasks and Functions
8.2. Tasks
8.2.1. Task Declaration and Invocation
8.2.2. Task Examples
Use of input and output arguments
Asymmetric Sequence Generator
8.2.3. Automatic (Re-entrant) Tasks
8.3. Functions
8.3.1. Function Declaration and Invocation
8.3.2. Function Examples
Parity calculation
Left/right shifter
8.3.3. Automatic (Recursive) Functions
8.3.4. Constant Functions
8.3.5. Signed Functions
8.4. Summary
8.5. Exercises
9. Useful Modeling Techniques
9.1. Procedural Continuous Assignments
9.1.1. assign and deassign
9.1.2. force and release
force and release on registers
force and release on nets
9.2. Overriding Parameters
9.2.1. defparam Statement
9.2.2. Module_Instance Parameter Values
9.3. Conditional Compilation and Execution
9.3.1. Conditional Compilation
9.3.2. Conditional Execution
9.4. Time Scales
9.5. Useful System Tasks
9.5.1. File Output
Opening a file
Writing to files
Closing files
9.5.2. Displaying Hierarchy
9.5.3. Strobing
9.5.4. Random Number Generation
9.5.5. Initializing Memory from File
9.5.6. Value Change Dump File
9.6. Summary
9.7. Exercises
2. Advanced VerilogTopics
10. Timing and Delays
10.1. Types of Delay Models
10.1.1. Distributed Delay
10.1.2. Lumped Delay
10.1.3. Pin-to-Pin Delays
10.2. Path Delay Modeling
10.2.1. Specify Blocks
10.2.2. Inside Specify Blocks
Parallel connection
Full connection
Edge-Sensitive Paths
specparam statements
Conditional path delays
Rise, fall, and turn-off delays
Min, max, and typical delays
Handling x transitions
10.3. Timing Checks
10.3.1. $setup and $hold Checks
$setup task
$hold task
10.3.2. $width Check
10.4. Delay Back-Annotation
10.5. Summary
10.6. Exercises
11. Switch-Level Modeling
11.1. Switch-Modeling Elements
11.1.1. MOS Switches
11.1.2. CMOS Switches
11.1.3. Bidirectional Switches
11.1.4. Power and Ground
11.1.5. Resistive Switches
11.1.6. Delay Specification on Switches
MOS and CMOS switches
Bidirectional pass switches
Specify blocks
11.2. Examples
11.2.1. CMOS Nor Gate
11.2.2. 2-to-1 Multiplexer
11.2.3. Simple CMOS Latch
11.3. Summary
11.4. Exercises
12. User-Defined Primitives
12.1. UDP basics
12.1.1. Parts of UDP Definition
12.1.2. UDP Rules
12.2. Combinational UDPs
12.2.1. Combinational UDP Definition
12.2.2. State Table Entries
12.2.3. Shorthand Notation for Don't Cares
12.2.4. Instantiating UDP Primitives
12.2.5. Example of a Combinational UDP
12.3. Sequential UDPs
12.3.1. Level-Sensitive Sequential UDPs
12.3.2. Edge-Sensitive Sequential UDPs
12.3.3. Example of a Sequential UDP
12.4. UDP Table Shorthand Symbols
12.5. Guidelines for UDP Design
12.6. Summary
12.7. Exercises
13. Programming Language Interface
13.1. Uses of PLI
13.2. Linking and Invocation of PLI Tasks
13.2.1. Linking PLI Tasks
13.2.2. Invoking PLI Tasks
13.2.3. General Flow of PLI Task Addition and Invocation
13.3. Internal Data Representation
13.4. PLI Library Routines
13.4.1. Access Routines
Mechanics of access routines
Types of access routines
Examples of access routines
13.4.2. Utility Routines
Mechanics of utility routines
Types of utility routines
Example of utility routines
13.5. Summary
13.6. Exercises
14. Logic Synthesis with Verilog HDL
14.1. What Is Logic Synthesis?
14.2. Impact of Logic Synthesis
14.3. Verilog HDL Synthesis
14.3.1. Verilog Constructs
14.3.2. Verilog Operators
14.3.3. Interpretation of a Few Verilog Constructs
The assign statement
The if-else statement
The case statement
for loops
The function statement
14.4. Synthesis Design Flow
14.4.1. RTL to Gates
RTL description
Translation
Unoptimized intermediate representation
Logic optimization
Technology mapping and optimization
Technology library
Design constraints
Optimized gate-level description
14.4.2. An Example of RTL-to-Gates
Design specification
RTL description
Technology library
Design constraints
Logic synthesis
Final, Optimized, Gate-Level Description
IC Fabrication
14.5. Verification of Gate-Level Netlist
14.5.1. Functional Verification
Timing verification
14.6. Modeling Tips for Logic Synthesis
14.6.1. Verilog Coding Style
Use meaningful names for signals and variables
Avoid mixing positive and negative edge-triggered flipflops
Use basic building blocks vs. use continuous assign statements
Instantiate multiplexers vs. Use if-else or case statements
Use parentheses to optimize logic structure
Use arithmetic operators *, /, and % vs. Design building blocks
Be careful with multiple assignments to the same variable
Define if-else or case statements explicitly
14.6.2. Design Partitioning
Horizontal partitioning
Vertical Partitioning
Parallelizing design structure
14.6.3. Design Constraint Specification
14.7. Example of Sequential Circuit Synthesis
14.7.1. Design Specification
14.7.2. Circuit Requirements
14.7.3. Finite State Machine (FSM)
14.7.4. Verilog Description
14.7.5. Technology Library
14.7.6. Design Constraints
14.7.7. Logic Synthesis
14.7.8. Optimized Gate-Level Netlist
14.7.9. Verification
14.8. Summary
14.9. Exercises
15. Advanced Verification Techniques
15.1. Traditional Verification Flow
15.1.1. Architectural Modeling
15.1.2. Functional Verification Environment
15.1.3. Simulation
Software Simulation
Hardware Acceleration
Hardware Emulation
15.1.4. Analysis
15.1.5. Coverage
Structural Coverage
Functional Coverage
15.2. Assertion Checking
15.3. Formal Verification
15.3.1. Semi-formal Verification
15.3.2. Equivalence Checking
15.4. Summary
3. Appendices
A. Strength Modeling and Advanced Net Definitions
A.1. Strength Levels
A.2. Signal Contention
A.2.1. Multiple Signals with Same Value and Different Strength
A.2.2. Multiple Signals with Opposite Value and Same Strength
A.3. Advanced Net Types
A.3.1. tri
A.3.2. trireg
A.3.3. tri0 and tri1
A.3.4. supply0 and supply1
A.3.5. wor, wand, trior, and triand
B. List of PLI Routines
B.1. Conventions
B.2. Access Routines
B.2.1. Handle Routines
B.2.2. Next Routines
B.2.3. Value Change Link (VCL) Routines
B.2.4. Fetch Routines
B.2.5. Utility Access Routines
B.2.6. Modify Routines
B.3. Utility (tf_) Routines
B.3.1. Get Calling Task/Function Information
B.3.2. Get Argument List Information
B.3.3. Get Parameter Values
B.3.4. Put Parameter Value
B.3.5. Monitor Parameter Value Changes
B.3.6. Synchronize Tasks
B.3.7. Long Arithmetic
B.3.8. Display Messages
B.3.9. Miscellaneous Utility Routines
B.3.10. Housekeeping Tasks
C. List of Keywords, System Tasks, and Compiler Directives
C.1. Keywords
C.2. System Tasks and Functions
C.3. Compiler Directives
D. Formal Syntax Definition
D.1. Source Text
D.1.1. Library Source Text
D.1.2. Configuration Source Text
D.1.3. Module and Primitive Source Text
D.1.4. Module Parameters and Ports
D.1.5. Module Items
D.2. Declarations
D.2.1. Declaration Types
Module parameter declarations
Port declarations
Type declarations
D.2.2. Declaration Data Types
Net and variable types
Strengths
Delays
D.2.3. Declaration Lists
D.2.4. Declaration Assignments
D.2.5. Declaration Ranges
D.2.6. Function Declarations
D.2.7. Task Declarations
D.2.8. Block Item Declarations
D.3. Primitive Instances
D.3.1. Primitive Instantiation and Instances
D.3.2. Primitive Strengths
D.3.3. Primitive Terminals
D.3.4. Primitive Gate and Switch Types
D.4. Module and Generated Instantiation
D.4.1. Module Instantiation
D.4.2. Generated Instantiation
D.5. UDP Declaration and Instantiation
D.5.1. UDP Declaration
D.5.2. UDP Ports
D.5.3. UDP Body
D.5.4. UDP Instantiation
D.6. Behavioral Statements
D.6.1. Continuous Assignment Statements
D.6.2. Procedural Blocks and Assignments
D.6.3. Parallel and Sequential Blocks
D.6.4. Statements
D.6.5. Timing Control Statements
D.6.6. Conditional Statements
D.6.7. Case Statements
D.6.8. Looping Statements
D.6.9. Task Enable Statements
D.7. Specify Section
D.7.1. Specify Block Declaration
D.7.2. Specify Path Declarations
D.7.3. Specify Block Terminals
D.7.4. Specify Path Delays
D.7.5. System Timing Checks
System timing check commands
System timing check command arguments
System timing check event definitions
D.8. Expressions
D.8.1. Concatenations
D.8.2. Function calls
D.8.3. Expressions
D.8.4. Primaries
D.8.5. Expression Left-Side Values
D.8.6. Operators
D.8.7. Numbers
D.8.8. Strings
D.9. General
D.9.1. Attributes
D.9.2. Comments
D.9.3. Identifiers
D.9.4. Identifier Branches
D.9.5. Whitespace
Endnotes
E. Verilog Tidbits
Origins of Verilog HDL
Interpreted, Compiled, Native Compiled Simulators
Event-Driven Simulation, Oblivious Simulation
Cycle-Based Simulation
Fault Simulation
General Verilog Web sites
Architectural Modeling Tools
High-Level Verification Languages
Simulation Tools
Hardware Acceleration Tools
In-Circuit Emulation Tools
Coverage Tools
Assertion Checking Tools
Equivalence Checking Tools
Formal Verification Tools
F. Verilog Examples
F.1. Synthesizable FIFO Model
Input ports
Output ports
F.2. Behavioral DRAM Model
Input ports
Inout ports
Bibliography
Manuals
Books
Quick Reference Guides
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Using the CD-ROM
Technical Support
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