Table 3-1 Value Levels
Table 3-2 Strength Levels
Table 3-3 Special Characters
Table 3-4 String Format Specifications
Table 5-1 Truth Tables for And/Or Gates
Table 5-2 Truth Tables for Buf/Not Gates
Table 5-3 Truth Tables for Bufif/Notif Gates
Table 6-1 Operator Types and Symbols
Table 6-2 Equality Operators
Table 6-3 Truth Tables for Bitwise Operators
Table 6-4 Operator Precedence
Table 8-1 Tasks and Functions
Table 11-1 Logic Tables for NMOS and PMOS
Table 11-2 Strength Reduction by Resistive Switches
Table 11-3 Delay Specification on MOS and CMOS Switches
Table 11-4 Delay Specification for Bidirectional Switches
Table 12-1 UDP Table Shorthand Symbols
Table 13-1 Specifications for $my_stop_finish
Table 14-1 Verilog HDL Constructs for Logic Synthesis
Table 14-2 Verilog HDL Operators for Logic Synthesis
Table A-1 Strength Levels
Table B-1 Handle Routines
Table B-2 Next Routines
Table B-3 Value Change Link Routines
Table B-4 Fetch Routines
Table B-5 Utility Access Routines
Table B-6 Modify Routines
Table B-7 Get Calling Task/Function Information
Table B-8 Get Argument List Information
Table B-9 Get Parameter Values
Table B-10 Put Parameter Values
Table B-11 Monitor Parameter Value Changes
Table B-12 Synchronize Tasks
Table B-13 Long Arithmetic
Table B-14 Display Messages
Table B-15 Miscellaneous Utility Routines
Table B-16 Housekeeping Tasks
3.147.61.142