List Of Tables

Table 2.1. The three types of Verilog Code

Table 3.1. Table Indicating Value on Net C (net type tri) For Different Net Values on Driver A and B

Table 3.2. Table Indicating Value on Net C (net type trior) for Different Net Values on Driver A and B

Table 3.3. Table Indicating Value on Net C (net type triand) for Different Net Values on Driver A and B

Table 3.4. Table Indicating Value on Net C (net type trireg) for Different Net Values on Driver A and B

Table 3.5. Table Indicating Value on Net C (net type tri1) for Different Net Values on Driver A and B

Table 3.6. Table Indicating Value on Net C (net type tri0) for Different Net Values on Driver A and B

Table 3.7. Table Indicating Value on Net C (net type wand) for Different Net Values on Driver A and B

Table 3.8. Table Indicating Value on Net C (net type wor) for Different Net Values on Driver A and B

Table 3.9. Table Showing Different Strength Levels

Table 3.10. Truth Table for pmos Transistor Primitive

Table 3.11. Truth Table for nmos Transistor Primitive

Table 3.12. Truth Table for cmos Passgate Primitive

Table 3.13. Truth Table for notif0 Tri-state Inverter Primitive

Table 3.14. Truth Table for notif1 Tri-state Inverter Primitive

Table 3.15. Truth Table for bufif0 Tri-state Buffer Primitive

Table 3.16. Truth Table for bufif1 Tri-state Buffer Primitive

Table 3.17. Table Showing Functionality of UDP Module UDP_GATE

Table 3.18. Table Showing Functionality of UDP Module UDP_LATCH

Table 3.19. Table Showing Functionality of UDP Module UDP_POS_FLOP

Table 3.20. Concurrent and Sequential Statements

Table 4.1. Differences in Simulation Resulting From an Incomplete Sensitivity List

Table 4.2. Truth Table Showing Functionality for Module “conditional”

Table 4.3. Interface Signal Description for Traffic Light Controller

Table 5.1. Signal Description for Programmable Timer Design

Table 6.1. Table Showing a Description of PLB's Interface Signals

Table 6.2. Table Showing a Description of Bits 4 to 1 of CWR Register

Table 6.3. Table Showing a Description of Bits 2 and 1 of CWR Register

Table 6.4. Table Showing the Combinations of Functionality of PortA, PortB, PortC Upper and PortC Lower in Mode 0 Operation

Table 6.5. Table Showing the Combinations of Functionality of PortA and PortB in Mode 1 Operation

Table 6.6. Table Showing the Combinations of Functionality of PortA and PortB in Mode 1 Operation