Index

_reset, 58–59

_set, 57–58

1 × 2 decoder, 264–265

1 × 2 decoder with active low outputs, 265–266

1 × 2 decoder with enable input, 266–268

1 × 2 decoder with enable input and active low outputs, 268–269

1 × 2 DMUX, 243–245

1 × 2 DMUX with enable input, 244, 246–247

1 × 4 DMUX, 245, 247–249

1 × 4 DMUX with enable input, 246, 249–251

1 × 8 DMUX, 251–254

1 × 8 DMUX with enable input, 252, 255–257

1-bit (Boolean) variable definitions, 16–19

1-to-n demultiplexers, 243–244

2 × 1 MUX, 225–227

2 × 1 MUX with enable input, 226, 228–229

2 × 4 decoder, 269–271

2 × 4 decoder with active low outputs, 270–273

2 × 4 decoder with enable input, 273–275

2 × 4 decoder with enable input and active low outputs, 273–277

3 × 8 decoder, 276–279

3 × 8 decoder with active low outputs, 280–282

3 × 8 decoder with enable input, 280, 283–285

3 × 8 decoder with enable input and active low outputs, 283, 286–288

4 × 1 MUX, 228–230

4 × 1 MUX with enable input, 228, 231–232

4 × 2 priority encoder, 296–298

4 × 2 priority encoder with enable input, 298–299

4PDT switch, 1

74HC/LS165 registers, 1, 12–13

variable definitions, 17

8 × 1 MUX, 232–234, 236

8 × 1 MUX with enable input, 233, 235, 237–238

8 × 3 priority encoder, 300–303

8 × 3 priority encoder with enable input, 303–306

8-bit down counter (CTD_8), 130–132

8-bit off-delay timer (TOF_8), 105–107

8-bit on-delay timer (TON_8), 98–100, 102–104

8-bit oscillator timer (TOS_8), 112–115

8-bit pulse timer (TP_8), 108–111

8-bit up counter (CTU_8), 126–129

8-bit up/down counter (CTUD_8), 133–136

A

ADD, 163–164

and, 44–45

and_not, 46–47

Arithmetical functions, 163

Arithmetical macros

decR, 169–170

examples for, 170–174

incR, 168–169

R1addR2, 164–165

R1subR2, 165–167

RaddK, 165–166

RsubK, 167–168

B

BANK 0, 11–13

allocation of edge detection variables in, 68

allocation of variables for counter macros in, 123–124

allocation of variables for timers in, 97–99

BANK macros, 13–15

bI0 register, 14

bI1 register, 15

Buttons, 22–23

C

clock input (C), 77–78

clock out pin, 4, 9

clock_in, 1, 9

clock_out, 22

Comparison macros

examples for, 158–162

R_EQ_K, 153–154

R_GE_K, 151–153

R_GT_K, 151–152

R_LE_K, 155–156

R_LT_K, 154–155

R_NE_K, 157–158

R1_EQ_R2, 146–147

R1_GE_R2, 144–146

R1_GT_R2, 144–145

R1_LE_R2, 148–149

R1_LT_R2, 147–148

R1_NE_R2, 150–151

Contact and relay-based macros

_reset, 58–59

_set, 57–58

and, 44–45

and_not, 46–47

examples for, 59–65

in_out, 54–55

initialize, 31–32

inv_out, 56–57

ld, 38

ld_not, 39–40

nand, 47–48

nor, 42–44

not, 40

or, 41–42

or_not, 42–43

out, 51–53

out_not, 53–55

send_inputs, 33–34

xnor, 49, 51–52

xor, 47–49

xor_not, 49–50

Contact bouncing, 11

eliminating problem of in PIC16F648A-based PLC, 22–31

Contacts, 22–23

Counter macros

CTD_8, 130–132

CTU_8, 126–129

CTUD_8, 133–136

definition of status bits of, 125

examples for, 136–142

CPU board, 1, 6–8

photograph, 3

schematic diagram of, 2

CPU section, 1

CTD, 129–130

CTD_8, 130–132

CTU, 124–126

CTU_8, 126–129

CTUD_8, 133–136

D

D latch with active high enable (latch1), 72–73

D latch with active low enable (latch0), 72, 74

Data comparison, 143–144

data in pin, 1

data out pin, 9

Data transfer, 121–123

data_out, 22

dbncr0, 25–30

dbncr1, 30–31

DBNCRRED0, 28

Debouncer macros, 13–14, 25–31, 32

Debouncing, 23

DEC, 163

Decimal to BCD priority encoder, 303

Decimal to BCD priority encoder with enable input, 304, 307, 310–312

Decimal to binary coded decimal (BCD) priority encoder, 307–309

decod_1_2, 264–265

decod_1_2_AL, 265–266

decod_1_2_E, 266–268

decod_1_2_E_AL, 268–269

decod_2_4, 269–271

decod_2_4_AL, 270–273

decod_2_4_E, 273–275

decod_2_4_E_AL, 273–277

decod_3_8, 276–279

decod_3_8_AL, 280–282

decod_3_8_E, 280, 283–285

decod_3_8_E_AL, 283, 286–288

Decoder macros, examples for, 289–294

Decoders, 263–264

decR, 169–170

Decrement functions, 163

Demultiplexer macros

decod_1_2, 264–265

decod_1_2_AL, 265–266

decod_1_2_E, 266–268

decod_1_2_E_AL, 268–269

decod_2_4, 269–271

decod_2_4_AL, 270–273

decod_2_4_E, 273–275

decod_2_4_E_AL, 273–277

decod_3_8, 276–279

decod_3_8_AL, 280–282

decod_3_8_E, 280, 283–285

decod_3_8_E_AL, 283, 286–288

Dmux_1_2, 243–245

Dmux_1_2_E, 244, 246–247

Dmux_1_4, 245, 247–249

Dmux_1_4_E, 246, 249–251

examples for, 252, 255, 258–262

Demultiplexers (DMUX), 243–244

Destination registers, shift functions in, 199–200

dff_f, 77–79

DFF_FED, 67–68

dff_r, 74–77

DFF_RED, 67–68

Dmux_1_2, 243–245

Dmux_1_2_E, 244, 246–247

Dmux_1_4, 245, 247–249

Dmux_1_4_E, 246, 249–251

Dmux_1_8, 251–254

Dmux_1_8_E, 252, 255–257

Down counter (CTD), 129–130

E

Edge detection variables, 67–68

EEPROM data memory, 4

encod_4_2_p, 296–298

encod_4_2_p_E, 298–299

encod_8_3_p, 300–303

encod_8_3_p_E, 303–306

encod_dec_bcd_p, 303, 307–309

encod_dec_bcd_p_E, 304, 307, 310–312

Encoder macros. See Priority encoder macros

Encoders, 295–296

Example programs, 12

arithmetical macros, 170–174

comparison macros, 158–162

contact and relay-based macros, 59–65

counter macros, 136–142

decoder macros, 289–294

demultiplexer macros, 252, 255, 258–262

flip-flop macros, 88–96

multiplexer macros, 233, 235, 239–241

priority encoder macros, 312–317

shift and rotate macros, 210–224

EXNOR gate, 49

EXOR gate, 47–49

F

f_edge, 70–71

Falling edge detector (f_edge), 70–71

Falling edge triggered D flip-flop (dff_f), 77–79

Falling edge triggered JK flip-flop (jkff_f), 86, 88–91

Falling edge triggered T flip-flop (tff_f), 82–85

FED, 67–68

Flash program memory, 4

Flip-flop macros

dff_f, 77–79

dff_r, 74–77

examples for, 88–96

f_edge, 70–71

jkff_f, 86, 88–91

jkff_r, 82, 85–88

latch0, 72, 74

latch1, 72–73

r_edge, 68–70

tff_f, 82–85

tff_r, 80–82

Four-pole double-throw switch. See 4 PDT switch

FRSTSCN, 19, 34

G

get_inputs, 5, 11–12, 32–33

H

HC165, 21, 32–33

HC595, 21–22, 33–34

I

I/O contact debouncer, 24–25

I/O extension board, 1, 4–9

I0 register, 15

I1 register, 15

ICSP capability, 1

In Circuit Serial Programming capability. See ICSP capability

in_out, 54–55

INC, 163

incR, 168–169

Increment functions, 163

initialize, 11, 31–32, 97

initialization of counter macros within, 125

initialization of time macros within, 101

Input signals, 243

Inputs section, 6, 9

Internal relays, 18

inv_out, 56–57

inv_R, 189–190

J

jkff_f, 86, 88–91

JKFF_FED, 67–68

jkff_r, 82, 85–88

JKFF_RED, 67–68

L

latch out pin, 4

latch_out, 22

latch0, 72, 74

latch1, 72–73

ld, 38

ld_not, 39–40

Least significant bit (LSB), 199

Line decoders, 263–264

Load macros, 38–40, 121–123

load_R, 121–123

LOGIC variables, 19

Logical functions, 175

Logical macros

example for, 190–197

inv_R, 189–190

R1andR2, 176–177

R1nandR2, 177–179

R1norR2, 182–183

R1orR2, 180–181

R1xnorR2, 187–188

R1xorR2, 185–186

RandK, 177–178

RnandK, 179–180

RnorK, 183–184

RorK, 181–182

RxnorK, 187–189

RxorK, 186–187

M

m-to-n decoders, 263–264

m-to-n encoders, 295–296

M0 register, 17

M1 register, 17–18

M2 register, 18

M3 register, 19

Macros. See also specific macros

arithmetical, 163–170

BANK, 13–15

comparison, 143–158

contact and relay-based, 38–59

counter, 123–136

debouncer, 13–14, 25–31

decoder, 263–286

demultiplexer, 243–252

flip-flop, 67–88

get_inputs, 32–33

H165, 21

H595, 21–22

logical, 175–190

multiplexer, 225–233

priority encoder, 295–312

rotate, 201, 203, 205–209

shift, 199–204

swap, 209–210

timer, 97–115

Memory, 4. See also SRAM

Memory bits, 18

initial values of in Temp_2 register, 32

Model gate system, 319–322

control scenarios for, 321–323

solutions for the control scenarios for, 323–336

Most significant bit (MSB), 199

Move macros, 121–122

move_R, 121–122

Multiplexer macros

Dmux_1_8, 251–254

Dmux_1_8_E, 252, 255–257

examples for, 233, 235, 239–241

mux_2_1, 225–227

mux_2_1_E, 226, 228–229

mux_4_1, 228–230

mux_4_1_E, 228, 231–232

mux_8_1, 232–234, 236

mux_8_1_E, 233, 235, 237–238

Multiplexers(MUX), 225–226

mux_2_1, 225–227

mux_2_1_E, 226, 228–229

mux_4_1, 228–230

mux_4_1_E, 228, 231–232

mux_8_1, 232–234, 236

mux_8_1_E, 233, 235, 237–238

N

n-to-1 multiplexers, 225–226

nand, 47–48

nor, 42–44

Normally closed (NC) contact, 22–23

Normally open (NO) contact, 22–23

not, 40

Number of rotation, 199

Number of shift, 199

Numerical values, comparison of, 143

O

Off-delay timer (TOF), 102, 104

On-delay timer (TON), 97–98, 101

or, 41–42

or_not, 42–43

Oscillator timer (TOS), 111–112

out, 51–53

out_not, 53–55

Output lines, 243

Outputs section, 9

P

PIC16F648-based PLC

8-bit down counter for, 129–132

8-bit off-delay timers for, 102–107

8-bit on-delay timers for, 98–102

8-bit up counters for, 126–129

8-bit up/down counters for, 132–136

control scenarios for model gate system, 321–323

hardware, 1–9

oscillator timers for, 111–115

pulse timers for, 107–111

remotely controlled model gate system, 319–322

software structure, 11–22

solutions for the control scenarios for model gate system, 323–336

PLC

hardware, 1–10

scan cycle, 5, 9, 11–13, 19–20

PORTB, 31

Power section, 1

Priority encoder macros

encod_4_2_p, 296–298

encod_4_2_p_E, 298–299

encod_8_3_p, 300–303

encod_8_3_p_E, 303–306

encod_dec_bcd_p, 303, 307–309

encod_dec_bcd_p_E, 304, 307, 310–312

examples for, 312–317

Priority encoders, 295–296

Program examples, 12

arithmetical macros, 170–174

comparison macros, 158–162

contact and relay-based macros, 59–65

counter macros, 136–142

decoder macros, 289–294

demultiplexer macros, 252, 255, 258–262

flip-flop macros, 88–96

multiplexer macros, 233, 235, 239–241

priority encoder macros, 312–317

shift and rotate macros, 210–224

Programmable logic controllers. See PLC

Programming section, 1

Pulse timer (TP), 107–108

Q

Q0 register, 15, 17

Q1 register, 17

R

r_edge, 68–70

R_EQ_K, 153–154

R_GE_K, 151–153

R_GT_K, 151–152

R_LE_K, 155–156

R_LT_K, 154–155

R_NE_K, 157–158

R1_EQ_R2, 146–147

R1_GE_R2, 144–146

R1_GT_R2, 144–145

R1_LE_R2, 148–149

R1_LT_R2, 147–148

R1_NE_R2, 150–151

R1addR2, 164–165

R1andR2, 176–177

R1nandR2, 177–179

R1norR2, 182–183

R1orR2, 180–181

R1subR2, 165–167

R1xnorR2, 187–188

R1xorR2, 185–186

RaddK, 165–166

RAM data memory, 4

RandK, 177–178

RED, 67–68

Registers, comparison of, 143

Relay-based macros. See Contact and relay-based macros

Remotely controlled model gate system, 319–322

control scenarios for, 321–323

solutions for the control scenarios for, 323–336

Rising edge detector (r_edge), 68–70

Rising edge triggered D flip-flop (dff_r), 74–77

Rising edge triggered JK flip-flop (jkff_r), 82, 85–88

Rising edge triggered T flip-flop (tff_r), 80–82

RnandK, 179–180

RnorK, 183–184

RorK, 181–182

Rotate function, 199

Rotate macros. See Shift and rotate macros

rotate_L, 207–209

rotate_R, 201, 203, 205–206

RsubK, 167–168

RxnorK, 187–189

RxorK, 186–187

S

Scan oscillator, 19

SCNOSC, 19, 34

send_outputs, 9, 11, 13, 33–34

Shift and rotate macros

examples for, 210–224

rotate_L, 207–209

rotate_R, 201, 203, 205–206

shift_L, 200–201, 203–204

shift_R, 199–202

swap, 209–210

Shift functions, 199–200

shift in bit, 199

shift out bit, 199

shift/load, 1, 5

shift_L, 200–201, 203–204

shift_R, 199–202

Single I/O contact debouncer, 24–25

Source registers, shift functions in, 199–200

Special memory bits, initial values of in Temp_2 register, 32

SRAM, 11–13

allocation of variables for counter macros in, 123–124

allocation of variables for timers in, 97–99

BANK macros, 13–15

edge detection variables, 67–68

registers of, 31–32 (See also specific registers)

Static random-access memory. See SRAM

SUB, 163

swap, 209–210

Switches, 22–23

T

Temp_1, 28

Temp_2 register, 19

initial values of special memory bits in, 32

Temporary registers, 13

tff_f, 82–85

TFF_FED, 67–68

tff_r, 80–82

TFF_RED, 67–68

Timer macros

definition of status bits of, 100

example for, 115–119

TOF_8, 105–107

TON_8, 98–100, 102–104

TOS_8, 112–115

TP_8, 108–111

Timer registers, 20

Timing signals, 19–20

use of with debouncer macros, 27–29

TMR0, 12–13, 20, 31

TOF, 102, 104

TOF_8, 105–107

TON, 97–98, 101

TON_8, 98–100, 102–104

TOS, 111–112

TOS_8, 112–115

TP, 107–108

TP_8, 108–111

TPIC6B595 registers, 1, 4, 13

variable definitions, 17

U

Up counter (CTU), 124–126

Up/down counter (CTUD), 132–133

V

Variable definitions, 12–21

W

Watchdog timer, 11–12

X

xnor, 49, 51–52

xor, 47–49

xor_not, 49–50