Index
2’s Complement Numbers
Complement Computation
Scaling
2’s Complement Representation
2’s Complement Signed Multiplier
5:3 bit counter
5/3 lifting wavelet
4-entry FIFO queue
6:3 counter
(Advanced Microcontroller Bus Architecture) AMBA
A Hybrid FIR filter Structure
A multi channel DMA design
Acoustic Echo Canceller
Acoustic Noise Cancellation
Adaptive Algorithms
ADC bandwidth (BW)
adder graphs
Adders
Example
AES Algorithm
AES Architectures
Byte Systolic Fully Parallel
Time-Shared 8-bit Folding Architecture
Algorithm Transformations for CSA
Algorithmic State Machine (ASM)
Always Procedural Block
Amba High-speed Bus (AHB)
Analog Front End (AFE)
analog mixers
Application Specific Instruction-set Processor (ASIP)
Application Specific Processor (ASP)
Arithmetic Operators
Arithmetic Shift
ASICs
ASM
Example
ASM representation Blocks
assign
Balanced Equations
Example
Bandpass Sampling
Example
Barrel Shifter
dedicated multiplier
hierarchical design
pipelined design
Behavioral Level
Binary Carry Look-ahead Adder (BCLA)
Serial Implementation
Han-Carlson Parallel Prefix Adder
Kogge-Stone Parallel Prefix Adder
Ladner-Fischer Parallel Prefix Adder
RTL Verilog code
Bit-serial architecture
Example
Bitwise Arithmetic Operators
Black Box Testing
Block Diagram
Block Floating-Point Format
Block LMS
Block Turbo Code (BTC)
Blocking Procedural Assignment
Brent-Kung
Bubble Diagrams
Bus-based Design
Canonic Sign Digit (CSD)
carrier and sampling clock frequency offsets
Carry Chain Logic in FPGAs
Carry Look-ahead Adder
Carry Save Adder (CSA)
Carry Save Reduction
Carry Select Adder
Carry Skip Adder
CELP
Channel Coding
channel effects
Channel Equalizer using NLMS
CIC Filter
circuit clock
Circular Addressing
Clock Gating Technique
FSM Power Reduction
Cluster Look Ahead (CLA)
Code Coverage
Coding Guidelines
High Level Behavioral Description
State Machines
Coefficient Quantization
FIR Filter
Second Order Section
Common Object Request Broker Architecture (CORBA)
Common Sub expression Elimination (CSE)
Example
Common Sub expression with Multiple Operands
Communication Controller (CC)
Complexity Reduction
Compression Trees for Multi Operand Addition
Compression Trees
compressor 4
Concatenation Operator
Conditional Operator
Conditional Sum Adder
Constraint Based Testing
Control Data Flow Graph (CDFG)
Control Flow Graph (CFG)
Controller
CoORDinate DIgital Computer (CORDIC) algorithm
CORDIC algorithm
HW Mapping
Matlab Code
CORDIC Element (CE)
CORDIC HW design
Time Shared Architecture
implementation in Verilog
CORDIC Time shared architecture
Verilog code
Core Connect
corner case
Example Code
Correction Vector (CV)
Counter-based State Machine
Coverage Metrices
State Coverage
Toggle Coverage
Code Coverage
Path Coverage
Transition or Arc Coverage
Critical Path Delay
Critical Path
CSD
Example
C-Slow
Example
FPGA based design
time multiplexed logic
block processing
Instruction Set Processor
CORDIC
C-slow retiming
cut-set line
Cut-set Retiming
cut-set line
Delay transfer theorem
DF FIR Filter
Cyclo-Static DFG
Dadda Tree Reduction
Data Dependency Graph (DDG)
Data Flow Graph
Consistent and Inconsistent SDFG
Example IIR Filter as SDFG
Synchronous Data Flow Graph
Reconfigurable Computing
Dataflow Interchange Format (DIF) Language
Dataflow Level
Data path
DDFS
frequency and phase modulation systems
GMSK base band modulating
DDFS Architecture
Basic Architecture
DDFS in a digital communication receiver
Decomposed Multiplier
Delay Transfer Theorem
Pipeline 4-bit RCA
Design for Testability
Design of a Router for NOC
Design Strategies
DFG to HW Synthesis
Digit serial architecture
Example
Digital Base band Modulation
Digital Communication System
Digital Design Competing Objectives
Digital Filter Forms
Cascade Form
Direct Form-I (DF-I)
Direct Form-II (DF-II)
Second order Sections
Transposed Direct Form-II (TDF-II)
Digital Filters
Data Flow Graphs (DFGs)
Digital Front End (DFE)
Digital mixing
Digital Receiver
Digital Up-conversion and Mixing
Direct Digital Frequency Synthesizer (DDFS
Direct Form-I (DF-I)
Direct Form-II (DF-II)
Direct Memory Access (DMA)
Discrete Real-Time System
Distributed Arithmetic
Example
Example Verilog code
Doppler shift
Dot Notation
DSP
Fixed-point
floating-point
Dual Carry Save Reduction
Dynamic Dataflow Graph (DDFG)
Echo Canceller
Embedded Arithmetic Block
Design Optimization
Instantiation
Optimized Mapping
Element Interconnect Bus (EIB)
Encryption
Equality Operators
Exhaustive Test Vector Generation
Feedback cut-set retiming
Example
FT Architecture using FIR Filter Structure
FGPA
Configurable Logic Blocks (CLBs)
Finite Impulse Response (FIR)
Finite State Machine (FSM)
Example 4 ones detection
Example RTL Verilog Code
Mathematical Formulation
Testing
FIR Filter Design using Distributed Arithmetic
Fixed-point Arithmetic
Floating-point to Fixed-point Conversion
Qn.m Format
Overflow and Saturation
Support in SystemC
Support in Matlab
Fixed-Point HW
Fixed-Point Multiplication Rounding
Fixed-point Numbers
Bit Growth Issue
Rounding then Truncation
Floating Point Numbers
Addition
Multiplication
Normalized and De normalized Values
Floating-point Format
Floating-Point HW
Floating-Point to Fixed-Point Conversion
Floating-point to Fixed-point Conversion
Folded Architectures for FFT Computation
Folded FIR Filters
Folding Factor
Folding Scheduler
Folding Set
Folding Transformation
Example
Mathematical formulation
Folding
Example
Example L Coefficient FIR filter
Regular Structred DFG
Forward Error Correction (FEC)
FPGA
DSP48
DSP48e
Embedded Arithmetic Blocks
Embedded Processors
Framing
frequency error
Front End of a Receiver
FSM Decomposition Power Reduction
FSM Model for Exhaustive Testing
FSM Optimization Low power
FSM Testing
Adjacency Matrix for the ASM
Sequence Conformance
Full Adder
Fully Dedicated Architecture (FDA)
Selecting Basic Building Blocks
5 coefficient FIR filter in DF
Direct Form FIR Filter
Example of Direct Form (DF)-II
Example of first order IIR filter
Example Optimized DFG Transformation
Optimized DFG Transformation
Verilog code for DF FIR filter
Gate Level or Structural modeling
Gate Level Primitives
Generalized Cluster Look-Ahead (GCLA)
transformation
Generalized Parallel Counter (GPC)
Generating Test Cases
Global Correction Vector (GCV)
Computation for FIR filter
GMSK
Block diagram
GMSK Communication Transmitter
Goertzel algorithm
HW mapping
Golay complementary sequence
GPP
graphical Simulatable models
Hardware Description Language (HDL)
Hierarchical Design
HW/SW Partioning
HSDFG
Example
HW realization
Mapping a hypothetical DFG
Multi-rate DFG
Half Adder
Hard IP core
Hierarchical Carry Select Adder
hierarchical CLA logic
Hybrid Adder
Hybrid Ripple Carry and Carry Look-ahead Adder
Horizontal and Vertical Sub-expressions
Horizontal Sub-expression Elimination
Example
Horizontal Sub-expressions Elimination
Hierarchical FSM for Low Power Designs
Hybrid
Hybrid Connectivity
IIR Filter for Decimation
Example
IIR Filter for Decimation and Interpolation
IIR filter for Interpolation
Example
Illegal state detection
IMB Cell Processor
Implement DA-based Biquad IIR Filter
Initial Procedural Block
Instruction Dispatcher
Design Example
RTL Verilog code of the
integer
Integration Testing
Intellectual Property (IP)
Intermediate Frequency (IF)
Intermediate Overflow
FIR Filter
Inverse System Modeling
Iteration Period Bound (IPB)
Iteration Period
Example IIR system
Iteration
JPEG 2000
Kahn Process Network (KPN)
Example of hypothetical algorithm
Graphical illustration
JPEG Compression
Limitation
Matlab code of hypothetical application
Modeling Streaming Applications
MPEG Encoding
top-level code in Matlab
transmitter structure
KPN-based Top-level Design
Latency
Least Mean Square (LMS) Algorithm
LEC accelerator
Data path design
Instruction set design
Top level design
Levels of Abstraction
Switch Level
Levels of Testing
Line Echo Cancellation
Linear Prediction
Logic Shift Operator
Logical Operators
Look Ahead Transformation (LAT)
Example
Loop Bound
Example
Loop Unrolling
SW to HW Mapping
Loop
Low Noise Amplifier (LNA)
LPC coefficients
LUT-Less DA implementation
LZ77 architecture
Multiple iteration computation in parallel
LZ77 Data Compression Architecture
LZ77
Example
LZW
Mapping Multi-rate DFG in HW
Mealy machine
Mean Time Between Failure (MTBF)
Mean Time To Recover (MTTR)
mem
Memory Based Folded FFT Processor
Micro programmed Controller
Micro-coded Accelerator architecture
LEC
Micro-coded Mealy State Machine
Verilog Code
Micro-coded State Machine
Example of LIFO and FIFO
Micro-Coded State Machine based Design
Implementing Adaptive Algorithm
Micro-programmed state machine
Counter based with conditional branching
Design example for Motion Estimation
Design Example of a Wavelet Processor
Example
Loadable counter-based
Mealy machine
Micro-program counter based design
Moore machine
Nested Loop Support
Nested Subroutine Support
Subroutine Support
with parity field
Minimum Signed Digit (MSD) Representation
Model Checkers
Modified Booth Recoding Multiplier
RTL Verilog Implementation
Modified CORDIC Algorithm
HW Mapping
HW Optimization
Matlab implementation
Modified KPN and MPSoC
Moor’s Law
Moore machine
M-Parallel Sub-Filters Based Design
MPEG4
MSD
Example
Multi Core based Systems
Multi Processor System on Chip (MPSoC)
Multi-Dimensional Arrayed Data FlowGraph
Multiple Processors SoC (MPSoC)
Multiplication by Constant in Signal Processing Algorithm
multi-rate DFG
Example
Example 2-DCT
(N:n) counter
Network on Chip (NoC)
Top Level Design
Network-based Connectivity
Newton Repson method
NLMS algorithm for Equalization NLMS Algorithm
Matlab Implementation
NoC Flow Control
NoC for SDR
NoC Routing Algorithm
Deflection Rouging
Source Toggle XY
Weighted TXY (WTXY)
NoC Routing Protocols
NoC routing scheme
NoC Switching
Circuit switching
packet switching
NoC Topologies
Binary tree
Grid
Irregular connectivity
Mixed topology
Torus
NoC Virtual Channels
Non-blocking Procedural Assignments
Nondeterministic Polynomial-time (NP)
Non-Return-to-Zero (NRZ)
Novel CORDIC Architecture
Nyquist sampling criterion
Nyquist sampling theorem
Object Request Broker (ORB)
OFDM
channel estimation
channel impulse response
coarse timing estimation
IFFT
QPSK
OFDM cyclic prefix
OFDM modulation
Optimized Compressors
Parallel Mapping
Parallel Multipliers
Partial Product Generation
Partial Product Reduction
Peak-to Average Power Ratio
Peripheral Retiming
Pipeline Direct Form FIR filter
Pipelining FDA
Pipelining of Feed-Forward system
Pipelining
4-bit RCA
Compression tree
Conditional Sum Adder (Conditional Sum Adder)
Four pipeline stages in a 4-bit RCA
Using Delay Transfer Theorem
Verilog code for two stage pipelined 4-bit RCA
Point-to-point
Poly phase Decomposition
FIR filter
Decimation
Power dissipation
Formula
Power Reduction of a State Machine
Power
Printed Circuit Board (PCB)
Processor on a single SoC (MPSoC)
Q-Format
Addition
Multiplication
Quantization of IIR Filter Coefficients
quadrature mixer
Quadrature Mixing in Transmitter
Random Testing
Receiver
Doppler shifts
Multi path effects
OFDM
Reduction Operator
reg
Register Transfer Level (RTL)
Regression Testing
Relational Operator
Re pipelining
Replication Operators
Representation Methods of DSP systems
Requirements and Specifications (R&S)
Intermediate Overflow Property
Retiming
Application
Feedback system
Mathematical Formulation
Minimize the number of registers
Shannon Decomposition
Support in Synthesis Tools
Wire Delay Consideration
Ripple Carry Adder (RCA)
ROM-based Micro-programmed state machine
Router
Back Plane
Routing Algorithm
Toggle XY Routing
XY Routing
RTL Coding Guidelines
Avoid Combinational Feedback
Avoid Latches in the Design
Sample period
sampling clock
sampling-rate
Satellite Burst Modem
Scattered Cluster Look Ahead (SCA)
SDFG
Homogeneous SDF (HSDF)
implementing CD to DAT format
Multi-Rage (MR-SDFG)
Single Rate SDFG
Self-Timed Firing
Example
Sequencing and Control
Sequential Architecture
Sequential Mapping
Sequential multiplier
Example
Optimized implementation
Shannon Decomposition
Reducing IPB
Sign Extension Elimination
Signal Flow Graph
signed wire
Silicon Backplane µ Network
Single Rate SDFG
Soft IP cores
Software Communication Architecture (SCA)
Software Defined Radio (SDR)
Source Encoding
Specification based testing
Spurious Free Dynamic Range (SFDR)
Standard Delay (SDF) file
Standard Hamming encoder for BTC
State Encoding
Almost One-Hot
Binary
Example
Gray
One-Hot
Status and Control Register (SCR)
Store and Forward Switching
String Property
Sub-Graph Sharing
Subroutine Return Address (SRA) register
Synchronous Digital Hardware Systems
synchronous digital hardware
synchronous Hard-Real Time systems
Synthesis Guidelines
Avoid Glue Logic
Design modules with Common Design Objectives
Design Partitioning
System Design Flow
System Design Guidelines
System Generator from Xilinx
System Identification
System Level Testing
System on Chip (SoC)
Mixed-Signal SoC
System Verilog
always Procedural Block
Assertion
case statements
Classes
Coverage
Data Types
Direct Programming Interface (DPI)
final Procedural Block
Functions and Tasks
FSM Coding
Interface
Loops
Module Instantiation
Nested Modules
Operators
Package
Port Listing
Randomization
typedef struct and enum
Systolic 8-point FFT architecture
Systolic architecture
Systolic FFT architecture
RTL Verilog Code
Systolic Folded Architecture
typedef struct and enum
Test Cases to Localize a Fault
Testing
CORDIC HW
Testing a Digital Design
Throughput
Time Control
Time-shared architecture
Design Example
Time-shared Sequential FIR filters
Timing Diagram
Top level design
training sequence
Transaction Level Modeling
Transformations on DFG
Transposed Direct Form FIR (TDF)
Transposed Direct Form FIR Filter
CSD multiplication
one stage of pipelining
Unfolding
Effective Use of FPGA Resources
Maximize use of Compression Tree
Unfolding then Retiming in Feedback Designs
Unified Multiplier
unfolding factor
Unfolding Transformation
Example
User Constraint (UCF) file
Verification in HW Design
Verification Setup Example
Verilog
$display
$monitor
Case statement
Clock
Comments
Conditional statements
Constants
Data Types
End module
Feedback Register
Function
Loading memory data from a file
Logic Values
Loop Statements
Macros
Module
Nets
Parameter
Ports and Data Types
Preprocessing commands
Programming Language Interface (PLI)
Register
Reset
RTL
Signed Arithmetic
Simulation Control
Task
Variable Declaration
Vertical Sub-expressions Elimination
VHDL
Virtual-Cut-Through Switching
VoIP Media Gateway
Wallace Tree Reduction
wire
Wishbone
Wormhole Switching
Xilinx Core Generation