apply_transform : process is
begin
   d_out <= transform(d_in) after 200 ps;
   -- debug_test <= transform(d_in);
   wait on enable, d_in;
end process apply_transform;

16#1#      16#22#      16#100.0#       16#0.8#

12  132  44  250000  32768  0.625

O"747" = B"111_100_111"
O"377" = B"011_111_111"
O"1_345" = B"001_011_100_101"
X"F2" = B"1111_0010"
X"0014" = B"0000_0000_0001_0100"
X"0000_0001" = B"0000_0000_0000_0000_0000_0000_0000_0001"

10UO"747" = B"0_111_100_111"
10UO"377" = B"0_011_111_111"
10UO"1_345" = B"1_011_100_101"
10SO"747" = B"1_111_100_111"
10SO"377" = B"0_011_111_111"
10SO"1_345" = B"1_011_100_101
12UX"F2" = B"0000_1111_0010"
12SX"F2" = B"1111_1111_0010"
10UX"F2" is illegal due to truncation of leading 1 bits
10SX"F2" = B"11_1111_0010"

D"24" = B"11000"
12D"24" = B"0000_0001_1000"
4D"24" is illegal due to truncation of a leading 1 bit

constant bits_per_word : integer := 32;
constant pi : real := 3.14159;

variable counter : integer := 0;
variable busy_status : boolean;
variable temp_result : std_ulogic;

counter := counter + 1;
busy_status := true;
temp_result := 'W';

package misc_types is
   type small_int is range 0 to 255;
   type fraction is range -1.0 to +1.0;
   type current is range integer'low to integer'high
     units nA;
       uA = 1000 nA;
       mA = 1000 uA;
       A = 1000 mA;
     end units;
   type colors is (red, yellow, green);
end package misc_types;

pulse_range'left =  pulse_range'low = 1 ms
pulse_range'right = pulse_range'high = 100 ms
pulse_range'ascending = true
word_index'left = 31 word_index'right = 0
word_index'low = 0 word_index'high  = 31
word_index'ascending = false

state'pos(standby) = 1              state'val(2) = active1
state'succ(active2) is undefined    state'pred(active1) = standby
state'leftof(off) is undefined      state'rightof(off) = standby

2 * 3 + 6 / 4 = 7
3 + -4 is syntactically incorrect
"cat" & character'('0') = "cat0"
true and x and not y or z is syntactically incorrect
B"101110" sll 3 = B"110000"
(B"100010" sra 2) & X"2C"= B"11100000101100"

if n mod 2 = 1 then
  odd := '1';
else
  odd := '0';
end if;
odd := '1' when n mod 2 = 1 else
       '0';

if year mod 400 = 0 then
   days_in_February := 29;
elsif year mod 100 = 0 then
   days_in_February := 28;
elsif year mod 4 = 0 then
   days_in_February := 29;
else
   days_in_February := 28;
end if;
days_in_February := 29 when year mod 400 = 0 else
                    28 when year mod 100 = 0 else
                    29 when year mod 4 = 0 else
                    28;

case x is
   when '0' | 'L' => x := '0';
   when '1' | 'H' => x := '1';
   when others => x := 'X';
end case;
with x select
   x := '0' when '0'  | 'L',
         '1' when '1' | 'H',
         'X' when others;

case ch is
   when 'A' to 'Z' | 'a' to 'z' |
         'À' to 'Ö' | 'ø' to 'β' | 'à' to 'ö' | 'ø' to 'ÿ' =>
     character_class := 1;
   when '0' to '9' =>  character_class := 2;
   when nul to usp | del | c128 to c159 =>  character_class := 4;
   when others => character_class := 3;
end case;
with ch select
   character_class :=
     1 when 'A' to 'Z' | 'a' to 'z' |
         'À' to 'Ö' | 'ø' to 'β' | 'à' to 'ö' | 'ø' to 'ÿ',
     2 when '0' to '9',
     4 when nul to usp | del | c128 to c159,
     3 when others;

loop
   wait until clk;
   exit when d;
end loop;

sum := 1.0;
term := 1.0;
n := 0;
while abs term > abs (sum / 1.0E5) loop
   n := n + 1;
   term := term * x / real(n);
   sum := sum + term;
end loop;

sum := 1.0;
term := 1.0;
for n in 1 to 7 loop
   term := term * x / real(n);
   sum := sum + term;
end loop;

assert to_X01(q) = not to_X01(q_n)
   report "flipflop outputs are not complementary";

report "counter is reset";

type num_vector is array (1 to 30) of integer;
variable numbers : num_vector;
...
sum := 0;
for i in numbers'range loop
   sum := sum + numbers(i);
end loop;
average := sum / numbers'length;

type std_ulogic_to_bit_array is array (std_ulogic) of bit;
constant std_ulogic_to_bit : std_ulogic_to_bit_array
   := ( 'U' => '0', 'X' => '0', '0' => '0', '1' => '1', 'Z' => '0',
        'W' => '0', 'L' => '0', 'H' => '1', '-' => '0' );
...
for index in 0 to 15 loop
   v2(index) := std_ulogic_to_bit(v1(index));
end loop;

type free_map_array is array (0 to 1, 0 to 79, 0 to 17) of bit;
variable free_map : free_map_array;
...
found := false;
search_loop : for side in 0 to 1 loop
   for track in 0 to 79 loop
     for sector in 0 to 17 loop
       if free_map(side, track, sector) then
         found := true;  free_side := side;
         free_track := track;  free_sector := sector;
         exit search_loop;
       end if;
     end loop;
   end loop;
end loop;

subtype std_ulogic_byte is std_ulogic_vector(7 downto 0);
constant Z_byte : std_ulogic_byte := "ZZZZZZZZ";

type times_array is array (positive range <>) of time_vector;
subtype times4_array is times_array(1 to 4);
variable times4_10 : times4_array(open)(0 to 9);

count := 0;
for index in v'range loop
   if v(index) then
     count := count + 1;
   end if;
end loop;

variable v1 : bit_vector(7 downto 0);
variable v2 : bit_vector(31 downto 0);
...
v2(31 downto 24) := v1;
v2 := v2 sra 24;

type test_record is record
     stimulus : bit_vector(0 to 2);
     delay : delay_length;
     expected_response : bit_vector(0 to 7);
   end record test_record;

entity lookup_ROM is
   port ( address : in lookup_index;  data : out real );
   type lookup_table is array (lookup_index) of real;
   constant lookup_data : lookup_table
              := ( real'high, 1.0, 1.0/2.0, 1.0/3.0, 1.0/4.0, ... );
end entity lookup_ROM;

architecture functional of lookup_ROM is
begin
   data <= lookup_data(address) after 200 ps;
end architecture functional;

wait on s until not s and en;

wait until ready for 5 ms;

mux_logic : process is
begin
   if enable and sel then
     z <= a and not b after 5 ns;
   elsif enable and sel then
     z <= x or y after 6 ns;
   else
     z <= '0' after 4 ns;
   end if;
   wait on a, b, enable, sel, x, y;
end process mux_logic;

process is
begin
   case bit_vector'(s, r) is
     when "00" =>  q <= unaffected;
     when "01" =>  q <= '0';
     when "10" | "11" =>  q <= '1';
   end case;
   wait on s, r;
end process;

assert (not clk'event) or clk'delayed'last_event >= T_pw_clk
     report "interval between changes on clk is too small";

bit_0 : entity work.ttl_74x74(basic)
     port map ( pr_n => '1', d => q0_n, clk => clk, clr_n => reset,
                q => q0, q_n => q0_n );
bit_1 : entity work.ttl_74x74(basic)
   port map ( pr_n => '1', d => q1_n, clk => q0_n, clr_n => reset,
              q => q1, q_n => q1_n );

library company_lib, project_lib;
use company_lib.in_pad, company_lib.out_pad, project_lib.all;

context phantom_context is
   library ieee, IP_worx, phantom_lib;
   use ieee.std_logic_1164.all;
   use IP_worx.all, phantom_lib.all;
end context phantom_context;

constant operand1 : in integer
operand1 : integer
constant tag : in bit_vector(31 downto 16)
tag : bit_vector(31 downto 16)
constant trace : in boolean := false
trace : boolean := false

variable average : out real
average : out real
variable identifier : inout string
identifier : inout string

signal clk : out bit
signal data_in : in std_ulogic_vector
signal data_in : std_ulogic_vector

stimulate ( s, 5 ns, 3 );
stimulate ( target => s, delay => 5 ns, cycles => 3 );
stimulate ( s, 10 ns, 1 );
stimulate ( s, 10 ns );
stimulate ( target => s, delay => 10 ns, cycles => open );
stimulate ( target => s, cycles => open, delay => 10 ns );
stimulate ( target => s, delay => 10 ns );
stimulate ( s, 1 ns, 15 );
stimulate ( target => s, delay => open, cycles => 15 );
stimulate ( target => s, cycles => 15 );
stimulate ( s, cycles => 15 );

swapper : process is
begin
   shuffle_bytes ( ext_data, int_data, swap_control, Tpd_swap );
   wait on ext_data, swap_control;
end process swapper;

product_size := approx_log_2(multiplicand)
                + approx_log_2(multiplier);

assert now <= 20 ms
   report "simulation time has exceeded 20 ms";

package EMS_types is
   type engine_speed is range 0 to integer'high
     units rpm;
     end units engine_speed;
   constant peak_rpm : engine_speed := 6000 rpm;
   type gear is (first, second, third, fourth, reverse);
end package EMS_types;
work.EMS_types.engine_speed
work.EMS_types.rpm            work.EMS_types.peak_rpm
work.EMS_types.gear           work.EMS_types.first
work.EMS_types.second         work.EMS_types.third
work.EMS_types.fourth         work.EMS_types.reverse

procedure increment ( num : inout integer );

function odd ( num : integer ) return boolean;

constant e : real;

use work.EMS_types.engine_speed;

library DSP_lib;
use DSP_lib.systolic_FFT, DSP_lib.DSP_types.all;

subtype wired_and_logic is wired_and tri_state_logic;
signal synch_control : wired_and_logic := '0';

synch_T <= not synch_T'driving_value;

assert std.env.resolution_limit < 1.0E-9 sec;

to_hstring(B"ZZZZ_0100") = "Z4"
to_hstring(B"XX_L01H") = to_hstring(B"XXXX_L01H") = "X3"
to_hstring(B"01_00ZZ") = to_hstring(B"0001_00ZZ") = "1X"

use ieee.numeric_std.all;
...
signal a, b, s : unsigned(23 downto 0);
signal carry_in, carry_out : std_ulogic;
...
(carry_out, s) < = a + b + carry_in;

D_ff : process (clk) is
begin
   if rising_edge(clk) then
        if en then
    q <= To_X01(d);
     end if;
   end if;
end process D_ff;

D_ff : process (clk) is
begin
   if rising_edge(clk) and To_X01(en) = '1' then
     q <= To_X01(d);
   end if;
end process D_ff;

signal a : sfixed(3 downto -6);
...
s <= resize(a*a, 7, -6);  -- resize using left and right bounds
s <= resize(a*a, s);      -- resize using bounds of s

signal x, y : float(7 downto -12)
...
y <= to_float(-1.0, y) when x < -1.0 else
     to_float(+1.0, y) when x > +1.0 else
     x;

alias received_source is received_packet.source;
alias received_dest is received_packet.dest;
alias received_flags is received_packet.flags;
alias received_payload is received_packet.payload;
alias received_checksum is received_packet.checksum;

alias received_AK is received_packet.flags(0);
alias received_ACKNO : bit_vector(2 downto 0)
         is received_packet.flags(1 to 3);
alias received_SEQNO : bit_vector(2 downto 0)
         is received_packet.flags(4 to 6);
alias received_UD is received_packet.flags(7);

alias cons is "&" [ character, string return string ];
report cons ( grade_char, "-grade" );

entity flipflop is
   generic ( Tpw_clk_h, T_pw_clk_l : delay_length := 3 ns );
   port ( clk, d : in bit;  q, q_n : out bit );
end entity flipflop;

clk_gen : entity work.clock_generator
   generic map ( period => 10 ns )
   port map ( clk => master_clk );

entity adder is
   generic ( data_length : positive );
   port ( a, b : in std_ulogic_vector(data_length - 1 downto 0);
          sum : out std_ulogic_vector(data_length - 1 downto 0) );
end entity adder;

io_control_reg : entity work.reg
   generic map ( width => 4 )
   port map ( d => data_out(3 downto 0),
              q(0) => io_en, q(1) => io_int_en,
              q(2) => io_dir, q(3) => io_mode,
              clk => io_write, reset => io_reset );

bv_mux : entity work.generic_mux2(rtl)
   generic map ( data_type => bit_vector(7 downto 0) )
   port map ( sel => sel, a => d_in1, b => d_in2,
                          z => d_out );

package int_stacks is new work.generic_stacks
   generic map ( size => 100, element_type => integer );
use int_stacks.all;
variable int_stack : stack_type;
...
push(int_stack, -1);

while not is_full(test_buffer) loop
   write(test_buffer, "00000000");
end loop;

procedure check_bv_setup is new check_setup
   generic map ( signal_type => bit_vector,
                 clk_type => bit, clk_active_value => '0',
                 T_su => 100ps );
...
check_bv_setup(s, clk);

function bv_increment(bv : bit_vector) return bit_vector is
   use ieee.numeric_bit_unsigned.all;
begin
   return bv + 1;
end function bv_increment;
...
val_counter : work.generic_counter(rtl)
   generic map ( count_type => bit_vector(9 downto 0),
                 reset_value => (others => '0'),
                 increment => bv_increment )
   port map ( clk => clk, reset => reset, data => val_count );

use ieee.numeric_std.all;
package unsigned_dictionaries is new work.dictionaries
   generic map ( size => 1000,
                 element_type => unsigned(63 downto 0),
                 key_type => string,
                 key_of => to_hstring,
                 "<" => ">" );

package float_generic_math_ops is
   generic ( package float_pkg_for_math is
               new ieee.float_generic_pkg generic map (<>) );
   use fixed_pkg_for_math.all;
   function exp ( x : float ) return float;
   function log ( x : float ) return float;
   ...
end package float_generic_math_ops;
package float_math_ops is new float_generic_math_ops
   generic map ( float_pkg_for_math => ieee.float_pkg );

component magnitude_comparator is
   generic ( width : positive;  Tpd : delay_length );
   port ( a, b : in std_ulogic_vector(width - 1 downto 0);
          a_equals_b, a_less_than_b : out std_ulogic );
end component magnitude_comparator;

position_comparator : component magnitude_comparator
   generic map ( width => current_position'length, Tpd => 12 ns )
   port map ( a => current_position, b => upper_limit,
              a_less_than_b => position_ok, a_equals_b => open );

package small_number_pkg is
   subtype small_number is natural range 0 to 255;
   component adder is
     port ( a, b : in small_number;  s : out small_number );
   end component adder;
end package small_number_pkg;

library dsp_lib;
configuration digital_filter_rtl of digital_filter is
   for register_transfer
     for coeff_1_multiplier : multiplier
       use entity dsp_lib.fixed_point_mult(algorithmic);
     end for;
   end for;
end configuration digital_filter_rtl;

library dsp_lib;
configuration digital_filter_std_cell of digital_filter is
   for register_transfer
     for coeff_1_multiplier : multiplier
       use configuration dsp_lib.fixed_point_mult_std_cell;
     end for;
   end for;
end configuration digital_filter_std_cell;

library dsp_lib;
architecture register_transfer of digital_filter is
   ...
begin
   coeff_1_multiplier :
     configuration dsp_lib.fixed_point_mult_std_cell
       port map ( ... );
   ...
end architecture register_transfer;

use entity work.multiplexer
   generic map ( Tpd => 3.5 ns );

generic map ( Tpd_01 => open, Tpd_10 => open )
port map ( a => a, b => b, c => c, d => open, y => y )

for interface_decoder : decoder_2_to_4
   use entity work.decoder_3_to_8(basic)
     generic map ( Tpd_01 => prop_delay, Tpd_10 => prop_delay )
     port map ( s0 => in0, s1 => in1, s2 => '0',
                enable => '1',
                y0 => out0, y1 => out1, y2 => out2, y3 => out3,
                y4 => open, y5 => open, y6 => open, y7 => open );
end for;

configuration rebound of computer_system is
   for structure
     for interface_decoder : decoder_2_to_4
       generic map ( Tpd_01 => 4.3 ns, Tpd_10 => 3.8 ns );
     end for;
   end for;
end configuration rebound;

inverter_array : for index in data_in'range generate
   inv : component inverter
     port map ( i => data_in(index), y_n => data_out_n(index) );
end generate inverter_array;

direct_clock : if positive_clock generate
   internal_clock <= external_clock;
else generate
   clock_inverter : component inverter
     port map ( i => external_clock, y => internal_clock );
end generate inverting_clock;

for synch_delay_line(1)
   for delay_ff : d_ff
     use entity parts_lib.d_flipflop(low_input_load);
        end for;
end for;
for synch_delay_line(2 to 4)
   for delay_ff : d_ff
     use entity parts_lib.d_flipflop(standard_input_load);
   end for;
end for;

direct_clock : if noninverting : positive_clock generate
   internal_clock <= external_clock;
else inverting : generate
   clock_inverter : component inverter
     port map ( i => external_clock, y => internal_clock );
end generate inverting_clock;

for inverting_clock(inverting)
   for clock_inverter : inverter
     use entity parts_lib.inverter;
   end for;
end for;

type character_ptr is access character;
variable char : character_ptr := new character'(ETX);
...
char.all := 'A';

type string_ptr is access string;
variable str : string_ptr := new string'(" ");
...
str(1) := NUL;

z.re := x.re * y.re - x.im * y.im;
z.im := x.re * y.im + x.im * y.re;

type message_cell;
type message_ptr is access message_cell;
type message_cell is record
     source, destination : natural;
     data : bit_vector(0 to 255);
     next_cell : message_ptr;
   end record message_cell;
variable message_list : message_ptr;
...
message_list := new message_cell'( source => 1, destination => 5,
                                    data => (others => '0'),
                                    next_cell => message_list );

type real_file is file of real;
file sample_file : real_file open read_mode is "samples.dat";
...
read ( sample_file, x );

type bv_file is file of bit_vector;
file trace_file : bv_file open write_mode is "/tmp/trace.tmp";
...
write ( trace_file, addr & d_bus );

file_open ( status => waveform_status, f => waveform_file,
             external_name => "waveform", open_kind => read_mode);
assert waveform_status = open_ok
   report file_open_status'image(waveform_status)
          & " occurred opening waveform file" severity error;

use std.textio.all;
variable prompt_line, input_line : line;
variable number : integer;
...
write(prompt_line, string'("Enter a number:");
writeline(output, prompt_line);
readline(input, input_line);
read(input_line, number);

"   3500 ns 00111100 ok   "

package memories_support_1Kx24 is new work.memories_suppor
   generic map ( width => 24, depth => 10,
                 fixed_pkg => ieee.fixed_pkg,
                 float_pkg => ieee.float_pkg );
use memories_support_1Kx24.all;
package memories_1Kx24 is new work.memories
   generic map
     ( width => 24, depth => 10,
       control_type => bit,
       address_type => std_ulogic_vector(9 downto 0),
       data_type => std_ulogic_vector(23 downto 0) );

package memories_support_32x128 is new work.memories_suppor
   generic map ( width => 128, depth => 5,
                 fixed_pkg => ieee.fixed_pkg,
                 float_pkg => ieee.float_pkg );
use memories_support_32x128.all;
package memories_32x128 is new work.memories
   generic map
     ( width => 128, depth => 5,
       control_type => std_ulogic,
       address_type => unsigned(4 downto 0),
       data_type => float128 );

<<constant .test_bench.dp.d_width : positive>>
<<signal .test_bench.dp.d_bus : std_ulogic_vector(7 downto 0)>>
<<signal .test_bench.dp.adder(3).carry : std_ulogic>>

alias d_width is
    <<constant .test_bench.dp.d_width : positive>>;
alias d_bus is
   <<signal .test_bench.dp.d_bus : std_ulogic_vector(7 downto 0)>>;
alias carry is
   <<signal .test_bench.dp.adder(3).carry : std_ulogic>>;

<<constant dp.d_width : positive>>
<<signal dp.d_bus : std_ulogic_vector(7 downto 0)>>
<<signal dp.adder(3).carry : std_ulogic>>

reset <= force '1';
wait for 200 ns;
reset <= release;

alias mem_d is <<signal mem.d : std_logic_vector(7 downto 0)>>;
...
mem_d <= force out "ZZZZZZZZ";
mem_d <= force in "ZZZZZZZZ";
...
mem_d <= release out;
mem_d <= release in;

configuration verifying of bus_interface is
   use vunit verify_protocol;
   for behavior
   end for;
end configuration verifying;

for ext : ext_interface
   use entity bus_interface(behavior);
   use vunit verify_protocol;
end for;

type shared_integer is protected
   procedure set ( i : integer );
   impure function get return integer;
end protected shared_integer;
type shared_integer is protected body
   variable value : integer;
   procedure set ( i : integer ) is
   begin
     value := i;
   end procedure set;
   impure function get return integer is
   begin
     return value;
   end function get;
end protected body shared_integer;

word'path_name = ":proj_lib:cpu_types:word"
mult_unsigned'path_name =
":proj_lib:bit_vector_signed_arithmetic:"
     & "mult_unsigned[bit_vector, bit_vector return bit_vector]:"
bv2'path_name =
":proj_lib:bit_vector_signed_arithmetic:"
     & "mult_unsigned[bit_vector, bit_vector return bit_vector]:bv2"
next_test_case'path_name =
":tes_tbench:stim_gen:next_test_case"
next_test_case'instance_name =
":test_bench(test_rtl):stim_gen:next_test_case"
get_ID'path_name =
":test_bench:stim_gen:ID_manager:"
     & "get_ID[return natural:"
get_ID'instance_name =
":test_bench(test_rtl):stim_gen:ID_manager:"
     & "get_ID[return natural]:"

val0_reg'path_name = ":test_bench:dut:val0_reg:"
val0_reg'instance_name =
     ":test_bench(counter_test)"
     & ":dut@counter(registered):val0_reg@reg4(struct):"
bit0'path_name = ":test_bench:dut:val1_reg:bit0"
bit0'instance_name =
     ":test_bench(counter_test)"
     & ":dut@counter(registered):val1_reg@reg4(struct)"
     & ":bit0@edge_triggered_dff(behavioral):"
clr'path_name = ":test_bench:dut:val1_reg:bit0:clr"
clr'instance_name =
     ":test_bench(counter_test)"
     & ":dut@counter(registered):val1_reg@reg4(struct)"
     & ":bit0@edge_triggered_dff(behavioral):clr"

attribute load : capacitance;
attribute load of d_in : signal is 3 pF;

type area is range 0 to integer'high
   units um_2;
   end units area;
attribute cell_area : area;
attribute cell_area of library_cell : architecture is 15 um_2;

attribute optimization of
   test_empty [ list_ptr, boolean ] : procedure is "inline";

group statement_set is ( label, label <> );
group steps_1_and_2 : statement_set ( step_1, step_2 );
attribute resource_allocation of steps_1_and_2 : group is
             max_sharing;

logic_block : process (enable_n, adr, reg1, reg2) is
begin
   if std_match(enable_n, '0') then
     if std_match(adr, '0') then
       dat_o <= reg1;
     else
       dat_o <= reg2;
     end if;
     ack_o <= '1';
   else
     dat_o <= "ZZZZZZZZ";
     ack_o <= 'Z';
   end if;
end process logic_block;

en_reg : process ( clk ) is
begin
   if rising_edge(clk) then
     if en = '1' then
       reg_out <= data_in;
     end if;
   end if;
end process en_reg;

type RAM_type is array (0 to 8191) of signed(15 downto 0);
signal RAM : RAM_type := (others => X"0000");

type decoder_array is array (0 to 15) of std_ulogic_vector(1 to 7);
constant decoder_ROM : decoder_array :=
   ( 0 => "0111111", 1 => "0000110",
     2 => "1011011", 3 => "1001111",
     4 => "1100110", 5 => "1101101",
     6 => "1111101", 7 => "0000111",
     8 => "1111111", 9 => "1101111",
     others => "1000000" );
...
decoder : seg <= decoder_ROM(to_integer(bcd));

attribute enum_encoding of state : type is "00 01 11";

attribute fsm_state of state : type is "00 01 11";

attribute fsm_state of
   current_state, next_state : signal is "00 01 11";

signal serial_bus : wired_or_bit bus;
signal d_node : unique_bit register;

vote <= 3 after 2 us, null after 5 us;

inverting_latch : block ( en ) is
begin
   q_out_n <= guarded not d_in;
end block inverting_latch;

disconnect source1 : wired_word after 3.5 ns;
disconnect others : wired_word after 3.2 ns;
disconnect all : wired_bit after 2.8 ns;

inverting_ff : block is
   signal q_internal : bit;
begin
   the_dff : component dff
     port map ( clk => sys_clk, d => d_in, q => q_internal );
   the_inverter : component inverter
     port map ( i => q_internal, y => q_out_n );
end block inverting_ff;

for inverting_ff
   for the_dff : dff
     use entity work.d_flipflop(basic);
   end for;
   for the_inverter : inverter
     use entity work.inverter(basic);
   end for;
end for;

architecture rtl of ethernet_mac is
'protect data_keyowner = "IP_werx"
'protect data_keyname = "IP_werx_sim"
'protect data_method = "3des-cbc"
'protect begin
   signal fifo_enable : std_ulogic;
   ...
begin
   rx_fifo : IP_werx_fifo
     port map ( ... );
   ...
'protect end
end architecture rtl;

architecture rtl of ethernet_mac is
'protect key_keyowner = "Aero Industries"
'protect key_keyname = "Aero Design"
'protect key_method = "pgp-rsa"
'protect key_block
'protect data_method = "aes192-cbc"
'protect encoding = (enctype="base64")
'protect begin
   signal fifo_enable : std_ulogic;
   ...
begin
   rx_fifo : IP_werx_fifo
     port map ( ... );
   ...
'protect end
end architecture rtl;

architecture vhpi_implementation of control is
   attribute foreign of vhpi_implementation : architecture is
"VHPIDIRECT $VHPIUSERLIB/control.so control_elab control_exec";
begin
end architecture vhpi_implementation;

architecture vhpi_implementation of control is
   attribute foreign of vhpi_implementation : architecture is
      "VHPI control_lib control_model";
begin
end architecture vhpi_implementation;

control_lib control_model vhpiArchF control_elab control_exe

function cvt_to_bit ( s : std_ulogic ) return bit is
begin
   return To_bit(s);
end function cvt_to_bit;

gate1 : component nand2
   port map ( a => To_stdulogic(s1), b => To_stdulogic(s2),
              cvt_to_bit(y_n) => s3 );